Beyond Moore
The roadmap past A14 logic depends on materials silicon can't provide. Atomically thin 2D semiconductors are the most credible path forward, but only if someone makes them manufacturable at wafer scale. Matter42 is building the industrial process-intelligence platform to do it.
Scaling inflection
The ceiling
0160 mV/dec
Silicon’s thermionic floor blocks further voltage scaling without runaway leakage.
The opening
02<1 mV/dec
MoS2 and MoTe2 stacks switch below the silicon floor, with channels demonstrated at ~0.34 nm.
The path
03Process IP
Convert the recipe surface into measurable, patentable process windows at wafer scale.
The forcing function
Data-center power is now the binding constraint on compute. Silicon can't keep dropping voltage without leakage, and geometry alone won't recover the economics.
AI infrastructure is repricing logic by joules per inference.
The IEA projects global data-center demand at roughly 945 TWh by 2030, with hyperscaler electricity bills rising by tens of billions of dollars a year. Lower-voltage 2D channels move that number directly.
The physics is settled. Manufacturing is what is left.
Vertical MoS2 transistors have hit ~0.34 nm channel lengths and switched below silicon’s 60 mV/dec floor. IRDS 2024 puts 2D channel logic in commercial production around 2034; imec’s public roadmap targets A2 around 2039. None of the open problems are physics. They are process.
The open IP landscape
Headline devices prove the physics. They do not close wafer-scale growth, transferability, or the full process window, and that is where defensible IP lives.
At IEDM 2025, imec with TSMC reported a dual-gated WSe2 pFET hitting roughly 690 µA/µm drive current. The same week, imec with Intel showed damascene-style top contacts on WS2, MoS2, and WSe2. In both cases TSMC and Intel grew the 2D layers themselves; the consortium did not. The leading 2D-FET research consortium in the world still treats wafer-scale 2D growth as a separate, unsolved problem.
That gap is the chokepoint of the entire 2D-FET supply chain.
Advisor read
Tony Heinz, Stanford University and SLAC
“The work to date, even in industry, is still focused largely at the single device level and not on scalability of a complete manufacturable process. We are perhaps closer to what you see in those photos of a germanium point contact transistor at Bell Labs in the 1950s than to current scaled Si IC technology. The corresponding IP for this new platform is also yet to be developed.”
IP whitespace map
Each row is a manufacturability problem. The darker the right edge, the larger the unmapped process surface Matter42 can convert into data, models, and patents.
Wafer-scale growth
Single-crystal monolayers on amorphous substrates under 400 °C
Contacts
Sub-kΩ·µm contacts in a reproducible, high-yield process
Gate dielectrics
Threshold-voltage programmability across n- and p-FETs
Layer control
Layer-number, mobility, and defect-density surfaces with tight wafer-scale spread
Strain and alloying
TMD alloying analogous to III–V technology, plus device-level strain engineering
Layer transfer
Damage- and residue-free release with CFET-scale alignment
Demo
Isolated films
Window
Narrow windows
Scale
Above BEOL budget
Single-crystal monolayers on amorphous substrates under 400 °C
Demo
Bi-MoS2 records
Window
Module-specific
Scale
kΩ·µm at scale
Sub-kΩ·µm contacts in a reproducible, high-yield process
Demo
Seed layers
Window
Narrow windows
Scale
Variability open
Threshold-voltage programmability across n- and p-FETs
Demo
Point demos
Window
Tool-specific
Scale
Uniformity open
Layer-number, mobility, and defect-density surfaces with tight wafer-scale spread
Demo
Underexplored
Window
Mostly blank
Scale
Not mapped
TMD alloying analogous to III–V technology, plus device-level strain engineering
Demo
Lab routes
Window
No yield baseline
Scale
Alignment open
Damage- and residue-free release with CFET-scale alignment
Industrial process intelligence
Manual campaigns trace one thin line through a process space that couples 20 orders of magnitude in time and 10 in space. Atlas pairs agentic AI, multimodal characterization, ML-accelerated simulation, and a closed-loop lab so each experiment updates the map.
MoS2 MOCVD growth landscape
S/Mo is log-scaled so the optimum near 18 and the high-ratio backfire region both sit on screen.
Atlas
Ingests Raman, PL, XPS, TEM, optical, and IR data alongside literature and simulation, and proposes calibrated process parameters back. Already runs defect characterization on TMD Raman maps roughly 100 times faster than the manual workflow.
Closed-loop lab
A 300 mm-capable reactor with on-tool diagnostics, planned and re-planned by Atlas between runs. Designed for roughly 3,000 growth runs a week, with recipes that move between tools without heavy re-qualification.
Data moat
Atlas is over 95% simulation-trained and fine-tuned on targeted experiments. That is the throughput a high-dimensional landscape needs to be mapped instead of sampled.
Proving ground
WS2, MoS2, and WSe2 are crowded on purpose: a platform only matters if it wins on the materials the industry already needs.
WS2
n-type, broad baselinesThe leading n-type candidate, with deep literature baselines and the widest range of published contact solutions. It is the place to anchor the platform against industry numbers.
MoS2
n-type benchmarkThe most-studied monolayer semiconductor. If we can’t beat TSMC, Intel, and imec on their own published numbers here, the platform claim doesn’t hold.
WSe2
p-type gatekeeperThe only p-type 2D material being actively explored at wafer scale. Without it, complementary 2D CMOS doesn’t close, and neither does any complete logic stack.
Long arc · materials
The same engine extends to roughly 100 binary TMDs and the wider 2D family, including wafer-scale 2D superconductors recently grown by MOCVD. Almost no incumbent process IP exists there yet.
Adjacent vertical
Monolayer MoS2 FETs have shown radiation tolerance roughly two orders of magnitude above silicon-based rad-hard floors. A structural advantage for satellite constellations and deep-space defense assets.
Roadmap
We are building toward a position where process IP gets generated continuously from structured experiments, not occasionally from artisanal breakthroughs.
Extend Atlas from characterization agents to wafer-scale synthesis models, and stand up the first closed-loop reactor.
Co-build the first process maps with academic and industrial partners where option value is concrete and measurable.
Pour the baseline data layer from literature, partner archives, simulations, and targeted in-house runs.
Strategic partners
Device physics has made 2D channels credible. The window for capturing the manufacturing IP is open now. We are looking for investors and semiconductor partners willing to back the platform that converts this process surface into IP before the eventual foundries have to license it.
Copyright © 2026 Matter42. All rights reserved.
Beyond Moore
The roadmap past A14 logic depends on materials silicon can't provide. Atomically thin 2D semiconductors are the most credible path forward, but only if someone makes them manufacturable at wafer scale. Matter42 is building the industrial process-intelligence platform to do it.
Scaling inflection
The ceiling
0160 mV/dec
Silicon’s thermionic floor blocks further voltage scaling without runaway leakage.
The opening
02<1 mV/dec
MoS2 and MoTe2 stacks switch below the silicon floor, with channels demonstrated at ~0.34 nm.
The path
03Process IP
Convert the recipe surface into measurable, patentable process windows at wafer scale.
The forcing function
Data-center power is now the binding constraint on compute. Silicon can't keep dropping voltage without leakage, and geometry alone won't recover the economics.
AI infrastructure is repricing logic by joules per inference.
The IEA projects global data-center demand at roughly 945 TWh by 2030, with hyperscaler electricity bills rising by tens of billions of dollars a year. Lower-voltage 2D channels move that number directly.
The physics is settled. Manufacturing is what is left.
Vertical MoS2 transistors have hit ~0.34 nm channel lengths and switched below silicon’s 60 mV/dec floor. IRDS 2024 puts 2D channel logic in commercial production around 2034; imec’s public roadmap targets A2 around 2039. None of the open problems are physics. They are process.
The open IP landscape
Headline devices prove the physics. They do not close wafer-scale growth, transferability, or the full process window, and that is where defensible IP lives.
At IEDM 2025, imec with TSMC reported a dual-gated WSe2 pFET hitting roughly 690 µA/µm drive current. The same week, imec with Intel showed damascene-style top contacts on WS2, MoS2, and WSe2. In both cases TSMC and Intel grew the 2D layers themselves; the consortium did not. The leading 2D-FET research consortium in the world still treats wafer-scale 2D growth as a separate, unsolved problem.
That gap is the chokepoint of the entire 2D-FET supply chain.
Advisor read
Tony Heinz, Stanford University and SLAC
“The work to date, even in industry, is still focused largely at the single device level and not on scalability of a complete manufacturable process. We are perhaps closer to what you see in those photos of a germanium point contact transistor at Bell Labs in the 1950s than to current scaled Si IC technology. The corresponding IP for this new platform is also yet to be developed.”
IP whitespace map
Each row is a manufacturability problem. The darker the right edge, the larger the unmapped process surface Matter42 can convert into data, models, and patents.
Wafer-scale growth
Single-crystal monolayers on amorphous substrates under 400 °C
Contacts
Sub-kΩ·µm contacts in a reproducible, high-yield process
Gate dielectrics
Threshold-voltage programmability across n- and p-FETs
Layer control
Layer-number, mobility, and defect-density surfaces with tight wafer-scale spread
Strain and alloying
TMD alloying analogous to III–V technology, plus device-level strain engineering
Layer transfer
Damage- and residue-free release with CFET-scale alignment
Demo
Isolated films
Window
Narrow windows
Scale
Above BEOL budget
Single-crystal monolayers on amorphous substrates under 400 °C
Demo
Bi-MoS2 records
Window
Module-specific
Scale
kΩ·µm at scale
Sub-kΩ·µm contacts in a reproducible, high-yield process
Demo
Seed layers
Window
Narrow windows
Scale
Variability open
Threshold-voltage programmability across n- and p-FETs
Demo
Point demos
Window
Tool-specific
Scale
Uniformity open
Layer-number, mobility, and defect-density surfaces with tight wafer-scale spread
Demo
Underexplored
Window
Mostly blank
Scale
Not mapped
TMD alloying analogous to III–V technology, plus device-level strain engineering
Demo
Lab routes
Window
No yield baseline
Scale
Alignment open
Damage- and residue-free release with CFET-scale alignment
Industrial process intelligence
Manual campaigns trace one thin line through a process space that couples 20 orders of magnitude in time and 10 in space. Atlas pairs agentic AI, multimodal characterization, ML-accelerated simulation, and a closed-loop lab so each experiment updates the map.
MoS2 MOCVD growth landscape
S/Mo is log-scaled so the optimum near 18 and the high-ratio backfire region both sit on screen.
Atlas
Ingests Raman, PL, XPS, TEM, optical, and IR data alongside literature and simulation, and proposes calibrated process parameters back. Already runs defect characterization on TMD Raman maps roughly 100 times faster than the manual workflow.
Closed-loop lab
A 300 mm-capable reactor with on-tool diagnostics, planned and re-planned by Atlas between runs. Designed for roughly 3,000 growth runs a week, with recipes that move between tools without heavy re-qualification.
Data moat
Atlas is over 95% simulation-trained and fine-tuned on targeted experiments. That is the throughput a high-dimensional landscape needs to be mapped instead of sampled.
Proving ground
WS2, MoS2, and WSe2 are crowded on purpose: a platform only matters if it wins on the materials the industry already needs.
WS2
n-type, broad baselinesThe leading n-type candidate, with deep literature baselines and the widest range of published contact solutions. It is the place to anchor the platform against industry numbers.
MoS2
n-type benchmarkThe most-studied monolayer semiconductor. If we can’t beat TSMC, Intel, and imec on their own published numbers here, the platform claim doesn’t hold.
WSe2
p-type gatekeeperThe only p-type 2D material being actively explored at wafer scale. Without it, complementary 2D CMOS doesn’t close, and neither does any complete logic stack.
Long arc · materials
The same engine extends to roughly 100 binary TMDs and the wider 2D family, including wafer-scale 2D superconductors recently grown by MOCVD. Almost no incumbent process IP exists there yet.
Adjacent vertical
Monolayer MoS2 FETs have shown radiation tolerance roughly two orders of magnitude above silicon-based rad-hard floors. A structural advantage for satellite constellations and deep-space defense assets.
Roadmap
We are building toward a position where process IP gets generated continuously from structured experiments, not occasionally from artisanal breakthroughs.
Extend Atlas from characterization agents to wafer-scale synthesis models, and stand up the first closed-loop reactor.
Co-build the first process maps with academic and industrial partners where option value is concrete and measurable.
Pour the baseline data layer from literature, partner archives, simulations, and targeted in-house runs.
Strategic partners
Device physics has made 2D channels credible. The window for capturing the manufacturing IP is open now. We are looking for investors and semiconductor partners willing to back the platform that converts this process surface into IP before the eventual foundries have to license it.
Copyright © 2026 Matter42. All rights reserved.
