Patent
US 9,236,477A GRAPHENE TRANSISTOR WITH A SUBLITHOGRAPHIC CHANNEL WIDTH
Jack O. Chu
US
Copyright © 2026 Matter42. All rights reserved.
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US 9,236,477Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 0 A is a top-down view of the first exemplary structure after formation of a dielectric spacer and a gate structure including a gate dielectric and a …
FIG. 2A is a top-down view of the first exemplary structure after formation of inverted U- shaped silicon-carbon alloy structures by selective epitaxy according …
FIG. 3A is a top-down view of the first exemplary structure after truncation of end portions of the inverted U-shaped silicon-carbon alloy structures and …
FIG. 4A is a top-down view of the first exemplary structure after formation of silicon- carbon alloy fins by removal of top portions of the inverted U-shaped …
FIG. 5 A is a top-down view of the first exemplary structure after replacement of semiconductor fins with dielectric material fins according to an embodiment of …
FIG. 6A is a top-down view of the first exemplary structure after formation of a patterned mask layer and recessing of the planarization dielectric layer and …
FIG. 7A is a top-down view of the first exemplary structure after formation of graphene layers from physically exposed surface portions of the silicon-carbon …
FIG. 8A is a top-down view of the first exemplary structure after masking portions of the graphene layers to be employed as channel portions with a masking …
FIG. 9A is a top-down view of the first exemplary structure after depositing a conductive material to form a source contact structure and a drain contact …
FIG. 10 B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B' of
FIG. 12A is a top-down view of a second variation of the first exemplary structure according to an embodiment of the present disclosure. [0037]
FIG. 13A is a top-down view of a third variation of the first exemplary structure according to an embodiment of the present disclosure. [0040]
FIG. 14A is a top-down view of a second exemplary structure after formation of graphene layers according to an embodiment of the present disclosure. [0043]
FIG. 15A is a top-down view of the second exemplary structure after formation of a source contact structure, a drain contact structure, a dielectric spacer, …
FIG. 16A is a top-down view of a variation of the second exemplary structure according to an embodiment of the present disclosure. [0049]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a structure comprising: forming a semiconductor fin on an insulator layer; forming a silicon-carbon alloy structure by selective epitaxy of a silicon-carbon alloy on surfaces of said semiconductor fin; depositing a planarization dielectric layer around said silicon-carbon alloy structure and above said insulator layer; removing a horizontal portion of said silicon-carbon alloy structure, wherein a remaining vertical portion of said silicon-carbon alloy structure constitutes a silicon-carbon alloy fin; and converting a set of at least one contiguous physically exposed surface portion of said silicon-carbon alloy fin into a graphene layer by an anneal process. withdrawn
The method of Claim 1, further comprising forming a gate structure comprising a stack of a gate dielectric and a gate electrode across said silicon-carbon alloy fin and over said planarization dielectric layer and said graphene layer. withdrawn
The method of Claim 1, further comprising recessing portions of said planarization dielectric layer selective to said silicon-carbon alloy fin prior to formation of said graphene layer. withdrawn
The method of Claim 1, wherein said graphene layer is formed by evaporation of silicon atoms from said set of at least one contiguous physically exposed surface portion of said silicon-carbon alloy fin during said anneal process. withdrawn
The method of Claim 1, further comprising replacing said semiconductor fin with a dielectric material portion prior to performing said anneal process. withdrawn
The method of Claim 1, wherein said semiconductor fin is present on said silicon-carbon alloy fin during said anneal process. withdrawn
The method of Claim 1, wherein said set of at least one contiguous physically exposed surface portion consists of a surface portion underlying a top surface of said silicon- carbon alloy fin. withdrawn
A semiconductor structure comprising: a silicon-carbon alloy fin located on an insulator layer; a graphene layer located on a top surface of said silicon-carbon alloy fin; a dielectric material layer contacting said silicon-carbon alloy fin, wherein a horizontal interface between said graphene layer and said silicon-carbon alloy fin is recessed relative to a top surface of said dielectric material layer; and a gate structure comprising a stack of a gate dielectric and a gate electrode and straddling said silicon-carbon alloy fin and contacting said top surface of said dielectric material layer.
The semiconductor structure of Claim 11, wherein an entirety of said top surface of said silicon-carbon alloy fin is in contact with said graphene layer.
(Cu rr ently Amended) The semiconductor structure of Claim 11, wherein said graphene layer include includes a vertical portion that contacts a lengthwise sidewall surface of said silicon-carbon alloy fin.
The semiconductor structure of Claim 11, wherein an entirety of said graphene layer is located on, and above, said top surface of said silicon-carbon alloy fin and has a same width throughout.
The semiconductor structure of Claim 11, further comprising a dielectric material portion in contact with a lengthwise sidewall surface of said silicon-carbon alloy fin and a vertical surface of said dielectric material layer.
The semiconductor structure of Claim 11, further comprising a semiconductor material portion in epitaxial alignment with said silicon-carbon alloy fin and in contact with a lengthwise sidewall surface of said silicon-carbon alloy fin and a vertical surface of said dielectric material
Layer stacks claimed or described, ordered top of device to substrate.
graphene fin field-effect transistor with sublithographic channel width
Materials described outside the worked examples.
silicon-carbon alloy
SiC
semiconductor fin material
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 1050–1450 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,236,477Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 0 A is a top-down view of the first exemplary structure after formation of a dielectric spacer and a gate structure including a gate dielectric and a …
FIG. 2A is a top-down view of the first exemplary structure after formation of inverted U- shaped silicon-carbon alloy structures by selective epitaxy according …
FIG. 3A is a top-down view of the first exemplary structure after truncation of end portions of the inverted U-shaped silicon-carbon alloy structures and …
FIG. 4A is a top-down view of the first exemplary structure after formation of silicon- carbon alloy fins by removal of top portions of the inverted U-shaped …
FIG. 5 A is a top-down view of the first exemplary structure after replacement of semiconductor fins with dielectric material fins according to an embodiment of …
FIG. 6A is a top-down view of the first exemplary structure after formation of a patterned mask layer and recessing of the planarization dielectric layer and …
FIG. 7A is a top-down view of the first exemplary structure after formation of graphene layers from physically exposed surface portions of the silicon-carbon …
FIG. 8A is a top-down view of the first exemplary structure after masking portions of the graphene layers to be employed as channel portions with a masking …
FIG. 9A is a top-down view of the first exemplary structure after depositing a conductive material to form a source contact structure and a drain contact …
FIG. 10 B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B' of
FIG. 12A is a top-down view of a second variation of the first exemplary structure according to an embodiment of the present disclosure. [0037]
FIG. 13A is a top-down view of a third variation of the first exemplary structure according to an embodiment of the present disclosure. [0040]
FIG. 14A is a top-down view of a second exemplary structure after formation of graphene layers according to an embodiment of the present disclosure. [0043]
FIG. 15A is a top-down view of the second exemplary structure after formation of a source contact structure, a drain contact structure, a dielectric spacer, …
FIG. 16A is a top-down view of a variation of the second exemplary structure according to an embodiment of the present disclosure. [0049]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a structure comprising: forming a semiconductor fin on an insulator layer; forming a silicon-carbon alloy structure by selective epitaxy of a silicon-carbon alloy on surfaces of said semiconductor fin; depositing a planarization dielectric layer around said silicon-carbon alloy structure and above said insulator layer; removing a horizontal portion of said silicon-carbon alloy structure, wherein a remaining vertical portion of said silicon-carbon alloy structure constitutes a silicon-carbon alloy fin; and converting a set of at least one contiguous physically exposed surface portion of said silicon-carbon alloy fin into a graphene layer by an anneal process. withdrawn
The method of Claim 1, further comprising forming a gate structure comprising a stack of a gate dielectric and a gate electrode across said silicon-carbon alloy fin and over said planarization dielectric layer and said graphene layer. withdrawn
The method of Claim 1, further comprising recessing portions of said planarization dielectric layer selective to said silicon-carbon alloy fin prior to formation of said graphene layer. withdrawn
The method of Claim 1, wherein said graphene layer is formed by evaporation of silicon atoms from said set of at least one contiguous physically exposed surface portion of said silicon-carbon alloy fin during said anneal process. withdrawn
The method of Claim 1, further comprising replacing said semiconductor fin with a dielectric material portion prior to performing said anneal process. withdrawn
The method of Claim 1, wherein said semiconductor fin is present on said silicon-carbon alloy fin during said anneal process. withdrawn
The method of Claim 1, wherein said set of at least one contiguous physically exposed surface portion consists of a surface portion underlying a top surface of said silicon- carbon alloy fin. withdrawn
A semiconductor structure comprising: a silicon-carbon alloy fin located on an insulator layer; a graphene layer located on a top surface of said silicon-carbon alloy fin; a dielectric material layer contacting said silicon-carbon alloy fin, wherein a horizontal interface between said graphene layer and said silicon-carbon alloy fin is recessed relative to a top surface of said dielectric material layer; and a gate structure comprising a stack of a gate dielectric and a gate electrode and straddling said silicon-carbon alloy fin and contacting said top surface of said dielectric material layer.
The semiconductor structure of Claim 11, wherein an entirety of said top surface of said silicon-carbon alloy fin is in contact with said graphene layer.
(Cu rr ently Amended) The semiconductor structure of Claim 11, wherein said graphene layer include includes a vertical portion that contacts a lengthwise sidewall surface of said silicon-carbon alloy fin.
The semiconductor structure of Claim 11, wherein an entirety of said graphene layer is located on, and above, said top surface of said silicon-carbon alloy fin and has a same width throughout.
The semiconductor structure of Claim 11, further comprising a dielectric material portion in contact with a lengthwise sidewall surface of said silicon-carbon alloy fin and a vertical surface of said dielectric material layer.
The semiconductor structure of Claim 11, further comprising a semiconductor material portion in epitaxial alignment with said silicon-carbon alloy fin and in contact with a lengthwise sidewall surface of said silicon-carbon alloy fin and a vertical surface of said dielectric material
Layer stacks claimed or described, ordered top of device to substrate.
graphene fin field-effect transistor with sublithographic channel width
Materials described outside the worked examples.
silicon-carbon alloy
SiC
semiconductor fin material
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 1050–1450 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,236,477Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 0 A is a top-down view of the first exemplary structure after formation of a dielectric spacer and a gate structure including a gate dielectric and a …
FIG. 2A is a top-down view of the first exemplary structure after formation of inverted U- shaped silicon-carbon alloy structures by selective epitaxy according …
FIG. 3A is a top-down view of the first exemplary structure after truncation of end portions of the inverted U-shaped silicon-carbon alloy structures and …
FIG. 4A is a top-down view of the first exemplary structure after formation of silicon- carbon alloy fins by removal of top portions of the inverted U-shaped …
FIG. 5 A is a top-down view of the first exemplary structure after replacement of semiconductor fins with dielectric material fins according to an embodiment of …
FIG. 6A is a top-down view of the first exemplary structure after formation of a patterned mask layer and recessing of the planarization dielectric layer and …
FIG. 7A is a top-down view of the first exemplary structure after formation of graphene layers from physically exposed surface portions of the silicon-carbon …
FIG. 8A is a top-down view of the first exemplary structure after masking portions of the graphene layers to be employed as channel portions with a masking …
FIG. 9A is a top-down view of the first exemplary structure after depositing a conductive material to form a source contact structure and a drain contact …
FIG. 10 B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B' of
FIG. 12A is a top-down view of a second variation of the first exemplary structure according to an embodiment of the present disclosure. [0037]
FIG. 13A is a top-down view of a third variation of the first exemplary structure according to an embodiment of the present disclosure. [0040]
FIG. 14A is a top-down view of a second exemplary structure after formation of graphene layers according to an embodiment of the present disclosure. [0043]
FIG. 15A is a top-down view of the second exemplary structure after formation of a source contact structure, a drain contact structure, a dielectric spacer, …
FIG. 16A is a top-down view of a variation of the second exemplary structure according to an embodiment of the present disclosure. [0049]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a structure comprising: forming a semiconductor fin on an insulator layer; forming a silicon-carbon alloy structure by selective epitaxy of a silicon-carbon alloy on surfaces of said semiconductor fin; depositing a planarization dielectric layer around said silicon-carbon alloy structure and above said insulator layer; removing a horizontal portion of said silicon-carbon alloy structure, wherein a remaining vertical portion of said silicon-carbon alloy structure constitutes a silicon-carbon alloy fin; and converting a set of at least one contiguous physically exposed surface portion of said silicon-carbon alloy fin into a graphene layer by an anneal process. withdrawn
The method of Claim 1, further comprising forming a gate structure comprising a stack of a gate dielectric and a gate electrode across said silicon-carbon alloy fin and over said planarization dielectric layer and said graphene layer. withdrawn
The method of Claim 1, further comprising recessing portions of said planarization dielectric layer selective to said silicon-carbon alloy fin prior to formation of said graphene layer. withdrawn
The method of Claim 1, wherein said graphene layer is formed by evaporation of silicon atoms from said set of at least one contiguous physically exposed surface portion of said silicon-carbon alloy fin during said anneal process. withdrawn
The method of Claim 1, further comprising replacing said semiconductor fin with a dielectric material portion prior to performing said anneal process. withdrawn
The method of Claim 1, wherein said semiconductor fin is present on said silicon-carbon alloy fin during said anneal process. withdrawn
The method of Claim 1, wherein said set of at least one contiguous physically exposed surface portion consists of a surface portion underlying a top surface of said silicon- carbon alloy fin. withdrawn
A semiconductor structure comprising: a silicon-carbon alloy fin located on an insulator layer; a graphene layer located on a top surface of said silicon-carbon alloy fin; a dielectric material layer contacting said silicon-carbon alloy fin, wherein a horizontal interface between said graphene layer and said silicon-carbon alloy fin is recessed relative to a top surface of said dielectric material layer; and a gate structure comprising a stack of a gate dielectric and a gate electrode and straddling said silicon-carbon alloy fin and contacting said top surface of said dielectric material layer.
The semiconductor structure of Claim 11, wherein an entirety of said top surface of said silicon-carbon alloy fin is in contact with said graphene layer.
(Cu rr ently Amended) The semiconductor structure of Claim 11, wherein said graphene layer include includes a vertical portion that contacts a lengthwise sidewall surface of said silicon-carbon alloy fin.
The semiconductor structure of Claim 11, wherein an entirety of said graphene layer is located on, and above, said top surface of said silicon-carbon alloy fin and has a same width throughout.
The semiconductor structure of Claim 11, further comprising a dielectric material portion in contact with a lengthwise sidewall surface of said silicon-carbon alloy fin and a vertical surface of said dielectric material layer.
The semiconductor structure of Claim 11, further comprising a semiconductor material portion in epitaxial alignment with said silicon-carbon alloy fin and in contact with a lengthwise sidewall surface of said silicon-carbon alloy fin and a vertical surface of said dielectric material
Layer stacks claimed or described, ordered top of device to substrate.
graphene fin field-effect transistor with sublithographic channel width
Materials described outside the worked examples.
silicon-carbon alloy
SiC
semiconductor fin material
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 1050–1450 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,236,477Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 0 A is a top-down view of the first exemplary structure after formation of a dielectric spacer and a gate structure including a gate dielectric and a …
FIG. 2A is a top-down view of the first exemplary structure after formation of inverted U- shaped silicon-carbon alloy structures by selective epitaxy according …
FIG. 3A is a top-down view of the first exemplary structure after truncation of end portions of the inverted U-shaped silicon-carbon alloy structures and …
FIG. 4A is a top-down view of the first exemplary structure after formation of silicon- carbon alloy fins by removal of top portions of the inverted U-shaped …
FIG. 5 A is a top-down view of the first exemplary structure after replacement of semiconductor fins with dielectric material fins according to an embodiment of …
FIG. 6A is a top-down view of the first exemplary structure after formation of a patterned mask layer and recessing of the planarization dielectric layer and …
FIG. 7A is a top-down view of the first exemplary structure after formation of graphene layers from physically exposed surface portions of the silicon-carbon …
FIG. 8A is a top-down view of the first exemplary structure after masking portions of the graphene layers to be employed as channel portions with a masking …
FIG. 9A is a top-down view of the first exemplary structure after depositing a conductive material to form a source contact structure and a drain contact …
FIG. 10 B is a vertical cross-sectional view of the first exemplary structure along the vertical plane B-B' of
FIG. 12A is a top-down view of a second variation of the first exemplary structure according to an embodiment of the present disclosure. [0037]
FIG. 13A is a top-down view of a third variation of the first exemplary structure according to an embodiment of the present disclosure. [0040]
FIG. 14A is a top-down view of a second exemplary structure after formation of graphene layers according to an embodiment of the present disclosure. [0043]
FIG. 15A is a top-down view of the second exemplary structure after formation of a source contact structure, a drain contact structure, a dielectric spacer, …
FIG. 16A is a top-down view of a variation of the second exemplary structure according to an embodiment of the present disclosure. [0049]
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a structure comprising: forming a semiconductor fin on an insulator layer; forming a silicon-carbon alloy structure by selective epitaxy of a silicon-carbon alloy on surfaces of said semiconductor fin; depositing a planarization dielectric layer around said silicon-carbon alloy structure and above said insulator layer; removing a horizontal portion of said silicon-carbon alloy structure, wherein a remaining vertical portion of said silicon-carbon alloy structure constitutes a silicon-carbon alloy fin; and converting a set of at least one contiguous physically exposed surface portion of said silicon-carbon alloy fin into a graphene layer by an anneal process. withdrawn
The method of Claim 1, further comprising forming a gate structure comprising a stack of a gate dielectric and a gate electrode across said silicon-carbon alloy fin and over said planarization dielectric layer and said graphene layer. withdrawn
The method of Claim 1, further comprising recessing portions of said planarization dielectric layer selective to said silicon-carbon alloy fin prior to formation of said graphene layer. withdrawn
The method of Claim 1, wherein said graphene layer is formed by evaporation of silicon atoms from said set of at least one contiguous physically exposed surface portion of said silicon-carbon alloy fin during said anneal process. withdrawn
The method of Claim 1, further comprising replacing said semiconductor fin with a dielectric material portion prior to performing said anneal process. withdrawn
The method of Claim 1, wherein said semiconductor fin is present on said silicon-carbon alloy fin during said anneal process. withdrawn
The method of Claim 1, wherein said set of at least one contiguous physically exposed surface portion consists of a surface portion underlying a top surface of said silicon- carbon alloy fin. withdrawn
A semiconductor structure comprising: a silicon-carbon alloy fin located on an insulator layer; a graphene layer located on a top surface of said silicon-carbon alloy fin; a dielectric material layer contacting said silicon-carbon alloy fin, wherein a horizontal interface between said graphene layer and said silicon-carbon alloy fin is recessed relative to a top surface of said dielectric material layer; and a gate structure comprising a stack of a gate dielectric and a gate electrode and straddling said silicon-carbon alloy fin and contacting said top surface of said dielectric material layer.
The semiconductor structure of Claim 11, wherein an entirety of said top surface of said silicon-carbon alloy fin is in contact with said graphene layer.
(Cu rr ently Amended) The semiconductor structure of Claim 11, wherein said graphene layer include includes a vertical portion that contacts a lengthwise sidewall surface of said silicon-carbon alloy fin.
The semiconductor structure of Claim 11, wherein an entirety of said graphene layer is located on, and above, said top surface of said silicon-carbon alloy fin and has a same width throughout.
The semiconductor structure of Claim 11, further comprising a dielectric material portion in contact with a lengthwise sidewall surface of said silicon-carbon alloy fin and a vertical surface of said dielectric material layer.
The semiconductor structure of Claim 11, further comprising a semiconductor material portion in epitaxial alignment with said silicon-carbon alloy fin and in contact with a lengthwise sidewall surface of said silicon-carbon alloy fin and a vertical surface of said dielectric material
Layer stacks claimed or described, ordered top of device to substrate.
graphene fin field-effect transistor with sublithographic channel width
Materials described outside the worked examples.
silicon-carbon alloy
SiC
semiconductor fin material
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 1050–1450 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
graphene
C
semiconductor material portion
single crystalline silicon
Si
single crystalline silicon-germanium alloy
SiGe
| 1150–1400 °C |
| — |
Temperature | 1200–1600 °C | — |
Thickness | 30–300 nm | — |
Thickness | 2–40 nm | — |
Pressure | 10–10 Torr | — |
GRAPHENE BARRIER LAYERS FOR INTERCONNECTS AND METHODS FOR FORMING THE SAME
graphene
C
semiconductor material portion
single crystalline silicon
Si
single crystalline silicon-germanium alloy
SiGe
| 1150–1400 °C |
| — |
Temperature | 1200–1600 °C | — |
Thickness | 30–300 nm | — |
Thickness | 2–40 nm | — |
Pressure | 10–10 Torr | — |
GRAPHENE BARRIER LAYERS FOR INTERCONNECTS AND METHODS FOR FORMING THE SAME
graphene
C
semiconductor material portion
single crystalline silicon
Si
single crystalline silicon-germanium alloy
SiGe
| 1150–1400 °C |
| — |
Temperature | 1200–1600 °C | — |
Thickness | 30–300 nm | — |
Thickness | 2–40 nm | — |
Pressure | 10–10 Torr | — |
GRAPHENE BARRIER LAYERS FOR INTERCONNECTS AND METHODS FOR FORMING THE SAME
graphene
C
semiconductor material portion
single crystalline silicon
Si
single crystalline silicon-germanium alloy
SiGe
| 1150–1400 °C |
| — |
Temperature | 1200–1600 °C | — |
Thickness | 30–300 nm | — |
Thickness | 2–40 nm | — |
Pressure | 10–10 Torr | — |
GRAPHENE BARRIER LAYERS FOR INTERCONNECTS AND METHODS FOR FORMING THE SAME