1. A driver circuit for driving a I II -Nitride H FE T device, comprising: a resonant drive circuit coupled to the I II -Nitride H FET device, said resonant drive circuit comprising an LC circuit having an inductance and a capacitance, the capacitance of said LC circuit comprising the gate-source capacitance of the I II -Nitride H FE T device; a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal, the polarity of the second signal being different f r om the first signal; wherein said resonant drive circuit is controlled based at least in part on the second signal such that said resonant drive circuit provides a first voltage to the I II-Nitride H FET device to control the I II -Nitride H FE T device to operate in a conducting state and to provide a second voltage to the I II -Nitride HFET device to control the I II -Nitride HFET device to operate in a non-conducting state; wherein said level shifter circuit comprises a first stage and a second stage, said first stag e configured to receive the first signal and to convert the first signal to a third signal, the third signal alternating between a peak voltage of the first signal and the second voltage, said second stage configured to receive the third sig n al and to convert the third signal to the second 2 signal, the second signal alternating between the first voltage and the second voltage.

canceled

canceled

The driver circuit of claim [7] 1, wherein said second stage comprises a low standby current level shifter circuit.

The driver circuit of claim [7] 1 wherein said second stage comprises a buffer circuit.

canceled

T he -itegrate-eksait-ef-elaim4, An integrated circuit for driving a G aN H FET device, comprising: a resonant drive circuit coupled to the G aN H FET device, said resonant drive circuit comprising a totem pole arrangement of a PMOS transistor and a NMOS transistor, an LC circuit bein g cou p led to a j unction between said PMOS transistor and said NMOS transistor, said LC circuit having an inductance and a capacitance, the capacitance of said LC circuit comprising the gate-source capacitance of the G aN HFET device; a first level shifter circuit co u pled to the g ate of said PMOS transistor, said first level shifter circuit configured to receive a first signal and to amplify the first signal to a second sig n al, the polarity of the second signal being different from the first signal, the second si g nal alternating between a first voltage and a second voltage, the second signal controlling said PMOS transistor to o p erate in a conducting state when the second signal is at the first voltage and the second signal controlling said PMOS transistor to operate in a non-conducting state when the second signal is at the second voltage; a second level shifter circuit coupled to the gate of said NMOS transistor configured to receive a third signal and to amp li fy the third signal to a fourth signal, the polarity of the fourth signa l bein g different from the third si g nal, the fourth si g nal alter n atin g between the 4 first voltage and the second voltage, the fourth signal controlling said NMOS transistor to operate in a conducting state when the fourth signal is at the second voltage and the fourth signal controlling said NMOS transistor to operate in a non-conducting state when the fou r th signal is at the first voltage; wherein when said PMOS transistor is in a conducting state and said NMOS transistor is in a non-conducting state, said resonant drive circuit provides the first voltage to the G aN HFET device to control the GaN HFET device to operate in a conducting state, and when said PMOS transistor is a non-conducting state and said NMOS transistor is in a conducting state, said resonant drive circuit provides a second voltage to the G aN HF ET device to control the G aN HF ET device to operate in a non-conducting state; wherein said first and second level shifter circuits each comprise a first stage and a second stage, wherein: said first stage of said first level shifter circuit is configured to receive the first signal and to convert the first signal to a fifth signal, the fifth signal alternating between a peak voltage of the first signal and the second voltage, said second stage of said first level circuit configured to receive the fifth signal and to convert the fifth signal to the second signal; and said first second stage of said second level shifter circuit being configured to receive the third signal and to convert the third signal to a sixth signal, the sixth signal alternating between a peak voltage of the third signal and the second voltage, said second stage of said second level shifter circuit configured to receive the sixth signal and to convert the sixth signal to 5 the fourth signal.

The integrated circuit of claim [11] 12, wherein said integrated circuit is implemented using Smart-Voltag e-e Xtension (SVX) technology.

(Cance l led). canceled

1. A driver circuit for driving a I II -Nitride H FE T device, comprising: a resonant drive circuit coupled to the I II -Nitride H FET device, said resonant drive circuit comprising an LC circuit having an inductance and a capacitance, the capacitance of said LC circuit comprising the gate-source capacitance of the I II -Nitride H FE T device; a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal, the polarity of the second signal being different f r om the first signal; wherein said resonant drive circuit is controlled based at least in part on the second signal such that said resonant drive circuit provides a first voltage to the I II-Nitride H FET device to control the I II -Nitride H FE T device to operate in a conducting state and to provide a second voltage to the I II -Nitride HFET device to control the I II -Nitride HFET device to operate in a non-conducting state; wherein said level shifter circuit comprises a first stage and a second stage, said first stag e configured to receive the first signal and to convert the first signal to a third signal, the third signal alternating between a peak voltage of the first signal and the second voltage, said second stage configured to receive the third sig n al and to convert the third signal to the second 2 signal, the second signal alternating between the first voltage and the second voltage.

canceled

canceled

The driver circuit of claim [7] 1, wherein said second stage comprises a low standby current level shifter circuit.

The driver circuit of claim [7] 1 wherein said second stage comprises a buffer circuit.

canceled

T he -itegrate-eksait-ef-elaim4, An integrated circuit for driving a G aN H FET device, comprising: a resonant drive circuit coupled to the G aN H FET device, said resonant drive circuit comprising a totem pole arrangement of a PMOS transistor and a NMOS transistor, an LC circuit bein g cou p led to a j unction between said PMOS transistor and said NMOS transistor, said LC circuit having an inductance and a capacitance, the capacitance of said LC circuit comprising the gate-source capacitance of the G aN HFET device; a first level shifter circuit co u pled to the g ate of said PMOS transistor, said first level shifter circuit configured to receive a first signal and to amplify the first signal to a second sig n al, the polarity of the second signal being different from the first signal, the second si g nal alternating between a first voltage and a second voltage, the second signal controlling said PMOS transistor to o p erate in a conducting state when the second signal is at the first voltage and the second signal controlling said PMOS transistor to operate in a non-conducting state when the second signal is at the second voltage; a second level shifter circuit coupled to the gate of said NMOS transistor configured to receive a third signal and to amp li fy the third signal to a fourth signal, the polarity of the fourth signa l bein g different from the third si g nal, the fourth si g nal alter n atin g between the 4 first voltage and the second voltage, the fourth signal controlling said NMOS transistor to operate in a conducting state when the fourth signal is at the second voltage and the fourth signal controlling said NMOS transistor to operate in a non-conducting state when the fou r th signal is at the first voltage; wherein when said PMOS transistor is in a conducting state and said NMOS transistor is in a non-conducting state, said resonant drive circuit provides the first voltage to the G aN HFET device to control the GaN HFET device to operate in a conducting state, and when said PMOS transistor is a non-conducting state and said NMOS transistor is in a conducting state, said resonant drive circuit provides a second voltage to the G aN HF ET device to control the G aN HF ET device to operate in a non-conducting state; wherein said first and second level shifter circuits each comprise a first stage and a second stage, wherein: said first stage of said first level shifter circuit is configured to receive the first signal and to convert the first signal to a fifth signal, the fifth signal alternating between a peak voltage of the first signal and the second voltage, said second stage of said first level circuit configured to receive the fifth signal and to convert the fifth signal to the second signal; and said first second stage of said second level shifter circuit being configured to receive the third signal and to convert the third signal to a sixth signal, the sixth signal alternating between a peak voltage of the third signal and the second voltage, said second stage of said second level shifter circuit configured to receive the sixth signal and to convert the sixth signal to 5 the fourth signal.

The integrated circuit of claim [11] 12, wherein said integrated circuit is implemented using Smart-Voltag e-e Xtension (SVX) technology.

(Cance l led). canceled

1. A driver circuit for driving a I II -Nitride H FE T device, comprising: a resonant drive circuit coupled to the I II -Nitride H FET device, said resonant drive circuit comprising an LC circuit having an inductance and a capacitance, the capacitance of said LC circuit comprising the gate-source capacitance of the I II -Nitride H FE T device; a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal, the polarity of the second signal being different f r om the first signal; wherein said resonant drive circuit is controlled based at least in part on the second signal such that said resonant drive circuit provides a first voltage to the I II-Nitride H FET device to control the I II -Nitride H FE T device to operate in a conducting state and to provide a second voltage to the I II -Nitride HFET device to control the I II -Nitride HFET device to operate in a non-conducting state; wherein said level shifter circuit comprises a first stage and a second stage, said first stag e configured to receive the first signal and to convert the first signal to a third signal, the third signal alternating between a peak voltage of the first signal and the second voltage, said second stage configured to receive the third sig n al and to convert the third signal to the second 2 signal, the second signal alternating between the first voltage and the second voltage.

canceled

canceled

The driver circuit of claim [7] 1, wherein said second stage comprises a low standby current level shifter circuit.

The driver circuit of claim [7] 1 wherein said second stage comprises a buffer circuit.

canceled

T he -itegrate-eksait-ef-elaim4, An integrated circuit for driving a G aN H FET device, comprising: a resonant drive circuit coupled to the G aN H FET device, said resonant drive circuit comprising a totem pole arrangement of a PMOS transistor and a NMOS transistor, an LC circuit bein g cou p led to a j unction between said PMOS transistor and said NMOS transistor, said LC circuit having an inductance and a capacitance, the capacitance of said LC circuit comprising the gate-source capacitance of the G aN HFET device; a first level shifter circuit co u pled to the g ate of said PMOS transistor, said first level shifter circuit configured to receive a first signal and to amplify the first signal to a second sig n al, the polarity of the second signal being different from the first signal, the second si g nal alternating between a first voltage and a second voltage, the second signal controlling said PMOS transistor to o p erate in a conducting state when the second signal is at the first voltage and the second signal controlling said PMOS transistor to operate in a non-conducting state when the second signal is at the second voltage; a second level shifter circuit coupled to the gate of said NMOS transistor configured to receive a third signal and to amp li fy the third signal to a fourth signal, the polarity of the fourth signa l bein g different from the third si g nal, the fourth si g nal alter n atin g between the 4 first voltage and the second voltage, the fourth signal controlling said NMOS transistor to operate in a conducting state when the fourth signal is at the second voltage and the fourth signal controlling said NMOS transistor to operate in a non-conducting state when the fou r th signal is at the first voltage; wherein when said PMOS transistor is in a conducting state and said NMOS transistor is in a non-conducting state, said resonant drive circuit provides the first voltage to the G aN HFET device to control the GaN HFET device to operate in a conducting state, and when said PMOS transistor is a non-conducting state and said NMOS transistor is in a conducting state, said resonant drive circuit provides a second voltage to the G aN HF ET device to control the G aN HF ET device to operate in a non-conducting state; wherein said first and second level shifter circuits each comprise a first stage and a second stage, wherein: said first stage of said first level shifter circuit is configured to receive the first signal and to convert the first signal to a fifth signal, the fifth signal alternating between a peak voltage of the first signal and the second voltage, said second stage of said first level circuit configured to receive the fifth signal and to convert the fifth signal to the second signal; and said first second stage of said second level shifter circuit being configured to receive the third signal and to convert the third signal to a sixth signal, the sixth signal alternating between a peak voltage of the third signal and the second voltage, said second stage of said second level shifter circuit configured to receive the sixth signal and to convert the sixth signal to 5 the fourth signal.

The integrated circuit of claim [11] 12, wherein said integrated circuit is implemented using Smart-Voltag e-e Xtension (SVX) technology.

(Cance l led). canceled

1. A driver circuit for driving a I II -Nitride H FE T device, comprising: a resonant drive circuit coupled to the I II -Nitride H FET device, said resonant drive circuit comprising an LC circuit having an inductance and a capacitance, the capacitance of said LC circuit comprising the gate-source capacitance of the I II -Nitride H FE T device; a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal, the polarity of the second signal being different f r om the first signal; wherein said resonant drive circuit is controlled based at least in part on the second signal such that said resonant drive circuit provides a first voltage to the I II-Nitride H FET device to control the I II -Nitride H FE T device to operate in a conducting state and to provide a second voltage to the I II -Nitride HFET device to control the I II -Nitride HFET device to operate in a non-conducting state; wherein said level shifter circuit comprises a first stage and a second stage, said first stag e configured to receive the first signal and to convert the first signal to a third signal, the third signal alternating between a peak voltage of the first signal and the second voltage, said second stage configured to receive the third sig n al and to convert the third signal to the second 2 signal, the second signal alternating between the first voltage and the second voltage.

canceled

canceled

The driver circuit of claim [7] 1, wherein said second stage comprises a low standby current level shifter circuit.

The driver circuit of claim [7] 1 wherein said second stage comprises a buffer circuit.

canceled

T he -itegrate-eksait-ef-elaim4, An integrated circuit for driving a G aN H FET device, comprising: a resonant drive circuit coupled to the G aN H FET device, said resonant drive circuit comprising a totem pole arrangement of a PMOS transistor and a NMOS transistor, an LC circuit bein g cou p led to a j unction between said PMOS transistor and said NMOS transistor, said LC circuit having an inductance and a capacitance, the capacitance of said LC circuit comprising the gate-source capacitance of the G aN HFET device; a first level shifter circuit co u pled to the g ate of said PMOS transistor, said first level shifter circuit configured to receive a first signal and to amplify the first signal to a second sig n al, the polarity of the second signal being different from the first signal, the second si g nal alternating between a first voltage and a second voltage, the second signal controlling said PMOS transistor to o p erate in a conducting state when the second signal is at the first voltage and the second signal controlling said PMOS transistor to operate in a non-conducting state when the second signal is at the second voltage; a second level shifter circuit coupled to the gate of said NMOS transistor configured to receive a third signal and to amp li fy the third signal to a fourth signal, the polarity of the fourth signa l bein g different from the third si g nal, the fourth si g nal alter n atin g between the 4 first voltage and the second voltage, the fourth signal controlling said NMOS transistor to operate in a conducting state when the fourth signal is at the second voltage and the fourth signal controlling said NMOS transistor to operate in a non-conducting state when the fou r th signal is at the first voltage; wherein when said PMOS transistor is in a conducting state and said NMOS transistor is in a non-conducting state, said resonant drive circuit provides the first voltage to the G aN HFET device to control the GaN HFET device to operate in a conducting state, and when said PMOS transistor is a non-conducting state and said NMOS transistor is in a conducting state, said resonant drive circuit provides a second voltage to the G aN HF ET device to control the G aN HF ET device to operate in a non-conducting state; wherein said first and second level shifter circuits each comprise a first stage and a second stage, wherein: said first stage of said first level shifter circuit is configured to receive the first signal and to convert the first signal to a fifth signal, the fifth signal alternating between a peak voltage of the first signal and the second voltage, said second stage of said first level circuit configured to receive the fifth signal and to convert the fifth signal to the second signal; and said first second stage of said second level shifter circuit being configured to receive the third signal and to convert the third signal to a sixth signal, the sixth signal alternating between a peak voltage of the third signal and the second voltage, said second stage of said second level shifter circuit configured to receive the sixth signal and to convert the sixth signal to 5 the fourth signal.

The integrated circuit of claim [11] 12, wherein said integrated circuit is implemented using Smart-Voltag e-e Xtension (SVX) technology.

(Cance l led). canceled