Patent
US 10,594,272GALLIUM NITRIDE POWER AMPLIFIER
Kevin Wesley Kobayashi
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,594,272Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) power amplifier (PA) comprising a plurality of ampli fi er stages integrated into a monolithic integrated circuit and coupled together between a radio frequency signal input and a radio frequency signal output, wherein at least one of the plurality of amplifier stages includes a first GaN transistor that is configured to have a first breakdown voltage that is no more than 75% of a second breakdown voltage of a second GaN transistor included in a different one of the plurality of amplifier stages; wherein the first GaN transistor has a first drain, a first gate, and a fi rst source with lateral spacing between one another and the second GaN transistor has a second drain, a second gate, and a second source with lateral spacing between one another such that the lateral spacing between at least one of the fi rst drain, the first gate, and the fi rst source is different from the lateral spacing between at least one of the second drain, the second gate, and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor is configured to operate at a first supply voltage and the second GaN transistor is configured to operate at a second supply voltage that is higher than the first supply voltage. Original
The GaN PA of claim 1 wherein the first GaN transistor has a first gate length and the second GaN transistor has a second gate length that is longer than the first gate length. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the fi rst gate and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second source disposed over the substrate such that a first lateral spacing between the fi rst gate and the fi rst source is less than a second lateral spacing between the second gate and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the fi rst gate and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second source disposed over the substrate such that a first lateral spacing between the fi rst gate and the first source is less than a second lateral spacing between the second gate and the second source, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first gate and [[a]] the first drain disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second drain disposed over the substrate such that a first lateral spacing between the first gate and the first drain is less than a second lateral spacing between the second gate and the second drain. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first gate and [[a]] the first drain disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second drain disposed over the substrate such that a first lateral spacing between the first gate and the first drain is less than a second lateral spacing between the second gate and the second drain, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first drain and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second drain and [[a]] the second source disposed over the substrate such that a first lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first drain, [[a]] the first gate, and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second drain, [[a]] the second gate, and [[a]] the second source disposed over the substrate such that a first lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the plurality of amplifier stages is arranged in a cascaded PA topology. Original
The GaN PA of claim 1 wherein the first transistor includes an epitaxially regrown contact. Original
The GaN PA of claim 1 wherein the first GaN transistor includes an epitaxially regrown channel region comprised of a first type of material that is different from a second type of material comprising a channel region of the second GaN transistor. Withdrawn
The GaN PA of claim 1 wherein the first GaN transistor has a single-field plated structure and the second GaN transistor has a double-field plated structure. Withdrawn
The GaN PA of claim 1 wherein the first GaN transistor has a first knee voltage that is lower than a second knee voltage of the second GaN transistor. Original
The GaN PA of claim 1 wherein the first GaN transistor a first gate length and the second GaN transistor has a second gate length that is equal to the first gate length within ± 1%. Currently amended
The GaN PA of claim I wherein the first GaN transistor has [[a]] the first drain, [[a]] the first gate, and [[a l] the first source disposed over a substrate and the second GaN transistor has [[a]] the second dr ain, I lal]I the second gate, and [[a]] the second source disposed over the substrate such that a f irs t lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source, a third lateral spacing between the first gate and the fi rst source is less than a fourth lateral spacing between the second gate and the second source, a fi f th lateral spacing between the first gate and the first drain is less than a sixth lateral spacing between the second gate and the second drain, and the first gate has a f irst gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 10 wherein the first gate includes a self-aligned spacer. Currently amended
The GaN PA of claim I wherein the plurality of amplifier stages is arranged in a parallel PA topology. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN power amplifier monolithic integrated circuit
Materials described outside the worked examples.
gallium nitride
GaN
Patent
Atlas literature
Patent
US 10,594,272Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) power amplifier (PA) comprising a plurality of ampli fi er stages integrated into a monolithic integrated circuit and coupled together between a radio frequency signal input and a radio frequency signal output, wherein at least one of the plurality of amplifier stages includes a first GaN transistor that is configured to have a first breakdown voltage that is no more than 75% of a second breakdown voltage of a second GaN transistor included in a different one of the plurality of amplifier stages; wherein the first GaN transistor has a first drain, a first gate, and a fi rst source with lateral spacing between one another and the second GaN transistor has a second drain, a second gate, and a second source with lateral spacing between one another such that the lateral spacing between at least one of the fi rst drain, the first gate, and the fi rst source is different from the lateral spacing between at least one of the second drain, the second gate, and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor is configured to operate at a first supply voltage and the second GaN transistor is configured to operate at a second supply voltage that is higher than the first supply voltage. Original
The GaN PA of claim 1 wherein the first GaN transistor has a first gate length and the second GaN transistor has a second gate length that is longer than the first gate length. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the fi rst gate and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second source disposed over the substrate such that a first lateral spacing between the fi rst gate and the fi rst source is less than a second lateral spacing between the second gate and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the fi rst gate and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second source disposed over the substrate such that a first lateral spacing between the fi rst gate and the first source is less than a second lateral spacing between the second gate and the second source, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first gate and [[a]] the first drain disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second drain disposed over the substrate such that a first lateral spacing between the first gate and the first drain is less than a second lateral spacing between the second gate and the second drain. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first gate and [[a]] the first drain disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second drain disposed over the substrate such that a first lateral spacing between the first gate and the first drain is less than a second lateral spacing between the second gate and the second drain, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first drain and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second drain and [[a]] the second source disposed over the substrate such that a first lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first drain, [[a]] the first gate, and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second drain, [[a]] the second gate, and [[a]] the second source disposed over the substrate such that a first lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the plurality of amplifier stages is arranged in a cascaded PA topology. Original
The GaN PA of claim 1 wherein the first transistor includes an epitaxially regrown contact. Original
The GaN PA of claim 1 wherein the first GaN transistor includes an epitaxially regrown channel region comprised of a first type of material that is different from a second type of material comprising a channel region of the second GaN transistor. Withdrawn
The GaN PA of claim 1 wherein the first GaN transistor has a single-field plated structure and the second GaN transistor has a double-field plated structure. Withdrawn
The GaN PA of claim 1 wherein the first GaN transistor has a first knee voltage that is lower than a second knee voltage of the second GaN transistor. Original
The GaN PA of claim 1 wherein the first GaN transistor a first gate length and the second GaN transistor has a second gate length that is equal to the first gate length within ± 1%. Currently amended
The GaN PA of claim I wherein the first GaN transistor has [[a]] the first drain, [[a]] the first gate, and [[a l] the first source disposed over a substrate and the second GaN transistor has [[a]] the second dr ain, I lal]I the second gate, and [[a]] the second source disposed over the substrate such that a f irs t lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source, a third lateral spacing between the first gate and the fi rst source is less than a fourth lateral spacing between the second gate and the second source, a fi f th lateral spacing between the first gate and the first drain is less than a sixth lateral spacing between the second gate and the second drain, and the first gate has a f irst gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 10 wherein the first gate includes a self-aligned spacer. Currently amended
The GaN PA of claim I wherein the plurality of amplifier stages is arranged in a parallel PA topology. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN power amplifier monolithic integrated circuit
Materials described outside the worked examples.
gallium nitride
GaN
Patent
Atlas literature
Patent
US 10,594,272Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) power amplifier (PA) comprising a plurality of ampli fi er stages integrated into a monolithic integrated circuit and coupled together between a radio frequency signal input and a radio frequency signal output, wherein at least one of the plurality of amplifier stages includes a first GaN transistor that is configured to have a first breakdown voltage that is no more than 75% of a second breakdown voltage of a second GaN transistor included in a different one of the plurality of amplifier stages; wherein the first GaN transistor has a first drain, a first gate, and a fi rst source with lateral spacing between one another and the second GaN transistor has a second drain, a second gate, and a second source with lateral spacing between one another such that the lateral spacing between at least one of the fi rst drain, the first gate, and the fi rst source is different from the lateral spacing between at least one of the second drain, the second gate, and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor is configured to operate at a first supply voltage and the second GaN transistor is configured to operate at a second supply voltage that is higher than the first supply voltage. Original
The GaN PA of claim 1 wherein the first GaN transistor has a first gate length and the second GaN transistor has a second gate length that is longer than the first gate length. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the fi rst gate and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second source disposed over the substrate such that a first lateral spacing between the fi rst gate and the fi rst source is less than a second lateral spacing between the second gate and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the fi rst gate and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second source disposed over the substrate such that a first lateral spacing between the fi rst gate and the first source is less than a second lateral spacing between the second gate and the second source, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first gate and [[a]] the first drain disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second drain disposed over the substrate such that a first lateral spacing between the first gate and the first drain is less than a second lateral spacing between the second gate and the second drain. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first gate and [[a]] the first drain disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second drain disposed over the substrate such that a first lateral spacing between the first gate and the first drain is less than a second lateral spacing between the second gate and the second drain, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first drain and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second drain and [[a]] the second source disposed over the substrate such that a first lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first drain, [[a]] the first gate, and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second drain, [[a]] the second gate, and [[a]] the second source disposed over the substrate such that a first lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the plurality of amplifier stages is arranged in a cascaded PA topology. Original
The GaN PA of claim 1 wherein the first transistor includes an epitaxially regrown contact. Original
The GaN PA of claim 1 wherein the first GaN transistor includes an epitaxially regrown channel region comprised of a first type of material that is different from a second type of material comprising a channel region of the second GaN transistor. Withdrawn
The GaN PA of claim 1 wherein the first GaN transistor has a single-field plated structure and the second GaN transistor has a double-field plated structure. Withdrawn
The GaN PA of claim 1 wherein the first GaN transistor has a first knee voltage that is lower than a second knee voltage of the second GaN transistor. Original
The GaN PA of claim 1 wherein the first GaN transistor a first gate length and the second GaN transistor has a second gate length that is equal to the first gate length within ± 1%. Currently amended
The GaN PA of claim I wherein the first GaN transistor has [[a]] the first drain, [[a]] the first gate, and [[a l] the first source disposed over a substrate and the second GaN transistor has [[a]] the second dr ain, I lal]I the second gate, and [[a]] the second source disposed over the substrate such that a f irs t lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source, a third lateral spacing between the first gate and the fi rst source is less than a fourth lateral spacing between the second gate and the second source, a fi f th lateral spacing between the first gate and the first drain is less than a sixth lateral spacing between the second gate and the second drain, and the first gate has a f irst gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 10 wherein the first gate includes a self-aligned spacer. Currently amended
The GaN PA of claim I wherein the plurality of amplifier stages is arranged in a parallel PA topology. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN power amplifier monolithic integrated circuit
Materials described outside the worked examples.
gallium nitride
GaN
Patent
Atlas literature
Patent
US 10,594,272Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) power amplifier (PA) comprising a plurality of ampli fi er stages integrated into a monolithic integrated circuit and coupled together between a radio frequency signal input and a radio frequency signal output, wherein at least one of the plurality of amplifier stages includes a first GaN transistor that is configured to have a first breakdown voltage that is no more than 75% of a second breakdown voltage of a second GaN transistor included in a different one of the plurality of amplifier stages; wherein the first GaN transistor has a first drain, a first gate, and a fi rst source with lateral spacing between one another and the second GaN transistor has a second drain, a second gate, and a second source with lateral spacing between one another such that the lateral spacing between at least one of the fi rst drain, the first gate, and the fi rst source is different from the lateral spacing between at least one of the second drain, the second gate, and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor is configured to operate at a first supply voltage and the second GaN transistor is configured to operate at a second supply voltage that is higher than the first supply voltage. Original
The GaN PA of claim 1 wherein the first GaN transistor has a first gate length and the second GaN transistor has a second gate length that is longer than the first gate length. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the fi rst gate and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second source disposed over the substrate such that a first lateral spacing between the fi rst gate and the fi rst source is less than a second lateral spacing between the second gate and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the fi rst gate and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second source disposed over the substrate such that a first lateral spacing between the fi rst gate and the first source is less than a second lateral spacing between the second gate and the second source, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first gate and [[a]] the first drain disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second drain disposed over the substrate such that a first lateral spacing between the first gate and the first drain is less than a second lateral spacing between the second gate and the second drain. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first gate and [[a]] the first drain disposed over a substrate and the second GaN transistor has [[a]] the second gate and [[a]] the second drain disposed over the substrate such that a first lateral spacing between the first gate and the first drain is less than a second lateral spacing between the second gate and the second drain, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first drain and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second drain and [[a]] the second source disposed over the substrate such that a first lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source. Currently amended
The GaN PA of claim 1 wherein the first GaN transistor has [[a]] the first drain, [[a]] the first gate, and [[a]] the first source disposed over a substrate and the second GaN transistor has [[a]] the second drain, [[a]] the second gate, and [[a]] the second source disposed over the substrate such that a first lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source, and the first gate has a first gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 1 wherein the plurality of amplifier stages is arranged in a cascaded PA topology. Original
The GaN PA of claim 1 wherein the first transistor includes an epitaxially regrown contact. Original
The GaN PA of claim 1 wherein the first GaN transistor includes an epitaxially regrown channel region comprised of a first type of material that is different from a second type of material comprising a channel region of the second GaN transistor. Withdrawn
The GaN PA of claim 1 wherein the first GaN transistor has a single-field plated structure and the second GaN transistor has a double-field plated structure. Withdrawn
The GaN PA of claim 1 wherein the first GaN transistor has a first knee voltage that is lower than a second knee voltage of the second GaN transistor. Original
The GaN PA of claim 1 wherein the first GaN transistor a first gate length and the second GaN transistor has a second gate length that is equal to the first gate length within ± 1%. Currently amended
The GaN PA of claim I wherein the first GaN transistor has [[a]] the first drain, [[a]] the first gate, and [[a l] the first source disposed over a substrate and the second GaN transistor has [[a]] the second dr ain, I lal]I the second gate, and [[a]] the second source disposed over the substrate such that a f irs t lateral spacing between the first drain and the first source is less than a second lateral spacing between the second drain and the second source, a third lateral spacing between the first gate and the fi rst source is less than a fourth lateral spacing between the second gate and the second source, a fi f th lateral spacing between the first gate and the first drain is less than a sixth lateral spacing between the second gate and the second drain, and the first gate has a f irst gate length that is shorter than a second gate length of the second gate. Currently amended
The GaN PA of claim 10 wherein the first gate includes a self-aligned spacer. Currently amended
The GaN PA of claim I wherein the plurality of amplifier stages is arranged in a parallel PA topology. Withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
GaN power amplifier monolithic integrated circuit
Materials described outside the worked examples.
gallium nitride
GaN