Patent
Atlas literature
Patent
US 12,573,843 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified block diagram of an electrostatic discharge (ESD) protection system in accordance with an embodiment of the present disclosure. 35
FIG. 2 is a schematic diagram of an ESD clamp circuit in accordance with an embodiment of the present disclosure.
FIG. 3A is a schematic diagram of an ESD clamp circuit in accordance with another embodiment of the present disclosure. 40
FIG. 4 is a schematic diagram of an ESD clamp circuit in 50 accordance with yet another embodiment of the present disclosure.
FIG. 5 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure. 55
FIG. 6 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
FIG. 7 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present 60 disclosure.
FIG. 8 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
FIG. 9 is a schematic diagram of an ESD clamp circuit in 65 accordance with still another embodiment of the present disclosure. B₂
FIG. 10 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a control circuit, coupled between a first terminal and a second terminal of the semiconductor device, and con-figured to provide a first voltage at a first node; 5 a driving circuit, electrically connected to the control circuit at the first node, and configured to provide a trigger signal at a second node in response to an electrostatic discharge (ESD) event occurring at the first terminal or the second terminal; 10 a voltage pull-up device, coupled between the first termi-nal and the first node, and configured to pull up the first voltage at the first node in response to the ESD event occurring at the first terminal; and a discharging circuit, electrically connected to the second node, and coupled between the first terminal and the second terminal, wherein the control circuit comprises: a first high-electron-mobility transistor (HEMT), hav-ing a gate connected to a third node, a drain electri-cally connected to the first node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide the first power supply voltage to generate a first bias voltage at the third node.
The semiconductor device of claim 1, wherein when a first power supply voltage and a second power supply voltage are respectively provided to the first terminal and the second terminal, the control circuit is further configured to pull down the first voltage at the first node to the second power supply voltage, wherein the first power supply volt-age is positive, and the second power supply voltage is negative or a ground voltage.
The semiconductor device of claim 1, wherein the voltage pull-up device is a first capacitor.
An electrostatic discharge (ESD) clamp circuit, com-prising: a trigger circuit, comprising: a first resistor, coupled between a first terminal of the ESD clamp circuit and a first node; and a first capacitor, coupled between the first node and a second terminal of the ESD clamp circuit; a discharging circuit, comprising: a first high-electron-mobility transistor (HEMT), hav-ing a gate electrically connected to a second node, a drain electrically connected the first terminal, and a source electrically connected to the second terminal; a driving circuit, comprising: a high-side HEMT, having a gate electrically connected to a third node, a drain electrically connected to the first terminal, and a source electrically connected to the first node; and a low-side HEMT, having a gate electrically connected to an output terminal of the trigger circuit, a drain electrically connected to the second node, and a source electrically connected to the second terminal; and a control circuit, coupled between the first terminal and the second terminal, wherein the control circuit com-prises: a second HEMT, having a gate connected to a fourth node, a drain electrically connected to the third node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide a first power supply voltage to generate a first bias voltage at the fourth node.
The ESD clamp circuit of claim 14, wherein the first HEMT and the low-side HEMT are implemented using enhancement-mode N-type HEMTs, and a total width of the first HEMT is greater than that of the low-side HEMT, wherein the high-side HEMT is implemented using a depletion-mode N-type HEMT, and a total width of the high-side HEMT is smaller than that of the low-side HEMT.
The ESD clamp circuit of claim 14, wherein during a normal direct-current (DC) operation mode of the ESD clamp circuit, the first power supply voltage and a second power supply voltage are respectively provided to the first terminal and the second terminal, and the ESD clamp circuit further comprises: a second capacitor, coupled between the first terminal and the third node, and configured to pull up the first voltage at the third node to a second voltage of an ESD event in response to the ESD event occurring at the first terminal.
The ESD clamp circuit of claim 14, further compris-ing: a stack rectifier, comprising one or more second HEMTs arranged in a cascode architecture, wherein each sec-ond HEMT is in a first diode-connected configuration; and a rectifier, comprising: a third HEMT in a second diode-connected configuration opposite to the first diode-connected configuration.
An electrostatic discharge (ESD) clamp circuit, com-prising: a resistance-capacitance (RC) trigger circuit, comprising: a high-side resistor and a low-side capacitor coupled to a first terminal and a second terminal, respectively, of the ESD clamp circuit; a discharging circuit, comprising: a first high-electron-mobility transistor (HEMT), having a gate, a drain B₂ electrically connected the first terminal, and a source electrically connected to the second terminal; a driving circuit, electrically connected between the RC trigger circuit and the gate of the first HEMT; a stack rectifier, comprising one or more second HEMTs arranged in a cascode architecture, wherein each sec-ond HEMT is in a first diode-connected configuration; and a rectifier, comprising: a third HEMT in a second diode-connected configuration opposite to the first diode-connected configuration, wherein the driving circuit is configured to provide a first bias voltage to turn off the first HEMT during a normal direct-current (DC) operation mode of the ESD clamp circuit, and provide a second bias voltage to turn on the first HEMT during an ESD mode of the ESD clamp circuit, wherein the second bias voltage is approxi-mately equal to a first voltage of an ESD event occur-ring at the first terminal or the second terminal.
The ESD clamp circuit of claim 18, wherein in response to the ESD event occurring at the second terminal, the first voltage of the ESD event is transferred to the gate of the first HEMT to turn on the first HEMT to generate a discharge current flowing from the second terminal to the first terminal through the first HEMT to discharge electric charges of the ESD event.
The ESD clamp circuit of claim 18, further compris-ing: a control circuit, coupled between the first terminal and the second terminal of the semiconductor device, and configured to provide a first voltage to the driving circuit at a first node, wherein the control circuit comprises: a fourth HEMT, having a gate connected to a second node, a drain electrically connected to the first node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide a power supply voltage to generate a first bias voltage at the second node. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device with ESD clamp (claims 1–13)
ESD clamp circuit (claims 14–17)
Materials described outside the worked examples.
AlGaN/GaN heterojunction (2DEG channel)
silicon-chromium
SiCr
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–6000 µm | — |
Thickness | 100–1000 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 9
Patent
Atlas literature
Patent
US 12,573,843 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified block diagram of an electrostatic discharge (ESD) protection system in accordance with an embodiment of the present disclosure. 35
FIG. 2 is a schematic diagram of an ESD clamp circuit in accordance with an embodiment of the present disclosure.
FIG. 3A is a schematic diagram of an ESD clamp circuit in accordance with another embodiment of the present disclosure. 40
FIG. 4 is a schematic diagram of an ESD clamp circuit in 50 accordance with yet another embodiment of the present disclosure.
FIG. 5 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure. 55
FIG. 6 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
FIG. 7 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present 60 disclosure.
FIG. 8 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
FIG. 9 is a schematic diagram of an ESD clamp circuit in 65 accordance with still another embodiment of the present disclosure. B₂
FIG. 10 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a control circuit, coupled between a first terminal and a second terminal of the semiconductor device, and con-figured to provide a first voltage at a first node; 5 a driving circuit, electrically connected to the control circuit at the first node, and configured to provide a trigger signal at a second node in response to an electrostatic discharge (ESD) event occurring at the first terminal or the second terminal; 10 a voltage pull-up device, coupled between the first termi-nal and the first node, and configured to pull up the first voltage at the first node in response to the ESD event occurring at the first terminal; and a discharging circuit, electrically connected to the second node, and coupled between the first terminal and the second terminal, wherein the control circuit comprises: a first high-electron-mobility transistor (HEMT), hav-ing a gate connected to a third node, a drain electri-cally connected to the first node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide the first power supply voltage to generate a first bias voltage at the third node.
The semiconductor device of claim 1, wherein when a first power supply voltage and a second power supply voltage are respectively provided to the first terminal and the second terminal, the control circuit is further configured to pull down the first voltage at the first node to the second power supply voltage, wherein the first power supply volt-age is positive, and the second power supply voltage is negative or a ground voltage.
The semiconductor device of claim 1, wherein the voltage pull-up device is a first capacitor.
An electrostatic discharge (ESD) clamp circuit, com-prising: a trigger circuit, comprising: a first resistor, coupled between a first terminal of the ESD clamp circuit and a first node; and a first capacitor, coupled between the first node and a second terminal of the ESD clamp circuit; a discharging circuit, comprising: a first high-electron-mobility transistor (HEMT), hav-ing a gate electrically connected to a second node, a drain electrically connected the first terminal, and a source electrically connected to the second terminal; a driving circuit, comprising: a high-side HEMT, having a gate electrically connected to a third node, a drain electrically connected to the first terminal, and a source electrically connected to the first node; and a low-side HEMT, having a gate electrically connected to an output terminal of the trigger circuit, a drain electrically connected to the second node, and a source electrically connected to the second terminal; and a control circuit, coupled between the first terminal and the second terminal, wherein the control circuit com-prises: a second HEMT, having a gate connected to a fourth node, a drain electrically connected to the third node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide a first power supply voltage to generate a first bias voltage at the fourth node.
The ESD clamp circuit of claim 14, wherein the first HEMT and the low-side HEMT are implemented using enhancement-mode N-type HEMTs, and a total width of the first HEMT is greater than that of the low-side HEMT, wherein the high-side HEMT is implemented using a depletion-mode N-type HEMT, and a total width of the high-side HEMT is smaller than that of the low-side HEMT.
The ESD clamp circuit of claim 14, wherein during a normal direct-current (DC) operation mode of the ESD clamp circuit, the first power supply voltage and a second power supply voltage are respectively provided to the first terminal and the second terminal, and the ESD clamp circuit further comprises: a second capacitor, coupled between the first terminal and the third node, and configured to pull up the first voltage at the third node to a second voltage of an ESD event in response to the ESD event occurring at the first terminal.
The ESD clamp circuit of claim 14, further compris-ing: a stack rectifier, comprising one or more second HEMTs arranged in a cascode architecture, wherein each sec-ond HEMT is in a first diode-connected configuration; and a rectifier, comprising: a third HEMT in a second diode-connected configuration opposite to the first diode-connected configuration.
An electrostatic discharge (ESD) clamp circuit, com-prising: a resistance-capacitance (RC) trigger circuit, comprising: a high-side resistor and a low-side capacitor coupled to a first terminal and a second terminal, respectively, of the ESD clamp circuit; a discharging circuit, comprising: a first high-electron-mobility transistor (HEMT), having a gate, a drain B₂ electrically connected the first terminal, and a source electrically connected to the second terminal; a driving circuit, electrically connected between the RC trigger circuit and the gate of the first HEMT; a stack rectifier, comprising one or more second HEMTs arranged in a cascode architecture, wherein each sec-ond HEMT is in a first diode-connected configuration; and a rectifier, comprising: a third HEMT in a second diode-connected configuration opposite to the first diode-connected configuration, wherein the driving circuit is configured to provide a first bias voltage to turn off the first HEMT during a normal direct-current (DC) operation mode of the ESD clamp circuit, and provide a second bias voltage to turn on the first HEMT during an ESD mode of the ESD clamp circuit, wherein the second bias voltage is approxi-mately equal to a first voltage of an ESD event occur-ring at the first terminal or the second terminal.
The ESD clamp circuit of claim 18, wherein in response to the ESD event occurring at the second terminal, the first voltage of the ESD event is transferred to the gate of the first HEMT to turn on the first HEMT to generate a discharge current flowing from the second terminal to the first terminal through the first HEMT to discharge electric charges of the ESD event.
The ESD clamp circuit of claim 18, further compris-ing: a control circuit, coupled between the first terminal and the second terminal of the semiconductor device, and configured to provide a first voltage to the driving circuit at a first node, wherein the control circuit comprises: a fourth HEMT, having a gate connected to a second node, a drain electrically connected to the first node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide a power supply voltage to generate a first bias voltage at the second node. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device with ESD clamp (claims 1–13)
ESD clamp circuit (claims 14–17)
Materials described outside the worked examples.
AlGaN/GaN heterojunction (2DEG channel)
silicon-chromium
SiCr
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–6000 µm | — |
Thickness | 100–1000 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 9
Patent
Atlas literature
Patent
US 12,573,843 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified block diagram of an electrostatic discharge (ESD) protection system in accordance with an embodiment of the present disclosure. 35
FIG. 2 is a schematic diagram of an ESD clamp circuit in accordance with an embodiment of the present disclosure.
FIG. 3A is a schematic diagram of an ESD clamp circuit in accordance with another embodiment of the present disclosure. 40
FIG. 4 is a schematic diagram of an ESD clamp circuit in 50 accordance with yet another embodiment of the present disclosure.
FIG. 5 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure. 55
FIG. 6 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
FIG. 7 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present 60 disclosure.
FIG. 8 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
FIG. 9 is a schematic diagram of an ESD clamp circuit in 65 accordance with still another embodiment of the present disclosure. B₂
FIG. 10 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a control circuit, coupled between a first terminal and a second terminal of the semiconductor device, and con-figured to provide a first voltage at a first node; 5 a driving circuit, electrically connected to the control circuit at the first node, and configured to provide a trigger signal at a second node in response to an electrostatic discharge (ESD) event occurring at the first terminal or the second terminal; 10 a voltage pull-up device, coupled between the first termi-nal and the first node, and configured to pull up the first voltage at the first node in response to the ESD event occurring at the first terminal; and a discharging circuit, electrically connected to the second node, and coupled between the first terminal and the second terminal, wherein the control circuit comprises: a first high-electron-mobility transistor (HEMT), hav-ing a gate connected to a third node, a drain electri-cally connected to the first node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide the first power supply voltage to generate a first bias voltage at the third node.
The semiconductor device of claim 1, wherein when a first power supply voltage and a second power supply voltage are respectively provided to the first terminal and the second terminal, the control circuit is further configured to pull down the first voltage at the first node to the second power supply voltage, wherein the first power supply volt-age is positive, and the second power supply voltage is negative or a ground voltage.
The semiconductor device of claim 1, wherein the voltage pull-up device is a first capacitor.
An electrostatic discharge (ESD) clamp circuit, com-prising: a trigger circuit, comprising: a first resistor, coupled between a first terminal of the ESD clamp circuit and a first node; and a first capacitor, coupled between the first node and a second terminal of the ESD clamp circuit; a discharging circuit, comprising: a first high-electron-mobility transistor (HEMT), hav-ing a gate electrically connected to a second node, a drain electrically connected the first terminal, and a source electrically connected to the second terminal; a driving circuit, comprising: a high-side HEMT, having a gate electrically connected to a third node, a drain electrically connected to the first terminal, and a source electrically connected to the first node; and a low-side HEMT, having a gate electrically connected to an output terminal of the trigger circuit, a drain electrically connected to the second node, and a source electrically connected to the second terminal; and a control circuit, coupled between the first terminal and the second terminal, wherein the control circuit com-prises: a second HEMT, having a gate connected to a fourth node, a drain electrically connected to the third node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide a first power supply voltage to generate a first bias voltage at the fourth node.
The ESD clamp circuit of claim 14, wherein the first HEMT and the low-side HEMT are implemented using enhancement-mode N-type HEMTs, and a total width of the first HEMT is greater than that of the low-side HEMT, wherein the high-side HEMT is implemented using a depletion-mode N-type HEMT, and a total width of the high-side HEMT is smaller than that of the low-side HEMT.
The ESD clamp circuit of claim 14, wherein during a normal direct-current (DC) operation mode of the ESD clamp circuit, the first power supply voltage and a second power supply voltage are respectively provided to the first terminal and the second terminal, and the ESD clamp circuit further comprises: a second capacitor, coupled between the first terminal and the third node, and configured to pull up the first voltage at the third node to a second voltage of an ESD event in response to the ESD event occurring at the first terminal.
The ESD clamp circuit of claim 14, further compris-ing: a stack rectifier, comprising one or more second HEMTs arranged in a cascode architecture, wherein each sec-ond HEMT is in a first diode-connected configuration; and a rectifier, comprising: a third HEMT in a second diode-connected configuration opposite to the first diode-connected configuration.
An electrostatic discharge (ESD) clamp circuit, com-prising: a resistance-capacitance (RC) trigger circuit, comprising: a high-side resistor and a low-side capacitor coupled to a first terminal and a second terminal, respectively, of the ESD clamp circuit; a discharging circuit, comprising: a first high-electron-mobility transistor (HEMT), having a gate, a drain B₂ electrically connected the first terminal, and a source electrically connected to the second terminal; a driving circuit, electrically connected between the RC trigger circuit and the gate of the first HEMT; a stack rectifier, comprising one or more second HEMTs arranged in a cascode architecture, wherein each sec-ond HEMT is in a first diode-connected configuration; and a rectifier, comprising: a third HEMT in a second diode-connected configuration opposite to the first diode-connected configuration, wherein the driving circuit is configured to provide a first bias voltage to turn off the first HEMT during a normal direct-current (DC) operation mode of the ESD clamp circuit, and provide a second bias voltage to turn on the first HEMT during an ESD mode of the ESD clamp circuit, wherein the second bias voltage is approxi-mately equal to a first voltage of an ESD event occur-ring at the first terminal or the second terminal.
The ESD clamp circuit of claim 18, wherein in response to the ESD event occurring at the second terminal, the first voltage of the ESD event is transferred to the gate of the first HEMT to turn on the first HEMT to generate a discharge current flowing from the second terminal to the first terminal through the first HEMT to discharge electric charges of the ESD event.
The ESD clamp circuit of claim 18, further compris-ing: a control circuit, coupled between the first terminal and the second terminal of the semiconductor device, and configured to provide a first voltage to the driving circuit at a first node, wherein the control circuit comprises: a fourth HEMT, having a gate connected to a second node, a drain electrically connected to the first node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide a power supply voltage to generate a first bias voltage at the second node. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device with ESD clamp (claims 1–13)
ESD clamp circuit (claims 14–17)
Materials described outside the worked examples.
AlGaN/GaN heterojunction (2DEG channel)
silicon-chromium
SiCr
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–6000 µm | — |
Thickness | 100–1000 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 9
Patent
Atlas literature
Patent
US 12,573,843 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified block diagram of an electrostatic discharge (ESD) protection system in accordance with an embodiment of the present disclosure. 35
FIG. 2 is a schematic diagram of an ESD clamp circuit in accordance with an embodiment of the present disclosure.
FIG. 3A is a schematic diagram of an ESD clamp circuit in accordance with another embodiment of the present disclosure. 40
FIG. 4 is a schematic diagram of an ESD clamp circuit in 50 accordance with yet another embodiment of the present disclosure.
FIG. 5 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure. 55
FIG. 6 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
FIG. 7 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present 60 disclosure.
FIG. 8 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
FIG. 9 is a schematic diagram of an ESD clamp circuit in 65 accordance with still another embodiment of the present disclosure. B₂
FIG. 10 is a schematic diagram of an ESD clamp circuit in accordance with still another embodiment of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a control circuit, coupled between a first terminal and a second terminal of the semiconductor device, and con-figured to provide a first voltage at a first node; 5 a driving circuit, electrically connected to the control circuit at the first node, and configured to provide a trigger signal at a second node in response to an electrostatic discharge (ESD) event occurring at the first terminal or the second terminal; 10 a voltage pull-up device, coupled between the first termi-nal and the first node, and configured to pull up the first voltage at the first node in response to the ESD event occurring at the first terminal; and a discharging circuit, electrically connected to the second node, and coupled between the first terminal and the second terminal, wherein the control circuit comprises: a first high-electron-mobility transistor (HEMT), hav-ing a gate connected to a third node, a drain electri-cally connected to the first node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide the first power supply voltage to generate a first bias voltage at the third node.
The semiconductor device of claim 1, wherein when a first power supply voltage and a second power supply voltage are respectively provided to the first terminal and the second terminal, the control circuit is further configured to pull down the first voltage at the first node to the second power supply voltage, wherein the first power supply volt-age is positive, and the second power supply voltage is negative or a ground voltage.
The semiconductor device of claim 1, wherein the voltage pull-up device is a first capacitor.
An electrostatic discharge (ESD) clamp circuit, com-prising: a trigger circuit, comprising: a first resistor, coupled between a first terminal of the ESD clamp circuit and a first node; and a first capacitor, coupled between the first node and a second terminal of the ESD clamp circuit; a discharging circuit, comprising: a first high-electron-mobility transistor (HEMT), hav-ing a gate electrically connected to a second node, a drain electrically connected the first terminal, and a source electrically connected to the second terminal; a driving circuit, comprising: a high-side HEMT, having a gate electrically connected to a third node, a drain electrically connected to the first terminal, and a source electrically connected to the first node; and a low-side HEMT, having a gate electrically connected to an output terminal of the trigger circuit, a drain electrically connected to the second node, and a source electrically connected to the second terminal; and a control circuit, coupled between the first terminal and the second terminal, wherein the control circuit com-prises: a second HEMT, having a gate connected to a fourth node, a drain electrically connected to the third node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide a first power supply voltage to generate a first bias voltage at the fourth node.
The ESD clamp circuit of claim 14, wherein the first HEMT and the low-side HEMT are implemented using enhancement-mode N-type HEMTs, and a total width of the first HEMT is greater than that of the low-side HEMT, wherein the high-side HEMT is implemented using a depletion-mode N-type HEMT, and a total width of the high-side HEMT is smaller than that of the low-side HEMT.
The ESD clamp circuit of claim 14, wherein during a normal direct-current (DC) operation mode of the ESD clamp circuit, the first power supply voltage and a second power supply voltage are respectively provided to the first terminal and the second terminal, and the ESD clamp circuit further comprises: a second capacitor, coupled between the first terminal and the third node, and configured to pull up the first voltage at the third node to a second voltage of an ESD event in response to the ESD event occurring at the first terminal.
The ESD clamp circuit of claim 14, further compris-ing: a stack rectifier, comprising one or more second HEMTs arranged in a cascode architecture, wherein each sec-ond HEMT is in a first diode-connected configuration; and a rectifier, comprising: a third HEMT in a second diode-connected configuration opposite to the first diode-connected configuration.
An electrostatic discharge (ESD) clamp circuit, com-prising: a resistance-capacitance (RC) trigger circuit, comprising: a high-side resistor and a low-side capacitor coupled to a first terminal and a second terminal, respectively, of the ESD clamp circuit; a discharging circuit, comprising: a first high-electron-mobility transistor (HEMT), having a gate, a drain B₂ electrically connected the first terminal, and a source electrically connected to the second terminal; a driving circuit, electrically connected between the RC trigger circuit and the gate of the first HEMT; a stack rectifier, comprising one or more second HEMTs arranged in a cascode architecture, wherein each sec-ond HEMT is in a first diode-connected configuration; and a rectifier, comprising: a third HEMT in a second diode-connected configuration opposite to the first diode-connected configuration, wherein the driving circuit is configured to provide a first bias voltage to turn off the first HEMT during a normal direct-current (DC) operation mode of the ESD clamp circuit, and provide a second bias voltage to turn on the first HEMT during an ESD mode of the ESD clamp circuit, wherein the second bias voltage is approxi-mately equal to a first voltage of an ESD event occur-ring at the first terminal or the second terminal.
The ESD clamp circuit of claim 18, wherein in response to the ESD event occurring at the second terminal, the first voltage of the ESD event is transferred to the gate of the first HEMT to turn on the first HEMT to generate a discharge current flowing from the second terminal to the first terminal through the first HEMT to discharge electric charges of the ESD event.
The ESD clamp circuit of claim 18, further compris-ing: a control circuit, coupled between the first terminal and the second terminal of the semiconductor device, and configured to provide a first voltage to the driving circuit at a first node, wherein the control circuit comprises: a fourth HEMT, having a gate connected to a second node, a drain electrically connected to the first node, and a source electrically connected to the second terminal; and a voltage divider, configured to divide a power supply voltage to generate a first bias voltage at the second node. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device with ESD clamp (claims 1–13)
ESD clamp circuit (claims 14–17)
Materials described outside the worked examples.
AlGaN/GaN heterojunction (2DEG channel)
silicon-chromium
SiCr
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–6000 µm | — |
Thickness | 100–1000 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 9
ESD clamp circuit with RC trigger, stack rectifier, and rectifier (claims 18–20)
ESD clamp circuit 200 (prior art/FIG. 2 embodiment described in description)
ESD clamp circuit 300 (FIG. 3A embodiment described in description)
titanium nitride
TiN
| — |
Thickness | 10–100 µm | — |
Thickness | 5–20 µm | — |
Thickness | 1–10 µm | — |
ESD clamp circuit with RC trigger, stack rectifier, and rectifier (claims 18–20)
ESD clamp circuit 200 (prior art/FIG. 2 embodiment described in description)
ESD clamp circuit 300 (FIG. 3A embodiment described in description)
titanium nitride
TiN
| — |
Thickness | 10–100 µm | — |
Thickness | 5–20 µm | — |
Thickness | 1–10 µm | — |
ESD clamp circuit with RC trigger, stack rectifier, and rectifier (claims 18–20)
ESD clamp circuit 200 (prior art/FIG. 2 embodiment described in description)
ESD clamp circuit 300 (FIG. 3A embodiment described in description)
titanium nitride
TiN
| — |
Thickness | 10–100 µm | — |
Thickness | 5–20 µm | — |
Thickness | 1–10 µm | — |
ESD clamp circuit with RC trigger, stack rectifier, and rectifier (claims 18–20)
ESD clamp circuit 200 (prior art/FIG. 2 embodiment described in description)
ESD clamp circuit 300 (FIG. 3A embodiment described in description)
titanium nitride
TiN
| — |
Thickness | 10–100 µm | — |
Thickness | 5–20 µm | — |
Thickness | 1–10 µm | — |
