A FinFET device, comprising: a fin formed in a semiconductor substrate, said semiconductor substrate comprising a first semiconductor material; a gate structure positioned above a portion of said fin; source and drain regions positioned on opposite sides of said gate structure; a silicon-carbide (SiC) semiconductor material positioned above said fin in said source region and said drain region, wherein said silicon-carbide (SiC) semiconductor material is different from said first semiconductor material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) se m iconductor m aterial in each of said source region and said drain region; and first and second contact structures that are conductively coupled to said graphene contacts in said source region and said drain region, respectively.

A FinFET device, comprising: a fin f o rmed in a semic o nduct o r substrate, said semic o nduct o r substrate comprising a fi rst semic o nduct o r material; a gate structure p o siti o ned above a portion o f said fin; so urce and drain regions p o siti o ned on o pposite sides of said gate structure; a sec o nd se mico nduct o r material p o siti o ned above said fi n in said s o urce regi o n and said drain regi o n, wherein said sec o nd semic o nduct o r material is different fro m said first semic o nduct o r material; a silicon-carbide (SiC) semiconductor material positioned above said fin in said so urce reg io n and sa i d dra in reg io n, wherein sa i d s ilico n-carbide (S iC) semic o nduct o r material is different fro m said first semic o nduct o r material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) semiconductor material in each of said source region and said drain region; and first and second contact structures that are conductively coupled to said graphene contacts in said s o urce regi o n and said drain regi o n, respectively.

An integrated circuit product, comprising a first fin of a PM O S FinFET device formed in a semiconductor substrate, said semiconductor substrate comprising a f ir st semiconductor material; a first gate structure of said PMOS FinFET device p o siti o ned above a p o rti o n of said fi rst fin; first source and drain regions of said PMOS FinFET device p o siti o ned o n opposite sides of said first gate structure; a second fin of an N M OS FinFET device formed in said semiconductor substrate; a second gate structure o f said NMOS FinFET device p o siti o ned above a p o rti o n of said second fin; second source and drain regions of said NMOS FinFET device positioned on opposite sides of said second gate structure; a second semiconductor material positioned on said first fin in said first source and drain regions of said PMOS Fin F ET device, wherein said second semic o nduct o r material is different fro m said first semic o nduct o r material; a third semic o nduct o r material p o siti o ned o n said second fi n in said second source and drain regions of said NMOS FinFET device, wherein said third semiconductor material is different fro m said first and sec o nd semiconductor materials; a silicon-carbide (SiC) semiconductor material positioned o n and in direct physical contact with said sec o nd semiconductor material in said first source and drain regions of said P M OS FinFET device and on and in direct physical contact wi th sa i d th ir d sem ico nduct or m ater i al in sa i d sec o nd source and drain reg ions of said NMOS FinFET device, said silicon-carbide (SiC) semiconductor material being different from said first semiconductor material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) semiconductor material in each of said first source and drain regions of said PM O S FinFET device and in said second source and drain regions of said NMOS FinFET device; and a plurality of contact structures, wherein each of said plurality of contact structures is conductively coupled to a respective one of said graphene contacts.

20. The integrated circuit pr o duct of cla im 19, wherein sa i d fourth se mico nduct or material comprises one of silicon germanium (S SVG 15950291.04-11-2018.JFV₈₇G₈₆RXEAPX1.CLM.6.9.1339.945.1504.991.svg 0.153 0.55 Chemistry

A FinFET device, comprising: a fin formed in a semiconductor substrate, said semiconductor substrate comprising a first semiconductor material; a gate structure positioned above a portion of said fin; source and drain regions positioned on opposite sides of said gate structure; a silicon-carbide (SiC) semiconductor material positioned above said fin in said source region and said drain region, wherein said silicon-carbide (SiC) semiconductor material is different from said first semiconductor material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) se m iconductor m aterial in each of said source region and said drain region; and first and second contact structures that are conductively coupled to said graphene contacts in said source region and said drain region, respectively.

A FinFET device, comprising: a fin f o rmed in a semic o nduct o r substrate, said semic o nduct o r substrate comprising a fi rst semic o nduct o r material; a gate structure p o siti o ned above a portion o f said fin; so urce and drain regions p o siti o ned on o pposite sides of said gate structure; a sec o nd se mico nduct o r material p o siti o ned above said fi n in said s o urce regi o n and said drain regi o n, wherein said sec o nd semic o nduct o r material is different fro m said first semic o nduct o r material; a silicon-carbide (SiC) semiconductor material positioned above said fin in said so urce reg io n and sa i d dra in reg io n, wherein sa i d s ilico n-carbide (S iC) semic o nduct o r material is different fro m said first semic o nduct o r material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) semiconductor material in each of said source region and said drain region; and first and second contact structures that are conductively coupled to said graphene contacts in said s o urce regi o n and said drain regi o n, respectively.

An integrated circuit product, comprising a first fin of a PM O S FinFET device formed in a semiconductor substrate, said semiconductor substrate comprising a f ir st semiconductor material; a first gate structure of said PMOS FinFET device p o siti o ned above a p o rti o n of said fi rst fin; first source and drain regions of said PMOS FinFET device p o siti o ned o n opposite sides of said first gate structure; a second fin of an N M OS FinFET device formed in said semiconductor substrate; a second gate structure o f said NMOS FinFET device p o siti o ned above a p o rti o n of said second fin; second source and drain regions of said NMOS FinFET device positioned on opposite sides of said second gate structure; a second semiconductor material positioned on said first fin in said first source and drain regions of said PMOS Fin F ET device, wherein said second semic o nduct o r material is different fro m said first semic o nduct o r material; a third semic o nduct o r material p o siti o ned o n said second fi n in said second source and drain regions of said NMOS FinFET device, wherein said third semiconductor material is different fro m said first and sec o nd semiconductor materials; a silicon-carbide (SiC) semiconductor material positioned o n and in direct physical contact with said sec o nd semiconductor material in said first source and drain regions of said P M OS FinFET device and on and in direct physical contact wi th sa i d th ir d sem ico nduct or m ater i al in sa i d sec o nd source and drain reg ions of said NMOS FinFET device, said silicon-carbide (SiC) semiconductor material being different from said first semiconductor material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) semiconductor material in each of said first source and drain regions of said PM O S FinFET device and in said second source and drain regions of said NMOS FinFET device; and a plurality of contact structures, wherein each of said plurality of contact structures is conductively coupled to a respective one of said graphene contacts.

20. The integrated circuit pr o duct of cla im 19, wherein sa i d fourth se mico nduct or material comprises one of silicon germanium (S SVG 15950291.04-11-2018.JFV₈₇G₈₆RXEAPX1.CLM.6.9.1339.945.1504.991.svg 0.153 0.55 Chemistry

A FinFET device, comprising: a fin formed in a semiconductor substrate, said semiconductor substrate comprising a first semiconductor material; a gate structure positioned above a portion of said fin; source and drain regions positioned on opposite sides of said gate structure; a silicon-carbide (SiC) semiconductor material positioned above said fin in said source region and said drain region, wherein said silicon-carbide (SiC) semiconductor material is different from said first semiconductor material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) se m iconductor m aterial in each of said source region and said drain region; and first and second contact structures that are conductively coupled to said graphene contacts in said source region and said drain region, respectively.

A FinFET device, comprising: a fin f o rmed in a semic o nduct o r substrate, said semic o nduct o r substrate comprising a fi rst semic o nduct o r material; a gate structure p o siti o ned above a portion o f said fin; so urce and drain regions p o siti o ned on o pposite sides of said gate structure; a sec o nd se mico nduct o r material p o siti o ned above said fi n in said s o urce regi o n and said drain regi o n, wherein said sec o nd semic o nduct o r material is different fro m said first semic o nduct o r material; a silicon-carbide (SiC) semiconductor material positioned above said fin in said so urce reg io n and sa i d dra in reg io n, wherein sa i d s ilico n-carbide (S iC) semic o nduct o r material is different fro m said first semic o nduct o r material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) semiconductor material in each of said source region and said drain region; and first and second contact structures that are conductively coupled to said graphene contacts in said s o urce regi o n and said drain regi o n, respectively.

An integrated circuit product, comprising a first fin of a PM O S FinFET device formed in a semiconductor substrate, said semiconductor substrate comprising a f ir st semiconductor material; a first gate structure of said PMOS FinFET device p o siti o ned above a p o rti o n of said fi rst fin; first source and drain regions of said PMOS FinFET device p o siti o ned o n opposite sides of said first gate structure; a second fin of an N M OS FinFET device formed in said semiconductor substrate; a second gate structure o f said NMOS FinFET device p o siti o ned above a p o rti o n of said second fin; second source and drain regions of said NMOS FinFET device positioned on opposite sides of said second gate structure; a second semiconductor material positioned on said first fin in said first source and drain regions of said PMOS Fin F ET device, wherein said second semic o nduct o r material is different fro m said first semic o nduct o r material; a third semic o nduct o r material p o siti o ned o n said second fi n in said second source and drain regions of said NMOS FinFET device, wherein said third semiconductor material is different fro m said first and sec o nd semiconductor materials; a silicon-carbide (SiC) semiconductor material positioned o n and in direct physical contact with said sec o nd semiconductor material in said first source and drain regions of said P M OS FinFET device and on and in direct physical contact wi th sa i d th ir d sem ico nduct or m ater i al in sa i d sec o nd source and drain reg ions of said NMOS FinFET device, said silicon-carbide (SiC) semiconductor material being different from said first semiconductor material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) semiconductor material in each of said first source and drain regions of said PM O S FinFET device and in said second source and drain regions of said NMOS FinFET device; and a plurality of contact structures, wherein each of said plurality of contact structures is conductively coupled to a respective one of said graphene contacts.

20. The integrated circuit pr o duct of cla im 19, wherein sa i d fourth se mico nduct or material comprises one of silicon germanium (S SVG 15950291.04-11-2018.JFV₈₇G₈₆RXEAPX1.CLM.6.9.1339.945.1504.991.svg 0.153 0.55 Chemistry

A FinFET device, comprising: a fin formed in a semiconductor substrate, said semiconductor substrate comprising a first semiconductor material; a gate structure positioned above a portion of said fin; source and drain regions positioned on opposite sides of said gate structure; a silicon-carbide (SiC) semiconductor material positioned above said fin in said source region and said drain region, wherein said silicon-carbide (SiC) semiconductor material is different from said first semiconductor material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) se m iconductor m aterial in each of said source region and said drain region; and first and second contact structures that are conductively coupled to said graphene contacts in said source region and said drain region, respectively.

A FinFET device, comprising: a fin f o rmed in a semic o nduct o r substrate, said semic o nduct o r substrate comprising a fi rst semic o nduct o r material; a gate structure p o siti o ned above a portion o f said fin; so urce and drain regions p o siti o ned on o pposite sides of said gate structure; a sec o nd se mico nduct o r material p o siti o ned above said fi n in said s o urce regi o n and said drain regi o n, wherein said sec o nd semic o nduct o r material is different fro m said first semic o nduct o r material; a silicon-carbide (SiC) semiconductor material positioned above said fin in said so urce reg io n and sa i d dra in reg io n, wherein sa i d s ilico n-carbide (S iC) semic o nduct o r material is different fro m said first semic o nduct o r material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) semiconductor material in each of said source region and said drain region; and first and second contact structures that are conductively coupled to said graphene contacts in said s o urce regi o n and said drain regi o n, respectively.

An integrated circuit product, comprising a first fin of a PM O S FinFET device formed in a semiconductor substrate, said semiconductor substrate comprising a f ir st semiconductor material; a first gate structure of said PMOS FinFET device p o siti o ned above a p o rti o n of said fi rst fin; first source and drain regions of said PMOS FinFET device p o siti o ned o n opposite sides of said first gate structure; a second fin of an N M OS FinFET device formed in said semiconductor substrate; a second gate structure o f said NMOS FinFET device p o siti o ned above a p o rti o n of said second fin; second source and drain regions of said NMOS FinFET device positioned on opposite sides of said second gate structure; a second semiconductor material positioned on said first fin in said first source and drain regions of said PMOS Fin F ET device, wherein said second semic o nduct o r material is different fro m said first semic o nduct o r material; a third semic o nduct o r material p o siti o ned o n said second fi n in said second source and drain regions of said NMOS FinFET device, wherein said third semiconductor material is different fro m said first and sec o nd semiconductor materials; a silicon-carbide (SiC) semiconductor material positioned o n and in direct physical contact with said sec o nd semiconductor material in said first source and drain regions of said P M OS FinFET device and on and in direct physical contact wi th sa i d th ir d sem ico nduct or m ater i al in sa i d sec o nd source and drain reg ions of said NMOS FinFET device, said silicon-carbide (SiC) semiconductor material being different from said first semiconductor material; a graphene contact positioned on and in direct physical contact with said silicon- carbide (SiC) semiconductor material in each of said first source and drain regions of said PM O S FinFET device and in said second source and drain regions of said NMOS FinFET device; and a plurality of contact structures, wherein each of said plurality of contact structures is conductively coupled to a respective one of said graphene contacts.

20. The integrated circuit pr o duct of cla im 19, wherein sa i d fourth se mico nduct or material comprises one of silicon germanium (S SVG 15950291.04-11-2018.JFV₈₇G₈₆RXEAPX1.CLM.6.9.1339.945.1504.991.svg 0.153 0.55 Chemistry