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A method for manufacturing a graphene device, the method comprising: a) providing a substrate, the substrate comprising an insulating layer and a semiconductor layer on the insulating layer; b) forming a back gate region on the insulating layer and in the semiconductor layer of the substrate, the back gate region comprising a gate electrode and a gate dielectric layer on the gate electrode, sidewalls of the gate electrode being surrounded by an isolating layer, and forming semiconductor doped regions in the semiconductor layer on opposite sides of the gate electrode; c) forming a graphene layer partially covering both the back gate region and the semiconductor doped regions; d) forming an interlayer dielectric layer; and e) forming a contact in the interlayer dielectric layer and on a portion of the gate electrode not covered by the graphene layer, and forming contacts in the interlayer dielectric layer and on portions of the semiconductor doped regions not covered by the graphene layer, wherein the substrate is an SOI substrate, and the SOI substrate comprises a top silicon, a buried oxide layer, and a back substrate; and the step b) comprises: etching the top silicon to form a gate trench; forming the semiconductor doped regions in the top silicon on opposite sides of the gate trench; formin g the isolating layer on sidewalls of the g ate trench, and forming in the gate trench the back gate region comprising the gate electrode and the gate dielectric layer on the gate electrode.

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A method for manufacturing a graphene device, the method comprising: a) providing a substrate, the substrate comprising an insulating layer and a semiconductor layer on the insulating layer; b) forming a back gate region on the insulating layer and in the semiconductor layer of the substrate, the back gate region comprising a gate electrode and a gate dielectric layer on the gate electrode, sidewalls of the gate electrode being surrounded by an isolating layer, and forming semiconductor doped regions in the semiconductor layer on opposite sides of the gate electrode; c) forming a graphene layer partially covering both the back gate region and the semiconductor doped regions; d) forming an interlayer dielectric layer; and e) forming a contact in the interlayer dielectric layer and on a portion of the gate electrode not covered by the graphene layer, and forming contacts in the interlayer dielectric layer and on portions of the semiconductor doped regions not covered by the graphene layer, wherein the substrate is an SOI substrate, and the SOI substrate comprises a top silicon, a buried oxide layer, and a back substrate; and the step b) comprises: etching the top silicon to form a gate trench; forming the semiconductor doped regions in the top silicon on opposite sides of the gate trench; formin g the isolating layer on sidewalls of the g ate trench, and forming in the gate trench the back gate region comprising the gate electrode and the gate dielectric layer on the gate electrode.

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A method for manufacturing a graphene device, the method comprising: a) providing a substrate, the substrate comprising an insulating layer and a semiconductor layer on the insulating layer; b) forming a back gate region on the insulating layer and in the semiconductor layer of the substrate, the back gate region comprising a gate electrode and a gate dielectric layer on the gate electrode, sidewalls of the gate electrode being surrounded by an isolating layer, and forming semiconductor doped regions in the semiconductor layer on opposite sides of the gate electrode; c) forming a graphene layer partially covering both the back gate region and the semiconductor doped regions; d) forming an interlayer dielectric layer; and e) forming a contact in the interlayer dielectric layer and on a portion of the gate electrode not covered by the graphene layer, and forming contacts in the interlayer dielectric layer and on portions of the semiconductor doped regions not covered by the graphene layer, wherein the substrate is an SOI substrate, and the SOI substrate comprises a top silicon, a buried oxide layer, and a back substrate; and the step b) comprises: etching the top silicon to form a gate trench; forming the semiconductor doped regions in the top silicon on opposite sides of the gate trench; formin g the isolating layer on sidewalls of the g ate trench, and forming in the gate trench the back gate region comprising the gate electrode and the gate dielectric layer on the gate electrode.

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A method for manufacturing a graphene device, the method comprising: a) providing a substrate, the substrate comprising an insulating layer and a semiconductor layer on the insulating layer; b) forming a back gate region on the insulating layer and in the semiconductor layer of the substrate, the back gate region comprising a gate electrode and a gate dielectric layer on the gate electrode, sidewalls of the gate electrode being surrounded by an isolating layer, and forming semiconductor doped regions in the semiconductor layer on opposite sides of the gate electrode; c) forming a graphene layer partially covering both the back gate region and the semiconductor doped regions; d) forming an interlayer dielectric layer; and e) forming a contact in the interlayer dielectric layer and on a portion of the gate electrode not covered by the graphene layer, and forming contacts in the interlayer dielectric layer and on portions of the semiconductor doped regions not covered by the graphene layer, wherein the substrate is an SOI substrate, and the SOI substrate comprises a top silicon, a buried oxide layer, and a back substrate; and the step b) comprises: etching the top silicon to form a gate trench; forming the semiconductor doped regions in the top silicon on opposite sides of the gate trench; formin g the isolating layer on sidewalls of the g ate trench, and forming in the gate trench the back gate region comprising the gate electrode and the gate dielectric layer on the gate electrode.

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