Patent
US 10,020,365GRAPHENE DEVICE AND METHOD OF FABRICATING A GRAPHENE DEVICE
Asta Maria Karkkainen
US
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Patent
Atlas literature
Patent
US 10,020,365Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: a substrate; a graphene semiconductor on said substrate, said graphene semiconductor comprising a porous graphene layer, said porous graphene layer having a plurality of randomly distributed pores, and including a plurality of graphene nanoribbons, each having a width between 0.1 ur n and 20 un and a porosity providing g p each with semicondu c tivity; and a gate electrode in contact with the graphene semiconductor. Currently amended
The device according to claim 1 further comprising at least one additional porous graphene layer. Previously presented
The device according to claim 1 further comprising a graphene electrode. Previously presented
Canceled
Canceled
The device according to claim [[4]] L wherein the graphene nanoribbons are substantially aligned with one another. Currently amended
Canceled
Canceled
Canceled
A method comprising etching a layer of graphene, and inhibiting said etching using a nanowire mask. Withdrawn
A method according to claim 15 wherein the method comprises depositing a multiplicity of nanowires on the later of graphene to form said nanowire mask. Withdrawn
A method according to claim 15 the nanowire mask comprises silicon, or silicon oxide. Withdrawn
A method according to cla i m 15 wherein the method comprises removing substantially all the nanowire mask after said etching. Withdrawn
An electronic device comprising: a first graphene electrode; a second graphene electrode; a graphene semiconductor; a gate electrode in contact with said graphene semiconductor between said first and second graphene electrodes; and an electrical power supply, wherein the graphene semiconductor, the first, and the second graphene electrodes are configured such that supply of a current by the electrical power supply, between a first location, in the first graphene electrode, and a second location, in the second graphene electrode, establishes a potential difference between the first location and the second location, such that the potential difference remains substantially constant with variation of the first or semiconductor comprises a porous graphene layer pores, and including a plurality of graphene and 20 n and a porosity providing g p each with
Canceled second location, and wherein the graphene having a plurality of randomly distributed nanoribbons, each having a width between 0.1 nm semiconductivity. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
graphene semiconductor device with gate electrode
electronic device with first and second graphene electrodes, graphene semiconductor, gate electrode, and electrical power supply
Materials described outside the worked examples.
porous graphene layer
graphene nanoribbons
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Porosity Range | 1–99 | porous graphene layer |
Nanoribbon Width Range | 0.1–20 |
Patent
Atlas literature
Patent
US 10,020,365Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: a substrate; a graphene semiconductor on said substrate, said graphene semiconductor comprising a porous graphene layer, said porous graphene layer having a plurality of randomly distributed pores, and including a plurality of graphene nanoribbons, each having a width between 0.1 ur n and 20 un and a porosity providing g p each with semicondu c tivity; and a gate electrode in contact with the graphene semiconductor. Currently amended
The device according to claim 1 further comprising at least one additional porous graphene layer. Previously presented
The device according to claim 1 further comprising a graphene electrode. Previously presented
Canceled
Canceled
The device according to claim [[4]] L wherein the graphene nanoribbons are substantially aligned with one another. Currently amended
Canceled
Canceled
Canceled
A method comprising etching a layer of graphene, and inhibiting said etching using a nanowire mask. Withdrawn
A method according to claim 15 wherein the method comprises depositing a multiplicity of nanowires on the later of graphene to form said nanowire mask. Withdrawn
A method according to claim 15 the nanowire mask comprises silicon, or silicon oxide. Withdrawn
A method according to cla i m 15 wherein the method comprises removing substantially all the nanowire mask after said etching. Withdrawn
An electronic device comprising: a first graphene electrode; a second graphene electrode; a graphene semiconductor; a gate electrode in contact with said graphene semiconductor between said first and second graphene electrodes; and an electrical power supply, wherein the graphene semiconductor, the first, and the second graphene electrodes are configured such that supply of a current by the electrical power supply, between a first location, in the first graphene electrode, and a second location, in the second graphene electrode, establishes a potential difference between the first location and the second location, such that the potential difference remains substantially constant with variation of the first or semiconductor comprises a porous graphene layer pores, and including a plurality of graphene and 20 n and a porosity providing g p each with
Canceled second location, and wherein the graphene having a plurality of randomly distributed nanoribbons, each having a width between 0.1 nm semiconductivity. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
graphene semiconductor device with gate electrode
electronic device with first and second graphene electrodes, graphene semiconductor, gate electrode, and electrical power supply
Materials described outside the worked examples.
porous graphene layer
graphene nanoribbons
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Porosity Range | 1–99 | porous graphene layer |
Nanoribbon Width Range | 0.1–20 |
Patent
Atlas literature
Patent
US 10,020,365Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: a substrate; a graphene semiconductor on said substrate, said graphene semiconductor comprising a porous graphene layer, said porous graphene layer having a plurality of randomly distributed pores, and including a plurality of graphene nanoribbons, each having a width between 0.1 ur n and 20 un and a porosity providing g p each with semicondu c tivity; and a gate electrode in contact with the graphene semiconductor. Currently amended
The device according to claim 1 further comprising at least one additional porous graphene layer. Previously presented
The device according to claim 1 further comprising a graphene electrode. Previously presented
Canceled
Canceled
The device according to claim [[4]] L wherein the graphene nanoribbons are substantially aligned with one another. Currently amended
Canceled
Canceled
Canceled
A method comprising etching a layer of graphene, and inhibiting said etching using a nanowire mask. Withdrawn
A method according to claim 15 wherein the method comprises depositing a multiplicity of nanowires on the later of graphene to form said nanowire mask. Withdrawn
A method according to claim 15 the nanowire mask comprises silicon, or silicon oxide. Withdrawn
A method according to cla i m 15 wherein the method comprises removing substantially all the nanowire mask after said etching. Withdrawn
An electronic device comprising: a first graphene electrode; a second graphene electrode; a graphene semiconductor; a gate electrode in contact with said graphene semiconductor between said first and second graphene electrodes; and an electrical power supply, wherein the graphene semiconductor, the first, and the second graphene electrodes are configured such that supply of a current by the electrical power supply, between a first location, in the first graphene electrode, and a second location, in the second graphene electrode, establishes a potential difference between the first location and the second location, such that the potential difference remains substantially constant with variation of the first or semiconductor comprises a porous graphene layer pores, and including a plurality of graphene and 20 n and a porosity providing g p each with
Canceled second location, and wherein the graphene having a plurality of randomly distributed nanoribbons, each having a width between 0.1 nm semiconductivity. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
graphene semiconductor device with gate electrode
electronic device with first and second graphene electrodes, graphene semiconductor, gate electrode, and electrical power supply
Materials described outside the worked examples.
porous graphene layer
graphene nanoribbons
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Porosity Range | 1–99 | porous graphene layer |
Nanoribbon Width Range | 0.1–20 |
Patent
Atlas literature
Patent
US 10,020,365Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: a substrate; a graphene semiconductor on said substrate, said graphene semiconductor comprising a porous graphene layer, said porous graphene layer having a plurality of randomly distributed pores, and including a plurality of graphene nanoribbons, each having a width between 0.1 ur n and 20 un and a porosity providing g p each with semicondu c tivity; and a gate electrode in contact with the graphene semiconductor. Currently amended
The device according to claim 1 further comprising at least one additional porous graphene layer. Previously presented
The device according to claim 1 further comprising a graphene electrode. Previously presented
Canceled
Canceled
The device according to claim [[4]] L wherein the graphene nanoribbons are substantially aligned with one another. Currently amended
Canceled
Canceled
Canceled
A method comprising etching a layer of graphene, and inhibiting said etching using a nanowire mask. Withdrawn
A method according to claim 15 wherein the method comprises depositing a multiplicity of nanowires on the later of graphene to form said nanowire mask. Withdrawn
A method according to claim 15 the nanowire mask comprises silicon, or silicon oxide. Withdrawn
A method according to cla i m 15 wherein the method comprises removing substantially all the nanowire mask after said etching. Withdrawn
An electronic device comprising: a first graphene electrode; a second graphene electrode; a graphene semiconductor; a gate electrode in contact with said graphene semiconductor between said first and second graphene electrodes; and an electrical power supply, wherein the graphene semiconductor, the first, and the second graphene electrodes are configured such that supply of a current by the electrical power supply, between a first location, in the first graphene electrode, and a second location, in the second graphene electrode, establishes a potential difference between the first location and the second location, such that the potential difference remains substantially constant with variation of the first or semiconductor comprises a porous graphene layer pores, and including a plurality of graphene and 20 n and a porosity providing g p each with
Canceled second location, and wherein the graphene having a plurality of randomly distributed nanoribbons, each having a width between 0.1 nm semiconductivity. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
graphene semiconductor device with gate electrode
electronic device with first and second graphene electrodes, graphene semiconductor, gate electrode, and electrical power supply
Materials described outside the worked examples.
porous graphene layer
graphene nanoribbons
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Porosity Range | 1–99 | porous graphene layer |
Nanoribbon Width Range | 0.1–20 |
graphene electrode
nanowire mask
silicon
Si
silicon oxide
SiO₂
Thickness | 0.1–20 nm | — |
graphene electrode
nanowire mask
silicon
Si
silicon oxide
SiO₂
Thickness | 0.1–20 nm | — |
graphene electrode
nanowire mask
silicon
Si
silicon oxide
SiO₂
Thickness | 0.1–20 nm | — |
graphene electrode
nanowire mask
silicon
Si
silicon oxide
SiO₂
Thickness | 0.1–20 nm | — |