Patent
US 11,895,768 B2PRINTED CIRCUIT BOARD SUBSTRATE COMPRISING A COATED BORON NITRIDE
Eui Kyoon Kim, Bruce Fitts, Christopher Brown
ROGERS CORPORATION, Chandler, AZ (US)·Feb. 6, 2024·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,895,768 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional illustration of an embodiment of a circuit material comprising the printed circuit board substrate;
FIG. 2 is an illustration of an embodiment of a method of preparing the printed circuit board substrate;
FIG. 3 is a graphical illustration of the aluminum con- centration with number of cycles of Examples 1-6;
FIG. 4 is a graphical illustration of the surface energy with the number of cycles of Examples 1-6; and
FIG. 5 is a graphical illustration of the dielectric strength with time of Examples 9 and 11.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A printed circuit board substrate comprising: a polymer matrix, wherein the polymer matrix comprises at least one of an epoxy, a polyphenylene ether, a polystyrene, an ethylene-propylene dicyclopentadiene copolymer, a polybutadiene, a polyisoprene, a fluo-ropolymer, or a crosslinked matrix comprising at least one of triallyl cyanurate, triallyl isocyanurate, 1,2,4-trivinyl cyclohexane, trimethylolpropane triacrylate, or trimethylolpropane trimethacrylate; a reinforcing layer; and 10 to 50 volume percent, based on the total volume of the printed circuit board substrate, of a plurality of coated boron nitride particles having an average particle size of 5 to 500 micrometers; wherein the plurality of coated boron nitride particles comprises a coating comprising aluminum oxide, wherein the coating has an average coating thickness of 0.5 to 10 nanometers, wherein the plurality of coated boron nitride particles further comprises a surface treatment; wherein the printed circuit board substrate has a peel strength of greater than or equl to 3 pli as determined in accordance with IPC-Tm-650-2,4,8; and wherein the printed circuit board has a Z-direction ther-mal conductivity that is at least 90% that of an equiva-lent printed circuit board comprising boron nitride particles without the coating comprising aluminum oxide.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles has an average particle size of 10 to 250 micrometers.
The printed circuit board substrate of claim 1, wherein the coating further comprises silicon dioxide.
The printed circuit board substrate of claim 1, wherein the average coating thickness is 1 to 10 nm.
The printed circuit board substrate of claim 1, wherein the coating is disposed over 10 to 100 A % of the total surface area of the plurality of the boron nitride particles.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles comprises less than 1 wt % of the coating based on the total weight of the plurality of coated boron nitride particles.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles comprises atomic layer deposition coated particles.
The printed circuit board substrate of claim 1, wherein the printed circuit board substrate comprises 10 to 25 vol % of the plurality of coated boron nitride particles based on the total volume of the printed circuit board substrate.
The printed circuit board substrate of claim 1, wherein the printed circuit board substrate comprises 15 to 99 vol % of the thermoset polymer matrix based on the total volume of the printed circuit board substrate.
The printed circuit board substrate of claim 1, wherein the reinforcing layer comprises a plurality of glass fibers.
The printed circuit board substrate of claim 1, wherein the polymer matrix comprises at least one of a butadiene homopolymer, an isoprene homopolymer, a butadiene-vi-nylaromatic copolymer, or an isoprene- vinylaromatic copo-lymer.
The printed circuit board substrate of claim 1, wherein the surface treatment comprises a coupling agent.
The printed circuit board substrate of claim 1, com-prising, based on the total volume of the printed circuit board substrate: 15 to 50 volume percent of the polymer matrix; 10 to 25 volume percent of the plurality of coated boron nitride particles; 20 to 50 volume percent of a secondary inorganic filler comprising a secondary inorganic dielectric filler, and a flame retardant filler; and the reinforcing layer.
A circuit material comprising the printed circuit board substrate of claim 1 and a conductive layer disposed on at least one surface of the printed circuit board substrate.
A method of making the printed circuit board substrate of claim 1, comprising forming a mixture comprising a thermosetting composi-tion and the plurality of the coated boron nitride particles; coating a reinforcing layer with the mixture; and curing the thermosetting composition to form the printed circuit board substrate.
Layer stacks claimed or described, ordered top of device to substrate.
printed circuit board substrate
circuit material
Materials described outside the worked examples.
coated boron nitride particles
BN
polymer matrix
aluminum oxide coating
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peel strength of printed circuit board substrate (IPC-TM-650-2.4.8) | ≥3 pli | BNpolymer matrix |
Z-direction thermal conductivity retention vs. uncoated BN baseline |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 39
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,895,768 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional illustration of an embodiment of a circuit material comprising the printed circuit board substrate;
FIG. 2 is an illustration of an embodiment of a method of preparing the printed circuit board substrate;
FIG. 3 is a graphical illustration of the aluminum con- centration with number of cycles of Examples 1-6;
FIG. 4 is a graphical illustration of the surface energy with the number of cycles of Examples 1-6; and
FIG. 5 is a graphical illustration of the dielectric strength with time of Examples 9 and 11.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A printed circuit board substrate comprising: a polymer matrix, wherein the polymer matrix comprises at least one of an epoxy, a polyphenylene ether, a polystyrene, an ethylene-propylene dicyclopentadiene copolymer, a polybutadiene, a polyisoprene, a fluo-ropolymer, or a crosslinked matrix comprising at least one of triallyl cyanurate, triallyl isocyanurate, 1,2,4-trivinyl cyclohexane, trimethylolpropane triacrylate, or trimethylolpropane trimethacrylate; a reinforcing layer; and 10 to 50 volume percent, based on the total volume of the printed circuit board substrate, of a plurality of coated boron nitride particles having an average particle size of 5 to 500 micrometers; wherein the plurality of coated boron nitride particles comprises a coating comprising aluminum oxide, wherein the coating has an average coating thickness of 0.5 to 10 nanometers, wherein the plurality of coated boron nitride particles further comprises a surface treatment; wherein the printed circuit board substrate has a peel strength of greater than or equl to 3 pli as determined in accordance with IPC-Tm-650-2,4,8; and wherein the printed circuit board has a Z-direction ther-mal conductivity that is at least 90% that of an equiva-lent printed circuit board comprising boron nitride particles without the coating comprising aluminum oxide.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles has an average particle size of 10 to 250 micrometers.
The printed circuit board substrate of claim 1, wherein the coating further comprises silicon dioxide.
The printed circuit board substrate of claim 1, wherein the average coating thickness is 1 to 10 nm.
The printed circuit board substrate of claim 1, wherein the coating is disposed over 10 to 100 A % of the total surface area of the plurality of the boron nitride particles.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles comprises less than 1 wt % of the coating based on the total weight of the plurality of coated boron nitride particles.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles comprises atomic layer deposition coated particles.
The printed circuit board substrate of claim 1, wherein the printed circuit board substrate comprises 10 to 25 vol % of the plurality of coated boron nitride particles based on the total volume of the printed circuit board substrate.
The printed circuit board substrate of claim 1, wherein the printed circuit board substrate comprises 15 to 99 vol % of the thermoset polymer matrix based on the total volume of the printed circuit board substrate.
The printed circuit board substrate of claim 1, wherein the reinforcing layer comprises a plurality of glass fibers.
The printed circuit board substrate of claim 1, wherein the polymer matrix comprises at least one of a butadiene homopolymer, an isoprene homopolymer, a butadiene-vi-nylaromatic copolymer, or an isoprene- vinylaromatic copo-lymer.
The printed circuit board substrate of claim 1, wherein the surface treatment comprises a coupling agent.
The printed circuit board substrate of claim 1, com-prising, based on the total volume of the printed circuit board substrate: 15 to 50 volume percent of the polymer matrix; 10 to 25 volume percent of the plurality of coated boron nitride particles; 20 to 50 volume percent of a secondary inorganic filler comprising a secondary inorganic dielectric filler, and a flame retardant filler; and the reinforcing layer.
A circuit material comprising the printed circuit board substrate of claim 1 and a conductive layer disposed on at least one surface of the printed circuit board substrate.
A method of making the printed circuit board substrate of claim 1, comprising forming a mixture comprising a thermosetting composi-tion and the plurality of the coated boron nitride particles; coating a reinforcing layer with the mixture; and curing the thermosetting composition to form the printed circuit board substrate.
Layer stacks claimed or described, ordered top of device to substrate.
printed circuit board substrate
circuit material
Materials described outside the worked examples.
coated boron nitride particles
BN
polymer matrix
aluminum oxide coating
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peel strength of printed circuit board substrate (IPC-TM-650-2.4.8) | ≥3 pli | BNpolymer matrix |
Z-direction thermal conductivity retention vs. uncoated BN baseline |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 39
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,895,768 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional illustration of an embodiment of a circuit material comprising the printed circuit board substrate;
FIG. 2 is an illustration of an embodiment of a method of preparing the printed circuit board substrate;
FIG. 3 is a graphical illustration of the aluminum con- centration with number of cycles of Examples 1-6;
FIG. 4 is a graphical illustration of the surface energy with the number of cycles of Examples 1-6; and
FIG. 5 is a graphical illustration of the dielectric strength with time of Examples 9 and 11.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A printed circuit board substrate comprising: a polymer matrix, wherein the polymer matrix comprises at least one of an epoxy, a polyphenylene ether, a polystyrene, an ethylene-propylene dicyclopentadiene copolymer, a polybutadiene, a polyisoprene, a fluo-ropolymer, or a crosslinked matrix comprising at least one of triallyl cyanurate, triallyl isocyanurate, 1,2,4-trivinyl cyclohexane, trimethylolpropane triacrylate, or trimethylolpropane trimethacrylate; a reinforcing layer; and 10 to 50 volume percent, based on the total volume of the printed circuit board substrate, of a plurality of coated boron nitride particles having an average particle size of 5 to 500 micrometers; wherein the plurality of coated boron nitride particles comprises a coating comprising aluminum oxide, wherein the coating has an average coating thickness of 0.5 to 10 nanometers, wherein the plurality of coated boron nitride particles further comprises a surface treatment; wherein the printed circuit board substrate has a peel strength of greater than or equl to 3 pli as determined in accordance with IPC-Tm-650-2,4,8; and wherein the printed circuit board has a Z-direction ther-mal conductivity that is at least 90% that of an equiva-lent printed circuit board comprising boron nitride particles without the coating comprising aluminum oxide.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles has an average particle size of 10 to 250 micrometers.
The printed circuit board substrate of claim 1, wherein the coating further comprises silicon dioxide.
The printed circuit board substrate of claim 1, wherein the average coating thickness is 1 to 10 nm.
The printed circuit board substrate of claim 1, wherein the coating is disposed over 10 to 100 A % of the total surface area of the plurality of the boron nitride particles.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles comprises less than 1 wt % of the coating based on the total weight of the plurality of coated boron nitride particles.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles comprises atomic layer deposition coated particles.
The printed circuit board substrate of claim 1, wherein the printed circuit board substrate comprises 10 to 25 vol % of the plurality of coated boron nitride particles based on the total volume of the printed circuit board substrate.
The printed circuit board substrate of claim 1, wherein the printed circuit board substrate comprises 15 to 99 vol % of the thermoset polymer matrix based on the total volume of the printed circuit board substrate.
The printed circuit board substrate of claim 1, wherein the reinforcing layer comprises a plurality of glass fibers.
The printed circuit board substrate of claim 1, wherein the polymer matrix comprises at least one of a butadiene homopolymer, an isoprene homopolymer, a butadiene-vi-nylaromatic copolymer, or an isoprene- vinylaromatic copo-lymer.
The printed circuit board substrate of claim 1, wherein the surface treatment comprises a coupling agent.
The printed circuit board substrate of claim 1, com-prising, based on the total volume of the printed circuit board substrate: 15 to 50 volume percent of the polymer matrix; 10 to 25 volume percent of the plurality of coated boron nitride particles; 20 to 50 volume percent of a secondary inorganic filler comprising a secondary inorganic dielectric filler, and a flame retardant filler; and the reinforcing layer.
A circuit material comprising the printed circuit board substrate of claim 1 and a conductive layer disposed on at least one surface of the printed circuit board substrate.
A method of making the printed circuit board substrate of claim 1, comprising forming a mixture comprising a thermosetting composi-tion and the plurality of the coated boron nitride particles; coating a reinforcing layer with the mixture; and curing the thermosetting composition to form the printed circuit board substrate.
Layer stacks claimed or described, ordered top of device to substrate.
printed circuit board substrate
circuit material
Materials described outside the worked examples.
coated boron nitride particles
BN
polymer matrix
aluminum oxide coating
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peel strength of printed circuit board substrate (IPC-TM-650-2.4.8) | ≥3 pli | BNpolymer matrix |
Z-direction thermal conductivity retention vs. uncoated BN baseline |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 39
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,895,768 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional illustration of an embodiment of a circuit material comprising the printed circuit board substrate;
FIG. 2 is an illustration of an embodiment of a method of preparing the printed circuit board substrate;
FIG. 3 is a graphical illustration of the aluminum con- centration with number of cycles of Examples 1-6;
FIG. 4 is a graphical illustration of the surface energy with the number of cycles of Examples 1-6; and
FIG. 5 is a graphical illustration of the dielectric strength with time of Examples 9 and 11.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A printed circuit board substrate comprising: a polymer matrix, wherein the polymer matrix comprises at least one of an epoxy, a polyphenylene ether, a polystyrene, an ethylene-propylene dicyclopentadiene copolymer, a polybutadiene, a polyisoprene, a fluo-ropolymer, or a crosslinked matrix comprising at least one of triallyl cyanurate, triallyl isocyanurate, 1,2,4-trivinyl cyclohexane, trimethylolpropane triacrylate, or trimethylolpropane trimethacrylate; a reinforcing layer; and 10 to 50 volume percent, based on the total volume of the printed circuit board substrate, of a plurality of coated boron nitride particles having an average particle size of 5 to 500 micrometers; wherein the plurality of coated boron nitride particles comprises a coating comprising aluminum oxide, wherein the coating has an average coating thickness of 0.5 to 10 nanometers, wherein the plurality of coated boron nitride particles further comprises a surface treatment; wherein the printed circuit board substrate has a peel strength of greater than or equl to 3 pli as determined in accordance with IPC-Tm-650-2,4,8; and wherein the printed circuit board has a Z-direction ther-mal conductivity that is at least 90% that of an equiva-lent printed circuit board comprising boron nitride particles without the coating comprising aluminum oxide.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles has an average particle size of 10 to 250 micrometers.
The printed circuit board substrate of claim 1, wherein the coating further comprises silicon dioxide.
The printed circuit board substrate of claim 1, wherein the average coating thickness is 1 to 10 nm.
The printed circuit board substrate of claim 1, wherein the coating is disposed over 10 to 100 A % of the total surface area of the plurality of the boron nitride particles.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles comprises less than 1 wt % of the coating based on the total weight of the plurality of coated boron nitride particles.
The printed circuit board substrate of claim 1, wherein the plurality of coated boron nitride particles comprises atomic layer deposition coated particles.
The printed circuit board substrate of claim 1, wherein the printed circuit board substrate comprises 10 to 25 vol % of the plurality of coated boron nitride particles based on the total volume of the printed circuit board substrate.
The printed circuit board substrate of claim 1, wherein the printed circuit board substrate comprises 15 to 99 vol % of the thermoset polymer matrix based on the total volume of the printed circuit board substrate.
The printed circuit board substrate of claim 1, wherein the reinforcing layer comprises a plurality of glass fibers.
The printed circuit board substrate of claim 1, wherein the polymer matrix comprises at least one of a butadiene homopolymer, an isoprene homopolymer, a butadiene-vi-nylaromatic copolymer, or an isoprene- vinylaromatic copo-lymer.
The printed circuit board substrate of claim 1, wherein the surface treatment comprises a coupling agent.
The printed circuit board substrate of claim 1, com-prising, based on the total volume of the printed circuit board substrate: 15 to 50 volume percent of the polymer matrix; 10 to 25 volume percent of the plurality of coated boron nitride particles; 20 to 50 volume percent of a secondary inorganic filler comprising a secondary inorganic dielectric filler, and a flame retardant filler; and the reinforcing layer.
A circuit material comprising the printed circuit board substrate of claim 1 and a conductive layer disposed on at least one surface of the printed circuit board substrate.
A method of making the printed circuit board substrate of claim 1, comprising forming a mixture comprising a thermosetting composi-tion and the plurality of the coated boron nitride particles; coating a reinforcing layer with the mixture; and curing the thermosetting composition to form the printed circuit board substrate.
Layer stacks claimed or described, ordered top of device to substrate.
printed circuit board substrate
circuit material
Materials described outside the worked examples.
coated boron nitride particles
BN
polymer matrix
aluminum oxide coating
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
peel strength of printed circuit board substrate (IPC-TM-650-2.4.8) | ≥3 pli | BNpolymer matrix |
Z-direction thermal conductivity retention vs. uncoated BN baseline |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 39
Related documents with shared materials, methods, properties, or citations.
Al₂O₃
silicon dioxide
SiO₂
glass fibers
secondary inorganic filler (dielectric and flame retardant)
| ≥90 % |
BN |
Z-direction thermal conductivity (ASTM D5470-17, TIM Tester 1300) | ≥ 0.8 W/mK | BNpolymer matrix |
Water absorption (ASTM D570-98(2018)) | ≤0.15 wt% | polymer matrix |
Intrinsic thermal conductivity of hexagonal boron nitride particles | 10–300 W/mK | BN |
Thickness | 0.5–100 nm | — |
Thickness | 1–100 nm | — |
Thickness | 0.1–1000 µm | — |
Thickness | 5–500 µm | — |
Thickness | 25–150 µm | — |
Thickness | 0.5–30 nm | — |
Thickness | 1–20 nm | — |
Thickness | 500–100000 nm | — |
Thickness | 10–250 µm | — |
Thickness | 3–40 µm | — |
Thickness | 0.1–100 nm | — |
Thickness | 1–10 nm | — |
Temperature | 150–200 °C | — |
Duration | 6–10 hours | — |
Temperature | 500–1500 °C | — |
Duration | 4–18 hours | — |
Thickness | 400–500 µm | — |
Thickness | 30–40 µm | — |
Pressure | 1–90 pa | — |
Thickness | 3–200 µm | — |
Thickness | 9–180 µm | — |
Temperature | 150–390 °C | — |
Pressure | 2–20 pa | — |
Thickness | ≤ 1 µm | — |
Duration | ≥ 4 hours | — |
Thickness | 0.5–10 nm | — |
Cited non-patent literature · 8
Al₂O₃
silicon dioxide
SiO₂
glass fibers
secondary inorganic filler (dielectric and flame retardant)
| ≥90 % |
BN |
Z-direction thermal conductivity (ASTM D5470-17, TIM Tester 1300) | ≥ 0.8 W/mK | BNpolymer matrix |
Water absorption (ASTM D570-98(2018)) | ≤0.15 wt% | polymer matrix |
Intrinsic thermal conductivity of hexagonal boron nitride particles | 10–300 W/mK | BN |
Thickness | 0.5–100 nm | — |
Thickness | 1–100 nm | — |
Thickness | 0.1–1000 µm | — |
Thickness | 5–500 µm | — |
Thickness | 25–150 µm | — |
Thickness | 0.5–30 nm | — |
Thickness | 1–20 nm | — |
Thickness | 500–100000 nm | — |
Thickness | 10–250 µm | — |
Thickness | 3–40 µm | — |
Thickness | 0.1–100 nm | — |
Thickness | 1–10 nm | — |
Temperature | 150–200 °C | — |
Duration | 6–10 hours | — |
Temperature | 500–1500 °C | — |
Duration | 4–18 hours | — |
Thickness | 400–500 µm | — |
Thickness | 30–40 µm | — |
Pressure | 1–90 pa | — |
Thickness | 3–200 µm | — |
Thickness | 9–180 µm | — |
Temperature | 150–390 °C | — |
Pressure | 2–20 pa | — |
Thickness | ≤ 1 µm | — |
Duration | ≥ 4 hours | — |
Thickness | 0.5–10 nm | — |
Cited non-patent literature · 8
Al₂O₃
silicon dioxide
SiO₂
glass fibers
secondary inorganic filler (dielectric and flame retardant)
| ≥90 % |
BN |
Z-direction thermal conductivity (ASTM D5470-17, TIM Tester 1300) | ≥ 0.8 W/mK | BNpolymer matrix |
Water absorption (ASTM D570-98(2018)) | ≤0.15 wt% | polymer matrix |
Intrinsic thermal conductivity of hexagonal boron nitride particles | 10–300 W/mK | BN |
Thickness | 0.5–100 nm | — |
Thickness | 1–100 nm | — |
Thickness | 0.1–1000 µm | — |
Thickness | 5–500 µm | — |
Thickness | 25–150 µm | — |
Thickness | 0.5–30 nm | — |
Thickness | 1–20 nm | — |
Thickness | 500–100000 nm | — |
Thickness | 10–250 µm | — |
Thickness | 3–40 µm | — |
Thickness | 0.1–100 nm | — |
Thickness | 1–10 nm | — |
Temperature | 150–200 °C | — |
Duration | 6–10 hours | — |
Temperature | 500–1500 °C | — |
Duration | 4–18 hours | — |
Thickness | 400–500 µm | — |
Thickness | 30–40 µm | — |
Pressure | 1–90 pa | — |
Thickness | 3–200 µm | — |
Thickness | 9–180 µm | — |
Temperature | 150–390 °C | — |
Pressure | 2–20 pa | — |
Thickness | ≤ 1 µm | — |
Duration | ≥ 4 hours | — |
Thickness | 0.5–10 nm | — |
Cited non-patent literature · 8
Al₂O₃
silicon dioxide
SiO₂
glass fibers
secondary inorganic filler (dielectric and flame retardant)
| ≥90 % |
BN |
Z-direction thermal conductivity (ASTM D5470-17, TIM Tester 1300) | ≥ 0.8 W/mK | BNpolymer matrix |
Water absorption (ASTM D570-98(2018)) | ≤0.15 wt% | polymer matrix |
Intrinsic thermal conductivity of hexagonal boron nitride particles | 10–300 W/mK | BN |
Thickness | 0.5–100 nm | — |
Thickness | 1–100 nm | — |
Thickness | 0.1–1000 µm | — |
Thickness | 5–500 µm | — |
Thickness | 25–150 µm | — |
Thickness | 0.5–30 nm | — |
Thickness | 1–20 nm | — |
Thickness | 500–100000 nm | — |
Thickness | 10–250 µm | — |
Thickness | 3–40 µm | — |
Thickness | 0.1–100 nm | — |
Thickness | 1–10 nm | — |
Temperature | 150–200 °C | — |
Duration | 6–10 hours | — |
Temperature | 500–1500 °C | — |
Duration | 4–18 hours | — |
Thickness | 400–500 µm | — |
Thickness | 30–40 µm | — |
Pressure | 1–90 pa | — |
Thickness | 3–200 µm | — |
Thickness | 9–180 µm | — |
Temperature | 150–390 °C | — |
Pressure | 2–20 pa | — |
Thickness | ≤ 1 µm | — |
Duration | ≥ 4 hours | — |
Thickness | 0.5–10 nm | — |
Cited non-patent literature · 8