Patent
US 9,536,965SEMICONDUCTOR DEVICE
Yi PEI
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,536,965Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a schematic cross-sectional view of a semiconductor device according to a first embodiment; 15
FIG. 2 shows a schematic top view of the semiconductor device according to the first embodiment;
FIG. 3 shows a schematic top view of a semiconductor device according to a second embodiment;
FIG. 4 shows a schematic cross-sectional temperature view of a semiconductor 20 device according to the prior art;
FIG. 5 shows a schematic cross-sectional temperature view of the semiconductor device according to the second embodiment;
FIG. 6 shows a schematic cross-sectional view of an active region of a semiconductor device according to a third embodiment; 25
FIG. 7 shows a schematic cross-sectional view of a semiconductor device according to a fourth embodiment in which a backside via is located at a first source …
FIG. 8 shows a schematic cross-sectional temperature view of the semiconductor device according to the fourth embodiment in which gold is filled in the backside …
FIG. 9 shows a schematic cross-sectional temperature view of the semiconductor device according to the fourth embodiment in which graphene is filled in the …
FIG. 10 shows a schematic cross-sectional view of a semiconductor device according to a fifth embodiment in which a backside via is located at a first source …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital interdigitated fingers among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion. a first heat dissipating layer disposed on the first gate portion and a second heat dissipating layer disposed on one or more of the first source portion, the first drain portion, the second source portion, the second drain portion and the second gate portion.
A semiconductor device, comprising: a substrate; 7 a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigitated fingers among the first source portion and the first drain portion; and The semiconductor device of claim 1, wherein the heat dissipating layer comprises a third heat dissipating layer disposed on the first gate portion and a fourth heat dissipating layer disposed in one or more of the first source portion, the first drain portion, the second source portion, the second drain portion and the second gate portion.
A semiconductor device, comprising: a substrate; a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigitated fingers among the first source portion and the first drain portion; The semiconductor device of claim 1, further comprising: a back metal located on a surface of the substrate opposite to the multilayer semiconductor layer; and a backside via below one of the first source portion and the second source portion, the backside via penetrating through the multilayer semiconductor layer and the substrate and being coupled to the back metal [[,]]; and wherein the heat dissipating layer comprises a fifth heat dissipating layer disposed in the backside via.
The semiconductor device of claim 1, wherein the first heat dissipating layer and the second dissipating layer i-s are made of a material selected from the group consisting of single layer graphene, bilayer graphene, multilayer graphene, graphene nanosheets, single-walled carbon nanotube and multi-walled carbon nanotube or combination thereof.
The semiconductor device of claim 1, wherein the multilayer semiconductor layer comprises: a nucleation layer located on the substrate; 10 a buffer layer located on the nucleation layer; a barrier layer located on the buffer layer, the barrier layer and the buffer layer forming a heterojunction structure, two dimensional electron gas being formed at an interface of the heterojunction; and a capping layer located on the barrier layer, wherein the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion are located on the capping layer.
canceled
The semiconductor device of claim [[2]] 1, further comprising: a first dielectric layer disposed on the multilayer semiconductor layer between the first source portion and the first gate portion and between the first drain portion and the first gate portion; and a second dielectric layer disposed on the first heat dissipating layer and on the first dielectric layer between the first source portion and the first gate portion and between the first drain portion and the first gate portion.
The semiconductor device of claim 3, further comprising a third dielectric layer disposed on the second heat dissipating layer and the second dielectric layer.
canceled
The semiconductor device of claim [[2]] 1, wherein the second source portion is coupled to the first source portion via an air bridge, the second heat dissipating layer is further disposed on the air bridge.
The semiconductor device of claim [[2]] 1, wherein the second drain portion is coupled to the first drain portion via a drain interconnection metal, the second heat dissipating layer is further disposed on the drain interconnection metal.
The semiconductor device of claim [[2]] 1, further comprising a heat sink which is disposed at edges of the passive region and is connected to the second heat dissipating layer.
The semiconductor device of claim 8, wherein the heat sink is made of ceramic.
Layer stacks claimed or described, ordered top of device to substrate.
GaN semiconductor device with heat dissipating layer (top-side)
Materials described outside the worked examples.
graphene (single layer, bilayer, multilayer, nanosheets)
carbon nanotube (single-walled and multi-walled)
Patent
Atlas literature
Patent
US 9,536,965Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a schematic cross-sectional view of a semiconductor device according to a first embodiment; 15
FIG. 2 shows a schematic top view of the semiconductor device according to the first embodiment;
FIG. 3 shows a schematic top view of a semiconductor device according to a second embodiment;
FIG. 4 shows a schematic cross-sectional temperature view of a semiconductor 20 device according to the prior art;
FIG. 5 shows a schematic cross-sectional temperature view of the semiconductor device according to the second embodiment;
FIG. 6 shows a schematic cross-sectional view of an active region of a semiconductor device according to a third embodiment; 25
FIG. 7 shows a schematic cross-sectional view of a semiconductor device according to a fourth embodiment in which a backside via is located at a first source …
FIG. 8 shows a schematic cross-sectional temperature view of the semiconductor device according to the fourth embodiment in which gold is filled in the backside …
FIG. 9 shows a schematic cross-sectional temperature view of the semiconductor device according to the fourth embodiment in which graphene is filled in the …
FIG. 10 shows a schematic cross-sectional view of a semiconductor device according to a fifth embodiment in which a backside via is located at a first source …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital interdigitated fingers among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion. a first heat dissipating layer disposed on the first gate portion and a second heat dissipating layer disposed on one or more of the first source portion, the first drain portion, the second source portion, the second drain portion and the second gate portion.
A semiconductor device, comprising: a substrate; 7 a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigitated fingers among the first source portion and the first drain portion; and The semiconductor device of claim 1, wherein the heat dissipating layer comprises a third heat dissipating layer disposed on the first gate portion and a fourth heat dissipating layer disposed in one or more of the first source portion, the first drain portion, the second source portion, the second drain portion and the second gate portion.
A semiconductor device, comprising: a substrate; a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigitated fingers among the first source portion and the first drain portion; The semiconductor device of claim 1, further comprising: a back metal located on a surface of the substrate opposite to the multilayer semiconductor layer; and a backside via below one of the first source portion and the second source portion, the backside via penetrating through the multilayer semiconductor layer and the substrate and being coupled to the back metal [[,]]; and wherein the heat dissipating layer comprises a fifth heat dissipating layer disposed in the backside via.
The semiconductor device of claim 1, wherein the first heat dissipating layer and the second dissipating layer i-s are made of a material selected from the group consisting of single layer graphene, bilayer graphene, multilayer graphene, graphene nanosheets, single-walled carbon nanotube and multi-walled carbon nanotube or combination thereof.
The semiconductor device of claim 1, wherein the multilayer semiconductor layer comprises: a nucleation layer located on the substrate; 10 a buffer layer located on the nucleation layer; a barrier layer located on the buffer layer, the barrier layer and the buffer layer forming a heterojunction structure, two dimensional electron gas being formed at an interface of the heterojunction; and a capping layer located on the barrier layer, wherein the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion are located on the capping layer.
canceled
The semiconductor device of claim [[2]] 1, further comprising: a first dielectric layer disposed on the multilayer semiconductor layer between the first source portion and the first gate portion and between the first drain portion and the first gate portion; and a second dielectric layer disposed on the first heat dissipating layer and on the first dielectric layer between the first source portion and the first gate portion and between the first drain portion and the first gate portion.
The semiconductor device of claim 3, further comprising a third dielectric layer disposed on the second heat dissipating layer and the second dielectric layer.
canceled
The semiconductor device of claim [[2]] 1, wherein the second source portion is coupled to the first source portion via an air bridge, the second heat dissipating layer is further disposed on the air bridge.
The semiconductor device of claim [[2]] 1, wherein the second drain portion is coupled to the first drain portion via a drain interconnection metal, the second heat dissipating layer is further disposed on the drain interconnection metal.
The semiconductor device of claim [[2]] 1, further comprising a heat sink which is disposed at edges of the passive region and is connected to the second heat dissipating layer.
The semiconductor device of claim 8, wherein the heat sink is made of ceramic.
Layer stacks claimed or described, ordered top of device to substrate.
GaN semiconductor device with heat dissipating layer (top-side)
Materials described outside the worked examples.
graphene (single layer, bilayer, multilayer, nanosheets)
carbon nanotube (single-walled and multi-walled)
Patent
Atlas literature
Patent
US 9,536,965Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a schematic cross-sectional view of a semiconductor device according to a first embodiment; 15
FIG. 2 shows a schematic top view of the semiconductor device according to the first embodiment;
FIG. 3 shows a schematic top view of a semiconductor device according to a second embodiment;
FIG. 4 shows a schematic cross-sectional temperature view of a semiconductor 20 device according to the prior art;
FIG. 5 shows a schematic cross-sectional temperature view of the semiconductor device according to the second embodiment;
FIG. 6 shows a schematic cross-sectional view of an active region of a semiconductor device according to a third embodiment; 25
FIG. 7 shows a schematic cross-sectional view of a semiconductor device according to a fourth embodiment in which a backside via is located at a first source …
FIG. 8 shows a schematic cross-sectional temperature view of the semiconductor device according to the fourth embodiment in which gold is filled in the backside …
FIG. 9 shows a schematic cross-sectional temperature view of the semiconductor device according to the fourth embodiment in which graphene is filled in the …
FIG. 10 shows a schematic cross-sectional view of a semiconductor device according to a fifth embodiment in which a backside via is located at a first source …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital interdigitated fingers among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion. a first heat dissipating layer disposed on the first gate portion and a second heat dissipating layer disposed on one or more of the first source portion, the first drain portion, the second source portion, the second drain portion and the second gate portion.
A semiconductor device, comprising: a substrate; 7 a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigitated fingers among the first source portion and the first drain portion; and The semiconductor device of claim 1, wherein the heat dissipating layer comprises a third heat dissipating layer disposed on the first gate portion and a fourth heat dissipating layer disposed in one or more of the first source portion, the first drain portion, the second source portion, the second drain portion and the second gate portion.
A semiconductor device, comprising: a substrate; a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigitated fingers among the first source portion and the first drain portion; The semiconductor device of claim 1, further comprising: a back metal located on a surface of the substrate opposite to the multilayer semiconductor layer; and a backside via below one of the first source portion and the second source portion, the backside via penetrating through the multilayer semiconductor layer and the substrate and being coupled to the back metal [[,]]; and wherein the heat dissipating layer comprises a fifth heat dissipating layer disposed in the backside via.
The semiconductor device of claim 1, wherein the first heat dissipating layer and the second dissipating layer i-s are made of a material selected from the group consisting of single layer graphene, bilayer graphene, multilayer graphene, graphene nanosheets, single-walled carbon nanotube and multi-walled carbon nanotube or combination thereof.
The semiconductor device of claim 1, wherein the multilayer semiconductor layer comprises: a nucleation layer located on the substrate; 10 a buffer layer located on the nucleation layer; a barrier layer located on the buffer layer, the barrier layer and the buffer layer forming a heterojunction structure, two dimensional electron gas being formed at an interface of the heterojunction; and a capping layer located on the barrier layer, wherein the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion are located on the capping layer.
canceled
The semiconductor device of claim [[2]] 1, further comprising: a first dielectric layer disposed on the multilayer semiconductor layer between the first source portion and the first gate portion and between the first drain portion and the first gate portion; and a second dielectric layer disposed on the first heat dissipating layer and on the first dielectric layer between the first source portion and the first gate portion and between the first drain portion and the first gate portion.
The semiconductor device of claim 3, further comprising a third dielectric layer disposed on the second heat dissipating layer and the second dielectric layer.
canceled
The semiconductor device of claim [[2]] 1, wherein the second source portion is coupled to the first source portion via an air bridge, the second heat dissipating layer is further disposed on the air bridge.
The semiconductor device of claim [[2]] 1, wherein the second drain portion is coupled to the first drain portion via a drain interconnection metal, the second heat dissipating layer is further disposed on the drain interconnection metal.
The semiconductor device of claim [[2]] 1, further comprising a heat sink which is disposed at edges of the passive region and is connected to the second heat dissipating layer.
The semiconductor device of claim 8, wherein the heat sink is made of ceramic.
Layer stacks claimed or described, ordered top of device to substrate.
GaN semiconductor device with heat dissipating layer (top-side)
Materials described outside the worked examples.
graphene (single layer, bilayer, multilayer, nanosheets)
carbon nanotube (single-walled and multi-walled)
Patent
Atlas literature
Patent
US 9,536,965Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a schematic cross-sectional view of a semiconductor device according to a first embodiment; 15
FIG. 2 shows a schematic top view of the semiconductor device according to the first embodiment;
FIG. 3 shows a schematic top view of a semiconductor device according to a second embodiment;
FIG. 4 shows a schematic cross-sectional temperature view of a semiconductor 20 device according to the prior art;
FIG. 5 shows a schematic cross-sectional temperature view of the semiconductor device according to the second embodiment;
FIG. 6 shows a schematic cross-sectional view of an active region of a semiconductor device according to a third embodiment; 25
FIG. 7 shows a schematic cross-sectional view of a semiconductor device according to a fourth embodiment in which a backside via is located at a first source …
FIG. 8 shows a schematic cross-sectional temperature view of the semiconductor device according to the fourth embodiment in which gold is filled in the backside …
FIG. 9 shows a schematic cross-sectional temperature view of the semiconductor device according to the fourth embodiment in which graphene is filled in the …
FIG. 10 shows a schematic cross-sectional view of a semiconductor device according to a fifth embodiment in which a backside via is located at a first source …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital interdigitated fingers among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion. a first heat dissipating layer disposed on the first gate portion and a second heat dissipating layer disposed on one or more of the first source portion, the first drain portion, the second source portion, the second drain portion and the second gate portion.
A semiconductor device, comprising: a substrate; 7 a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigitated fingers among the first source portion and the first drain portion; and The semiconductor device of claim 1, wherein the heat dissipating layer comprises a third heat dissipating layer disposed on the first gate portion and a fourth heat dissipating layer disposed in one or more of the first source portion, the first drain portion, the second source portion, the second drain portion and the second gate portion.
A semiconductor device, comprising: a substrate; a multilayer semiconductor layer located on the substrate, the multilayer semiconductor layer including an active region and a passive region located outside the active region; a source located on the multilayer semiconductor layer, the source including a first source portion inside the active region and a second source portion inside the passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigitated fingers among the first source portion and the first drain portion; The semiconductor device of claim 1, further comprising: a back metal located on a surface of the substrate opposite to the multilayer semiconductor layer; and a backside via below one of the first source portion and the second source portion, the backside via penetrating through the multilayer semiconductor layer and the substrate and being coupled to the back metal [[,]]; and wherein the heat dissipating layer comprises a fifth heat dissipating layer disposed in the backside via.
The semiconductor device of claim 1, wherein the first heat dissipating layer and the second dissipating layer i-s are made of a material selected from the group consisting of single layer graphene, bilayer graphene, multilayer graphene, graphene nanosheets, single-walled carbon nanotube and multi-walled carbon nanotube or combination thereof.
The semiconductor device of claim 1, wherein the multilayer semiconductor layer comprises: a nucleation layer located on the substrate; 10 a buffer layer located on the nucleation layer; a barrier layer located on the buffer layer, the barrier layer and the buffer layer forming a heterojunction structure, two dimensional electron gas being formed at an interface of the heterojunction; and a capping layer located on the barrier layer, wherein the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion are located on the capping layer.
canceled
The semiconductor device of claim [[2]] 1, further comprising: a first dielectric layer disposed on the multilayer semiconductor layer between the first source portion and the first gate portion and between the first drain portion and the first gate portion; and a second dielectric layer disposed on the first heat dissipating layer and on the first dielectric layer between the first source portion and the first gate portion and between the first drain portion and the first gate portion.
The semiconductor device of claim 3, further comprising a third dielectric layer disposed on the second heat dissipating layer and the second dielectric layer.
canceled
The semiconductor device of claim [[2]] 1, wherein the second source portion is coupled to the first source portion via an air bridge, the second heat dissipating layer is further disposed on the air bridge.
The semiconductor device of claim [[2]] 1, wherein the second drain portion is coupled to the first drain portion via a drain interconnection metal, the second heat dissipating layer is further disposed on the drain interconnection metal.
The semiconductor device of claim [[2]] 1, further comprising a heat sink which is disposed at edges of the passive region and is connected to the second heat dissipating layer.
The semiconductor device of claim 8, wherein the heat sink is made of ceramic.
Layer stacks claimed or described, ordered top of device to substrate.
GaN semiconductor device with heat dissipating layer (top-side)
Materials described outside the worked examples.
graphene (single layer, bilayer, multilayer, nanosheets)
carbon nanotube (single-walled and multi-walled)
GaN semiconductor device with backside via heat dissipating layer
ceramic
GaN multilayer semiconductor
GaN
GaN semiconductor device with backside via heat dissipating layer
ceramic
GaN multilayer semiconductor
GaN
GaN semiconductor device with backside via heat dissipating layer
ceramic
GaN multilayer semiconductor
GaN
GaN semiconductor device with backside via heat dissipating layer
ceramic
GaN multilayer semiconductor
GaN