Patent
US 9,070,677SEMICONDUCTOR PACKAGES
Soojeoung Park
US
Copyright © 2026 Matter42. All rights reserved.
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US 9,070,677Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts; [0028]
FIG. 2 is a cross-sectional view illustrating a semiconductor device according to other embodiments of the inventive concepts; 10 [0029]
FIG. 3 is a plan view illustrating a semiconductor package according to some embodiments of the inventive concepts; [0030]
FIG. 4 is a cross-sectional view taken along a line A-B of
FIG. 5 is a plan view illustrating a semiconductor package according to other embodiments of the inventive concepts; 15 [0032]
FIG. 6 is a cross-sectional view taken along a line A-B of
FIG. 7 is a plan view illustrating a semiconductor package according to other embodiments of the inventive concepts; [0034]
FIG. 8 is a cross-sectional view taken along a line A-B of
FIG. 9 is a plan view illustrating a semiconductor package according to other 20 embodiments of the inventive concepts; [0036]
FIG. 10 is a cross-sectional view taken along a line A-B of
FIGS. 11 and 12 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to embodiments of the inventive concepts; …
FIG. 12, a connection member 232 may be formed in the first opening 261, so that the ground solder 231m may be electrically connected to the lower graphene …
FIG. 13 is a schematic block diagram illustrating an example of electronic systems including semiconductor packages according to embodiments of the inventive …
FIG. 14 is a schematic block diagram illustrating an example of memory systems including semiconductor packages according to embodiments of the inventive …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A semiconductor package comprising: a lower package comprising a lower substrate, a lower semiconductor chip on the lower substrate, a lower graphene layer on the lower semiconductor chip, and a lower molding layer between the lower substrate and the lower graphene layer; an upper package on the lower substrate, the upper package spaced apart from the lower package, the upper package comprising an upper substrate, an upper semiconductor chip, and an upper molding layer; and lower conductive bumps between the lower substrate and the upper substrate, the lower conductive bumps comprising a g round bump and a signal transmitting bump.
The semiconductor package of claim 1, further comprising a first opening and a second opening in the lower molding layer and the lower graphene layer; wherein the first opening exposes an upper portion of the ground bump; and wherein the second opening exposes an upper portion of the signal transmitting bump. -3- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059
The semiconductor package of claim 1, further comprising an upper graphene layer on the upper semiconductor chip.
The semiconductor package of claim 1, wherein the lower package further comprises a lower coating layer on the lower graphene layer.
The semiconductor package of claim 1, wherein the lower package further comprises: a lower side graphene layer and a lower side coating layer on the lower side graphene layer; wherein the lower molding layer includes a t op surface, a bottom surface opposite the top surface, and a sidewall between an edge of the top surface and an edge of the bottom surface; and wherein the lower side graphene layer is on the sidewall of the lower molding layer.
The semiconductor package of claim 1, further comprising an air gap between the lower graphene layer and the upper substrate.
The semiconductor package of claim 1, wherein the lower graphene layer is in direct contact with the lower semiconductor chip.
A semiconductor package comprising: a substrate; -5- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059 a semiconductor chip on the substrate; conductive bumps laterally surrounding the semiconductor chip on the substrate; a graphene layer on the semiconductor chip; and a molding layer between the substrate and the graphene layer, wherein the graphene layer is electrically connected to the conductive bumps.
The semiconductor package of claim 13, further comprising a coating layer covering the graphene layer.
The semiconductor package of claim 13, further comprising a side graphene layer covering a sidewall of the molding layer.
A semiconductor package comprising: a substrate; a semiconductor chip on the substrate and electrically connected to the substrate; a molding layer on the substrate and at a side of the semiconductor chip; a graphene layer directly on the semiconductor chip and on the molding layer opposite the substrate; and conductive bumps on the substrate and through the molding layer, the conductive bumps in contact with the substrate and the graphene layer to electrically connect the substrate and the graphene layer, the molding layer positioned between the conductive bumps and the semiconductor chip. -6- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059
The semiconductor package of claim 16, wherein the graphene layer is further at sidewalls of the molding layer.
The semiconductor package of claim 16, wherein the conductive bumps comprise ground signal bumps.
The semiconductor package of claim 16, further comprising conductive signal bumps on the substrate and th r ough the molding layer, the conductive bumps in contact with the substrate and isolated from the graphene layer.
The semiconductor package of claim 16, further comprising a coating layer on the graphene layer. -7-
Layer stacks claimed or described, ordered top of device to substrate.
stacked semiconductor package (lower + upper package)
Materials described outside the worked examples.
graphene layer (lower)
graphene layer (upper)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12, a connection member 232 may be formed in the first opening 261, so that the ground solder 231m may be electrically connected to the lower graphene …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,070,677Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts; [0028]
FIG. 2 is a cross-sectional view illustrating a semiconductor device according to other embodiments of the inventive concepts; 10 [0029]
FIG. 3 is a plan view illustrating a semiconductor package according to some embodiments of the inventive concepts; [0030]
FIG. 4 is a cross-sectional view taken along a line A-B of
FIG. 5 is a plan view illustrating a semiconductor package according to other embodiments of the inventive concepts; 15 [0032]
FIG. 6 is a cross-sectional view taken along a line A-B of
FIG. 7 is a plan view illustrating a semiconductor package according to other embodiments of the inventive concepts; [0034]
FIG. 8 is a cross-sectional view taken along a line A-B of
FIG. 9 is a plan view illustrating a semiconductor package according to other 20 embodiments of the inventive concepts; [0036]
FIG. 10 is a cross-sectional view taken along a line A-B of
FIGS. 11 and 12 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to embodiments of the inventive concepts; …
FIG. 12, a connection member 232 may be formed in the first opening 261, so that the ground solder 231m may be electrically connected to the lower graphene …
FIG. 13 is a schematic block diagram illustrating an example of electronic systems including semiconductor packages according to embodiments of the inventive …
FIG. 14 is a schematic block diagram illustrating an example of memory systems including semiconductor packages according to embodiments of the inventive …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A semiconductor package comprising: a lower package comprising a lower substrate, a lower semiconductor chip on the lower substrate, a lower graphene layer on the lower semiconductor chip, and a lower molding layer between the lower substrate and the lower graphene layer; an upper package on the lower substrate, the upper package spaced apart from the lower package, the upper package comprising an upper substrate, an upper semiconductor chip, and an upper molding layer; and lower conductive bumps between the lower substrate and the upper substrate, the lower conductive bumps comprising a g round bump and a signal transmitting bump.
The semiconductor package of claim 1, further comprising a first opening and a second opening in the lower molding layer and the lower graphene layer; wherein the first opening exposes an upper portion of the ground bump; and wherein the second opening exposes an upper portion of the signal transmitting bump. -3- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059
The semiconductor package of claim 1, further comprising an upper graphene layer on the upper semiconductor chip.
The semiconductor package of claim 1, wherein the lower package further comprises a lower coating layer on the lower graphene layer.
The semiconductor package of claim 1, wherein the lower package further comprises: a lower side graphene layer and a lower side coating layer on the lower side graphene layer; wherein the lower molding layer includes a t op surface, a bottom surface opposite the top surface, and a sidewall between an edge of the top surface and an edge of the bottom surface; and wherein the lower side graphene layer is on the sidewall of the lower molding layer.
The semiconductor package of claim 1, further comprising an air gap between the lower graphene layer and the upper substrate.
The semiconductor package of claim 1, wherein the lower graphene layer is in direct contact with the lower semiconductor chip.
A semiconductor package comprising: a substrate; -5- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059 a semiconductor chip on the substrate; conductive bumps laterally surrounding the semiconductor chip on the substrate; a graphene layer on the semiconductor chip; and a molding layer between the substrate and the graphene layer, wherein the graphene layer is electrically connected to the conductive bumps.
The semiconductor package of claim 13, further comprising a coating layer covering the graphene layer.
The semiconductor package of claim 13, further comprising a side graphene layer covering a sidewall of the molding layer.
A semiconductor package comprising: a substrate; a semiconductor chip on the substrate and electrically connected to the substrate; a molding layer on the substrate and at a side of the semiconductor chip; a graphene layer directly on the semiconductor chip and on the molding layer opposite the substrate; and conductive bumps on the substrate and through the molding layer, the conductive bumps in contact with the substrate and the graphene layer to electrically connect the substrate and the graphene layer, the molding layer positioned between the conductive bumps and the semiconductor chip. -6- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059
The semiconductor package of claim 16, wherein the graphene layer is further at sidewalls of the molding layer.
The semiconductor package of claim 16, wherein the conductive bumps comprise ground signal bumps.
The semiconductor package of claim 16, further comprising conductive signal bumps on the substrate and th r ough the molding layer, the conductive bumps in contact with the substrate and isolated from the graphene layer.
The semiconductor package of claim 16, further comprising a coating layer on the graphene layer. -7-
Layer stacks claimed or described, ordered top of device to substrate.
stacked semiconductor package (lower + upper package)
Materials described outside the worked examples.
graphene layer (lower)
graphene layer (upper)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12, a connection member 232 may be formed in the first opening 261, so that the ground solder 231m may be electrically connected to the lower graphene …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,070,677Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts; [0028]
FIG. 2 is a cross-sectional view illustrating a semiconductor device according to other embodiments of the inventive concepts; 10 [0029]
FIG. 3 is a plan view illustrating a semiconductor package according to some embodiments of the inventive concepts; [0030]
FIG. 4 is a cross-sectional view taken along a line A-B of
FIG. 5 is a plan view illustrating a semiconductor package according to other embodiments of the inventive concepts; 15 [0032]
FIG. 6 is a cross-sectional view taken along a line A-B of
FIG. 7 is a plan view illustrating a semiconductor package according to other embodiments of the inventive concepts; [0034]
FIG. 8 is a cross-sectional view taken along a line A-B of
FIG. 9 is a plan view illustrating a semiconductor package according to other 20 embodiments of the inventive concepts; [0036]
FIG. 10 is a cross-sectional view taken along a line A-B of
FIGS. 11 and 12 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to embodiments of the inventive concepts; …
FIG. 12, a connection member 232 may be formed in the first opening 261, so that the ground solder 231m may be electrically connected to the lower graphene …
FIG. 13 is a schematic block diagram illustrating an example of electronic systems including semiconductor packages according to embodiments of the inventive …
FIG. 14 is a schematic block diagram illustrating an example of memory systems including semiconductor packages according to embodiments of the inventive …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A semiconductor package comprising: a lower package comprising a lower substrate, a lower semiconductor chip on the lower substrate, a lower graphene layer on the lower semiconductor chip, and a lower molding layer between the lower substrate and the lower graphene layer; an upper package on the lower substrate, the upper package spaced apart from the lower package, the upper package comprising an upper substrate, an upper semiconductor chip, and an upper molding layer; and lower conductive bumps between the lower substrate and the upper substrate, the lower conductive bumps comprising a g round bump and a signal transmitting bump.
The semiconductor package of claim 1, further comprising a first opening and a second opening in the lower molding layer and the lower graphene layer; wherein the first opening exposes an upper portion of the ground bump; and wherein the second opening exposes an upper portion of the signal transmitting bump. -3- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059
The semiconductor package of claim 1, further comprising an upper graphene layer on the upper semiconductor chip.
The semiconductor package of claim 1, wherein the lower package further comprises a lower coating layer on the lower graphene layer.
The semiconductor package of claim 1, wherein the lower package further comprises: a lower side graphene layer and a lower side coating layer on the lower side graphene layer; wherein the lower molding layer includes a t op surface, a bottom surface opposite the top surface, and a sidewall between an edge of the top surface and an edge of the bottom surface; and wherein the lower side graphene layer is on the sidewall of the lower molding layer.
The semiconductor package of claim 1, further comprising an air gap between the lower graphene layer and the upper substrate.
The semiconductor package of claim 1, wherein the lower graphene layer is in direct contact with the lower semiconductor chip.
A semiconductor package comprising: a substrate; -5- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059 a semiconductor chip on the substrate; conductive bumps laterally surrounding the semiconductor chip on the substrate; a graphene layer on the semiconductor chip; and a molding layer between the substrate and the graphene layer, wherein the graphene layer is electrically connected to the conductive bumps.
The semiconductor package of claim 13, further comprising a coating layer covering the graphene layer.
The semiconductor package of claim 13, further comprising a side graphene layer covering a sidewall of the molding layer.
A semiconductor package comprising: a substrate; a semiconductor chip on the substrate and electrically connected to the substrate; a molding layer on the substrate and at a side of the semiconductor chip; a graphene layer directly on the semiconductor chip and on the molding layer opposite the substrate; and conductive bumps on the substrate and through the molding layer, the conductive bumps in contact with the substrate and the graphene layer to electrically connect the substrate and the graphene layer, the molding layer positioned between the conductive bumps and the semiconductor chip. -6- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059
The semiconductor package of claim 16, wherein the graphene layer is further at sidewalls of the molding layer.
The semiconductor package of claim 16, wherein the conductive bumps comprise ground signal bumps.
The semiconductor package of claim 16, further comprising conductive signal bumps on the substrate and th r ough the molding layer, the conductive bumps in contact with the substrate and isolated from the graphene layer.
The semiconductor package of claim 16, further comprising a coating layer on the graphene layer. -7-
Layer stacks claimed or described, ordered top of device to substrate.
stacked semiconductor package (lower + upper package)
Materials described outside the worked examples.
graphene layer (lower)
graphene layer (upper)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12, a connection member 232 may be formed in the first opening 261, so that the ground solder 231m may be electrically connected to the lower graphene …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,070,677Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concepts; [0028]
FIG. 2 is a cross-sectional view illustrating a semiconductor device according to other embodiments of the inventive concepts; 10 [0029]
FIG. 3 is a plan view illustrating a semiconductor package according to some embodiments of the inventive concepts; [0030]
FIG. 4 is a cross-sectional view taken along a line A-B of
FIG. 5 is a plan view illustrating a semiconductor package according to other embodiments of the inventive concepts; 15 [0032]
FIG. 6 is a cross-sectional view taken along a line A-B of
FIG. 7 is a plan view illustrating a semiconductor package according to other embodiments of the inventive concepts; [0034]
FIG. 8 is a cross-sectional view taken along a line A-B of
FIG. 9 is a plan view illustrating a semiconductor package according to other 20 embodiments of the inventive concepts; [0036]
FIG. 10 is a cross-sectional view taken along a line A-B of
FIGS. 11 and 12 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to embodiments of the inventive concepts; …
FIG. 12, a connection member 232 may be formed in the first opening 261, so that the ground solder 231m may be electrically connected to the lower graphene …
FIG. 13 is a schematic block diagram illustrating an example of electronic systems including semiconductor packages according to embodiments of the inventive …
FIG. 14 is a schematic block diagram illustrating an example of memory systems including semiconductor packages according to embodiments of the inventive …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A semiconductor package comprising: a lower package comprising a lower substrate, a lower semiconductor chip on the lower substrate, a lower graphene layer on the lower semiconductor chip, and a lower molding layer between the lower substrate and the lower graphene layer; an upper package on the lower substrate, the upper package spaced apart from the lower package, the upper package comprising an upper substrate, an upper semiconductor chip, and an upper molding layer; and lower conductive bumps between the lower substrate and the upper substrate, the lower conductive bumps comprising a g round bump and a signal transmitting bump.
The semiconductor package of claim 1, further comprising a first opening and a second opening in the lower molding layer and the lower graphene layer; wherein the first opening exposes an upper portion of the ground bump; and wherein the second opening exposes an upper portion of the signal transmitting bump. -3- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059
The semiconductor package of claim 1, further comprising an upper graphene layer on the upper semiconductor chip.
The semiconductor package of claim 1, wherein the lower package further comprises a lower coating layer on the lower graphene layer.
The semiconductor package of claim 1, wherein the lower package further comprises: a lower side graphene layer and a lower side coating layer on the lower side graphene layer; wherein the lower molding layer includes a t op surface, a bottom surface opposite the top surface, and a sidewall between an edge of the top surface and an edge of the bottom surface; and wherein the lower side graphene layer is on the sidewall of the lower molding layer.
The semiconductor package of claim 1, further comprising an air gap between the lower graphene layer and the upper substrate.
The semiconductor package of claim 1, wherein the lower graphene layer is in direct contact with the lower semiconductor chip.
A semiconductor package comprising: a substrate; -5- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059 a semiconductor chip on the substrate; conductive bumps laterally surrounding the semiconductor chip on the substrate; a graphene layer on the semiconductor chip; and a molding layer between the substrate and the graphene layer, wherein the graphene layer is electrically connected to the conductive bumps.
The semiconductor package of claim 13, further comprising a coating layer covering the graphene layer.
The semiconductor package of claim 13, further comprising a side graphene layer covering a sidewall of the molding layer.
A semiconductor package comprising: a substrate; a semiconductor chip on the substrate and electrically connected to the substrate; a molding layer on the substrate and at a side of the semiconductor chip; a graphene layer directly on the semiconductor chip and on the molding layer opposite the substrate; and conductive bumps on the substrate and through the molding layer, the conductive bumps in contact with the substrate and the graphene layer to electrically connect the substrate and the graphene layer, the molding layer positioned between the conductive bumps and the semiconductor chip. -6- Applicant(s): Soojeoung Park U.S. Serial No.: 14/171,059
The semiconductor package of claim 16, wherein the graphene layer is further at sidewalls of the molding layer.
The semiconductor package of claim 16, wherein the conductive bumps comprise ground signal bumps.
The semiconductor package of claim 16, further comprising conductive signal bumps on the substrate and th r ough the molding layer, the conductive bumps in contact with the substrate and isolated from the graphene layer.
The semiconductor package of claim 16, further comprising a coating layer on the graphene layer. -7-
Layer stacks claimed or described, ordered top of device to substrate.
stacked semiconductor package (lower + upper package)
Materials described outside the worked examples.
graphene layer (lower)
graphene layer (upper)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12, a connection member 232 may be formed in the first opening 261, so that the ground solder 231m may be electrically connected to the lower graphene …
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