Patent
US 11,476,272THREE-DIMENSIONAL MEMORY DEVICE WITH A GRAPHENE CHANNEL AND METHODS OF MAKING THE SAME
Peter Rabkin
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,476,272Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, an exemplary structure according to an embodiment of the present disclosure is illustrated, which may be used, for example, to fabricate a device …
FIG. 2 is a schematic vertical cross-sectional view of the exemplary structure after formation of an alternating stack of insulating layers and sacrificial …
FIG. 3 is a schematic vertical cross-sectional view of the exemplary structure after formation of stepped terraces and a retro-stepped dielectric material …
FIG. 4A. The vertical plane A-A' is the plane of the cross-section for
FIG. 5 L illustrates an exemplary temperature cycle profile during the graphene formation process. In an illustrative example, the initial temperature T O may …
FIG. 6, the exemplary structure is illustrated after formation of memory opening fill structures 58 and support pillar structure 20 within the memory openings …
FIG. 7A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
FIG. 8. Backside recesses 43 are formed in volumes from which the sacrificial material layers 42 are removed. The removal of the second material of the …
FIG. 9C, a metallic barrier layer 46A may be deposited in the backside recesses 43. The metallic barrier layer 46A includes an electrically conductive metallic …
FIG. 10 is a schematic vertical cross-sectional view of the exemplary structure at the processing step of
FIG. 11 A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
FIG. 12A is a schematic vertical cross-sectional view of the exemplary structure after formation of an insulating spacer and a backside contact structure …
FIG. 13A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A three-dimensional memory device comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate; and a memory stack structure extending through the alternating stack and comprising a memory film and a vertical semiconductor channel, wherein the vertical semiconductor channel contacts an inner sidewall of the memory film and comprises at least one graphene layer; [[and]] a metallic drain region having a cylindrical sidewall that contacts an upper end of an inner cylindrical sidewall of the at least one graphene layer and comprising a metallic material selected from Ni, Ti, Au, Pd, Cr, Pd, alloys thereof, or metal silicides thereof, and a dielectric liner in direct contact with an inner sidewall of the at least one graphene la yer and comprising a material selected from a dielectric metal oxide material or silicon ox y nitride, wherein the dielectric liner is configured to increase mobility of charge carriers in the at least one graphene la y er by passivating surface states of the at least one graphene la y er. Currently amended
The three-dimensional memory device of Claim 1, wherein each of the at least one graphene layer includes a hexagonal lattice within a vertical plane that is parallel to an inner surface of the memory film. Original
The three-dimensional memory device of Claim 1, further comprising a dielectric core laterally surrounded by the at least one graphene layer. Original
The three-dimensional memory device of Claim 1, wherein the at least one graphene layer is doped with a dopant selected from B, N, Na or K. Original
The three-dimensional memory device of Claim 1, wherein a bottom end of the at least one graphene layer is in contact with a doped semiconductor material. Previously presented
The three-dimensional memory device of Claim 1, wherein: the memory film comprises a layer stack including a charge storage layer and a tunneling dielectric layer; and the at least one graphene layer is in direct contact with the tunneling dielectric layer. Original
The three-dimensional memory device of Claim 1, wherein: the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than an overlying electrically conductive layer within the alternating stack; the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces. Original
The three-dimensional memory device of Claim 1, wherein an interface between the metallic drain region and the at least one graphene layer comprises a cylindrical vertical interface between carbon atoms of the at least one graphene layer and a metallic element of the metallic material of the metallic drain region. Previously presented
The three-dimensional memory device of Claim 1, wherein a top surface of the metallic drain region is located within a same first horizontal plane as a top surface of the at least one graphene layer. Previously presented
The three-dimensional memory device of Claim 1, wherein the substrate comprises: a semiconductor material layer having a doping of a first conductivity type; and a source region having a doping of a second conductivity type that is an opposite of the first conductivity type. Previously presented
Canceled
14-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
three-dimensional memory device with graphene channel
Materials described outside the worked examples.
graphene layer (vertical semiconductor channel)
metallic drain region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, an exemplary structure according to an embodiment of the present disclosure is illustrated, which may be used, for example, to fabricate a device …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–50 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,476,272Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, an exemplary structure according to an embodiment of the present disclosure is illustrated, which may be used, for example, to fabricate a device …
FIG. 2 is a schematic vertical cross-sectional view of the exemplary structure after formation of an alternating stack of insulating layers and sacrificial …
FIG. 3 is a schematic vertical cross-sectional view of the exemplary structure after formation of stepped terraces and a retro-stepped dielectric material …
FIG. 4A. The vertical plane A-A' is the plane of the cross-section for
FIG. 5 L illustrates an exemplary temperature cycle profile during the graphene formation process. In an illustrative example, the initial temperature T O may …
FIG. 6, the exemplary structure is illustrated after formation of memory opening fill structures 58 and support pillar structure 20 within the memory openings …
FIG. 7A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
FIG. 8. Backside recesses 43 are formed in volumes from which the sacrificial material layers 42 are removed. The removal of the second material of the …
FIG. 9C, a metallic barrier layer 46A may be deposited in the backside recesses 43. The metallic barrier layer 46A includes an electrically conductive metallic …
FIG. 10 is a schematic vertical cross-sectional view of the exemplary structure at the processing step of
FIG. 11 A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
FIG. 12A is a schematic vertical cross-sectional view of the exemplary structure after formation of an insulating spacer and a backside contact structure …
FIG. 13A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A three-dimensional memory device comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate; and a memory stack structure extending through the alternating stack and comprising a memory film and a vertical semiconductor channel, wherein the vertical semiconductor channel contacts an inner sidewall of the memory film and comprises at least one graphene layer; [[and]] a metallic drain region having a cylindrical sidewall that contacts an upper end of an inner cylindrical sidewall of the at least one graphene layer and comprising a metallic material selected from Ni, Ti, Au, Pd, Cr, Pd, alloys thereof, or metal silicides thereof, and a dielectric liner in direct contact with an inner sidewall of the at least one graphene la yer and comprising a material selected from a dielectric metal oxide material or silicon ox y nitride, wherein the dielectric liner is configured to increase mobility of charge carriers in the at least one graphene la y er by passivating surface states of the at least one graphene la y er. Currently amended
The three-dimensional memory device of Claim 1, wherein each of the at least one graphene layer includes a hexagonal lattice within a vertical plane that is parallel to an inner surface of the memory film. Original
The three-dimensional memory device of Claim 1, further comprising a dielectric core laterally surrounded by the at least one graphene layer. Original
The three-dimensional memory device of Claim 1, wherein the at least one graphene layer is doped with a dopant selected from B, N, Na or K. Original
The three-dimensional memory device of Claim 1, wherein a bottom end of the at least one graphene layer is in contact with a doped semiconductor material. Previously presented
The three-dimensional memory device of Claim 1, wherein: the memory film comprises a layer stack including a charge storage layer and a tunneling dielectric layer; and the at least one graphene layer is in direct contact with the tunneling dielectric layer. Original
The three-dimensional memory device of Claim 1, wherein: the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than an overlying electrically conductive layer within the alternating stack; the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces. Original
The three-dimensional memory device of Claim 1, wherein an interface between the metallic drain region and the at least one graphene layer comprises a cylindrical vertical interface between carbon atoms of the at least one graphene layer and a metallic element of the metallic material of the metallic drain region. Previously presented
The three-dimensional memory device of Claim 1, wherein a top surface of the metallic drain region is located within a same first horizontal plane as a top surface of the at least one graphene layer. Previously presented
The three-dimensional memory device of Claim 1, wherein the substrate comprises: a semiconductor material layer having a doping of a first conductivity type; and a source region having a doping of a second conductivity type that is an opposite of the first conductivity type. Previously presented
Canceled
14-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
three-dimensional memory device with graphene channel
Materials described outside the worked examples.
graphene layer (vertical semiconductor channel)
metallic drain region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, an exemplary structure according to an embodiment of the present disclosure is illustrated, which may be used, for example, to fabricate a device …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–50 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,476,272Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, an exemplary structure according to an embodiment of the present disclosure is illustrated, which may be used, for example, to fabricate a device …
FIG. 2 is a schematic vertical cross-sectional view of the exemplary structure after formation of an alternating stack of insulating layers and sacrificial …
FIG. 3 is a schematic vertical cross-sectional view of the exemplary structure after formation of stepped terraces and a retro-stepped dielectric material …
FIG. 4A. The vertical plane A-A' is the plane of the cross-section for
FIG. 5 L illustrates an exemplary temperature cycle profile during the graphene formation process. In an illustrative example, the initial temperature T O may …
FIG. 6, the exemplary structure is illustrated after formation of memory opening fill structures 58 and support pillar structure 20 within the memory openings …
FIG. 7A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
FIG. 8. Backside recesses 43 are formed in volumes from which the sacrificial material layers 42 are removed. The removal of the second material of the …
FIG. 9C, a metallic barrier layer 46A may be deposited in the backside recesses 43. The metallic barrier layer 46A includes an electrically conductive metallic …
FIG. 10 is a schematic vertical cross-sectional view of the exemplary structure at the processing step of
FIG. 11 A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
FIG. 12A is a schematic vertical cross-sectional view of the exemplary structure after formation of an insulating spacer and a backside contact structure …
FIG. 13A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A three-dimensional memory device comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate; and a memory stack structure extending through the alternating stack and comprising a memory film and a vertical semiconductor channel, wherein the vertical semiconductor channel contacts an inner sidewall of the memory film and comprises at least one graphene layer; [[and]] a metallic drain region having a cylindrical sidewall that contacts an upper end of an inner cylindrical sidewall of the at least one graphene layer and comprising a metallic material selected from Ni, Ti, Au, Pd, Cr, Pd, alloys thereof, or metal silicides thereof, and a dielectric liner in direct contact with an inner sidewall of the at least one graphene la yer and comprising a material selected from a dielectric metal oxide material or silicon ox y nitride, wherein the dielectric liner is configured to increase mobility of charge carriers in the at least one graphene la y er by passivating surface states of the at least one graphene la y er. Currently amended
The three-dimensional memory device of Claim 1, wherein each of the at least one graphene layer includes a hexagonal lattice within a vertical plane that is parallel to an inner surface of the memory film. Original
The three-dimensional memory device of Claim 1, further comprising a dielectric core laterally surrounded by the at least one graphene layer. Original
The three-dimensional memory device of Claim 1, wherein the at least one graphene layer is doped with a dopant selected from B, N, Na or K. Original
The three-dimensional memory device of Claim 1, wherein a bottom end of the at least one graphene layer is in contact with a doped semiconductor material. Previously presented
The three-dimensional memory device of Claim 1, wherein: the memory film comprises a layer stack including a charge storage layer and a tunneling dielectric layer; and the at least one graphene layer is in direct contact with the tunneling dielectric layer. Original
The three-dimensional memory device of Claim 1, wherein: the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than an overlying electrically conductive layer within the alternating stack; the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces. Original
The three-dimensional memory device of Claim 1, wherein an interface between the metallic drain region and the at least one graphene layer comprises a cylindrical vertical interface between carbon atoms of the at least one graphene layer and a metallic element of the metallic material of the metallic drain region. Previously presented
The three-dimensional memory device of Claim 1, wherein a top surface of the metallic drain region is located within a same first horizontal plane as a top surface of the at least one graphene layer. Previously presented
The three-dimensional memory device of Claim 1, wherein the substrate comprises: a semiconductor material layer having a doping of a first conductivity type; and a source region having a doping of a second conductivity type that is an opposite of the first conductivity type. Previously presented
Canceled
14-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
three-dimensional memory device with graphene channel
Materials described outside the worked examples.
graphene layer (vertical semiconductor channel)
metallic drain region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, an exemplary structure according to an embodiment of the present disclosure is illustrated, which may be used, for example, to fabricate a device …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–50 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,476,272Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, an exemplary structure according to an embodiment of the present disclosure is illustrated, which may be used, for example, to fabricate a device …
FIG. 2 is a schematic vertical cross-sectional view of the exemplary structure after formation of an alternating stack of insulating layers and sacrificial …
FIG. 3 is a schematic vertical cross-sectional view of the exemplary structure after formation of stepped terraces and a retro-stepped dielectric material …
FIG. 4A. The vertical plane A-A' is the plane of the cross-section for
FIG. 5 L illustrates an exemplary temperature cycle profile during the graphene formation process. In an illustrative example, the initial temperature T O may …
FIG. 6, the exemplary structure is illustrated after formation of memory opening fill structures 58 and support pillar structure 20 within the memory openings …
FIG. 7A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
FIG. 8. Backside recesses 43 are formed in volumes from which the sacrificial material layers 42 are removed. The removal of the second material of the …
FIG. 9C, a metallic barrier layer 46A may be deposited in the backside recesses 43. The metallic barrier layer 46A includes an electrically conductive metallic …
FIG. 10 is a schematic vertical cross-sectional view of the exemplary structure at the processing step of
FIG. 11 A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
FIG. 12A is a schematic vertical cross-sectional view of the exemplary structure after formation of an insulating spacer and a backside contact structure …
FIG. 13A. The vertical plane A-A' is the plane of the schematic vertical cross-sectional view of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A three-dimensional memory device comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate; and a memory stack structure extending through the alternating stack and comprising a memory film and a vertical semiconductor channel, wherein the vertical semiconductor channel contacts an inner sidewall of the memory film and comprises at least one graphene layer; [[and]] a metallic drain region having a cylindrical sidewall that contacts an upper end of an inner cylindrical sidewall of the at least one graphene layer and comprising a metallic material selected from Ni, Ti, Au, Pd, Cr, Pd, alloys thereof, or metal silicides thereof, and a dielectric liner in direct contact with an inner sidewall of the at least one graphene la yer and comprising a material selected from a dielectric metal oxide material or silicon ox y nitride, wherein the dielectric liner is configured to increase mobility of charge carriers in the at least one graphene la y er by passivating surface states of the at least one graphene la y er. Currently amended
The three-dimensional memory device of Claim 1, wherein each of the at least one graphene layer includes a hexagonal lattice within a vertical plane that is parallel to an inner surface of the memory film. Original
The three-dimensional memory device of Claim 1, further comprising a dielectric core laterally surrounded by the at least one graphene layer. Original
The three-dimensional memory device of Claim 1, wherein the at least one graphene layer is doped with a dopant selected from B, N, Na or K. Original
The three-dimensional memory device of Claim 1, wherein a bottom end of the at least one graphene layer is in contact with a doped semiconductor material. Previously presented
The three-dimensional memory device of Claim 1, wherein: the memory film comprises a layer stack including a charge storage layer and a tunneling dielectric layer; and the at least one graphene layer is in direct contact with the tunneling dielectric layer. Original
The three-dimensional memory device of Claim 1, wherein: the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than an overlying electrically conductive layer within the alternating stack; the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces. Original
The three-dimensional memory device of Claim 1, wherein an interface between the metallic drain region and the at least one graphene layer comprises a cylindrical vertical interface between carbon atoms of the at least one graphene layer and a metallic element of the metallic material of the metallic drain region. Previously presented
The three-dimensional memory device of Claim 1, wherein a top surface of the metallic drain region is located within a same first horizontal plane as a top surface of the at least one graphene layer. Previously presented
The three-dimensional memory device of Claim 1, wherein the substrate comprises: a semiconductor material layer having a doping of a first conductivity type; and a source region having a doping of a second conductivity type that is an opposite of the first conductivity type. Previously presented
Canceled
14-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
three-dimensional memory device with graphene channel
Materials described outside the worked examples.
graphene layer (vertical semiconductor channel)
metallic drain region
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, an exemplary structure according to an embodiment of the present disclosure is illustrated, which may be used, for example, to fabricate a device …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–50 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
dielectric liner
dielectric core
memory film
sacrificial polycrystalline metal layer
carbon precursor (adsorbed carbon atoms)
FIG. 9C, a metallic barrier layer 46A may be deposited in the backside recesses 43. The metallic barrier layer 46A includes an electrically conductive metallic …
| 1–50 nm |
| — |
Thickness | 0–30 nm | — |
Thickness | 1–20 nm | — |
Thickness | 2–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1.5–10 nm | — |
Thickness | 2–5 nm | — |
Thickness | 3–10 nm | — |
Duration | 1–20 minutes | — |
— | 0.7–1.4 eV | — |
Thickness | 50–500 nm | — |
Thickness | 1–15 nm | — |
Thickness | 2–8 nm | — |
Thickness | 3–6 nm | — |
Thickness | 1.5–60 nm | — |
Thickness | 3–30 nm | — |
Thickness | 2–6 nm | — |
— | ≥ 0.7 eV | — |
dielectric liner
dielectric core
memory film
sacrificial polycrystalline metal layer
carbon precursor (adsorbed carbon atoms)
FIG. 9C, a metallic barrier layer 46A may be deposited in the backside recesses 43. The metallic barrier layer 46A includes an electrically conductive metallic …
| 1–50 nm |
| — |
Thickness | 0–30 nm | — |
Thickness | 1–20 nm | — |
Thickness | 2–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1.5–10 nm | — |
Thickness | 2–5 nm | — |
Thickness | 3–10 nm | — |
Duration | 1–20 minutes | — |
— | 0.7–1.4 eV | — |
Thickness | 50–500 nm | — |
Thickness | 1–15 nm | — |
Thickness | 2–8 nm | — |
Thickness | 3–6 nm | — |
Thickness | 1.5–60 nm | — |
Thickness | 3–30 nm | — |
Thickness | 2–6 nm | — |
— | ≥ 0.7 eV | — |
dielectric liner
dielectric core
memory film
sacrificial polycrystalline metal layer
carbon precursor (adsorbed carbon atoms)
FIG. 9C, a metallic barrier layer 46A may be deposited in the backside recesses 43. The metallic barrier layer 46A includes an electrically conductive metallic …
| 1–50 nm |
| — |
Thickness | 0–30 nm | — |
Thickness | 1–20 nm | — |
Thickness | 2–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1.5–10 nm | — |
Thickness | 2–5 nm | — |
Thickness | 3–10 nm | — |
Duration | 1–20 minutes | — |
— | 0.7–1.4 eV | — |
Thickness | 50–500 nm | — |
Thickness | 1–15 nm | — |
Thickness | 2–8 nm | — |
Thickness | 3–6 nm | — |
Thickness | 1.5–60 nm | — |
Thickness | 3–30 nm | — |
Thickness | 2–6 nm | — |
— | ≥ 0.7 eV | — |
dielectric liner
dielectric core
memory film
sacrificial polycrystalline metal layer
carbon precursor (adsorbed carbon atoms)
FIG. 9C, a metallic barrier layer 46A may be deposited in the backside recesses 43. The metallic barrier layer 46A includes an electrically conductive metallic …
| 1–50 nm |
| — |
Thickness | 0–30 nm | — |
Thickness | 1–20 nm | — |
Thickness | 2–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1.5–10 nm | — |
Thickness | 2–5 nm | — |
Thickness | 3–10 nm | — |
Duration | 1–20 minutes | — |
— | 0.7–1.4 eV | — |
Thickness | 50–500 nm | — |
Thickness | 1–15 nm | — |
Thickness | 2–8 nm | — |
Thickness | 3–6 nm | — |
Thickness | 1.5–60 nm | — |
Thickness | 3–30 nm | — |
Thickness | 2–6 nm | — |
— | ≥ 0.7 eV | — |