DEADTIME OPTIMIZATION FOR GaN HALF-BRIDGE AND FULL-BRIDGE SWITCH TOPOLOGIES

Yajie QIU

Patent

Atlas literature

Patent

US 11,545,889

DEADTIME OPTIMIZATION FOR GaN HALF-BRIDGE AND FULL-BRIDGE SWITCH TOPOLOGIES

Yajie QIU

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 2

FIG. 3

FIG. 4

FIG. 5

FIG. 6

FIG. 7

FIG. 8

FIG. 9

FIG. 10

FIG. 11

FIG. 12

FIG. 13

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

4 independent · 5 dependent

1
IndependentGaNGaN half-bridge or full-bridge switch topology with deadtime optimization method
A method of controlling deadtime for a half-bridge or full-bridge switch topology comprising a driver, wherein high side and low side switches comprise GaN transistors, comprising: receiving a ﬁrst input comprising a low-side drain current signal I D; receiving a second input indicative of a bulk voltage V ad; generating a current diﬀerence signal ID-I LOAD, where I LOAD is a l o ad current; integrating the current diﬀerence signal I D-I LOAD o ver a time inter v al of t 2-ti during voltage commutation to generate a current charge output SVG 17536542.11-29-2021.KWL₃₁VXNLDFLYX7.CLM.1.svg 0.65 2.29 Black and white based on the voltage V ac obtaining a reference current charge C oss for the high side switch SVG 17536542.11-29-2021.KWL₃₁VXNLDFLYX7.CLM.2.svg 0.57 4.36 Black and white comparing the current charge output and the reference current charge C oss, and generating a deadtime adjust output signal; outputting the deadtime adjust signal to the driver.
1. 2
  Dependent← claim 1GaNGaN half-bridge or full-bridge switch topology with deadtime optimization method
  The method of claim 1, wherein, the deadtime adjust signal is used to reduce or optimize deadtime to reduce deadtime losses, while avoiding cross-conduction.
3
IndependentGaNDeadtime optimization circuit for GaN half-bridge or full-bridge
A circuit for controlling deadtime for a half-bridge or full-bridge switch topology comprising a driver, wherein high-side and low-side switches comprise GaN transistors, the circuit comprising a drain current bump ﬁlter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge C oss and generating a deadtime adjust signal.
4
IndependentGaNDeadtime optimization circuit for GaN half-bridge or full-bridge
A circuit for controlling deadtime for a half-bridge or full-bridge switch topology wherein high-side and low-side switches comprise GaN transistors, comprising: an input for receiving a low-side drain current I D; an input for sensing a bulk voltage V ac; a unit for generating a current diﬀerence signal I D-I LOAD, where I LOAD is a l o ad current; a timer for recording and counting the deadtime; an integrator for integrating the current diﬀerence signal I D-I LOAD o ver a time inter v al of t 2-ti during voltage commutation to generate a current charge output SVG 17536542.11-29-2021.KWL₃₁VXNLDFLYX7.CLM.3.svg 0.55 1.9 Black and white a reference source for obtaining a reference current charge C oss based on V ac; deadtime adjustment circuitry for receiving the current charge output from the integrator, comparing the current charge output with the reference current charge C oss, and generating a deadtime adjust signal; an output for outputting the deadtime adjust signal to the driver.
1. 5
  Dependent← claim 4GaNDeadtime optimization circuit for GaN half-bridge or full-bridge
  The circuit of claim 4, wherein the unit for generating a current diﬀerence signal I D-I LOAD is a DC blocking unit or a subtractor.
2. 6
  Dependent← claim 4GaNDeadtime optimization circuit for GaN half-bridge or full-bridge
  The circuit of claim 4, wherein the integrator is an analog integrator or a digital integrator.
3. 7
  Dependent← claim 4GaNDeadtime optimization circuit for GaN half-bridge or full-bridge
  The circuit of claim 4 wherein, based on the sensed bulk voltage V ac, the reference source provides any one of: real-time calculation of the reference current charge C oss; real-time adjustment of a stored reference current charge Coss; an oﬄine look-up from a table of reference current charge values.
4. 8
  Dependent← claim 4GaNDeadtime optimization circuit for GaN half-bridge or full-bridge
  The circuit of claim 4, wherein: the unit for generating a current diﬀerence signal I D-I LOAD is a DC blocking unit or a subtractor; the integrator is an analog integrator or a digital integrator; and based on the sensed bulk voltage V a c the reference source provides any one of real-time calculation of the reference current charge C oss; real-time adjustment of a stored reference current charge C oss; and an oﬄine look-up from a table of reference current charge values.
9
IndependentGaNGaN half-bridge or full-bridge power switching system with deadtime optimization
A power switching system comprising a G aN half-bridge or a G aN full-bridge and a deadtime optimization system comprising a drain current bump ﬁlter for generating a current charge output during voltage commutation; and circuit elements for comparing the current charge output to a reference current charge C oss, and generating a deadtime adjust signal.

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

GaN half-bridge or full-bridge switch topology with deadtime optimization method

GaNlow-side switch

GaNhigh-side switch

Deadtime optimization circuit for GaN half-bridge or full-bridge

GaNlow-side GaN transistor switch

GaNhigh-side GaN transistor switch

GaN half-bridge or full-bridge power switching system with deadtime optimization

Materials

Materials described outside the worked examples.

GaN (Gallium Nitride)

GaN

Switch Transistor Channel Material

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