Patent
Atlas literature
Patent
US 11,682,983 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B show an example three-port multilevel power converter/inverter, according to an example; B₂
FIG. 2 illustrates normalized inductor current ripple val- ues for two and four level FCML paths as a function of the duty cycle, according to an example;
FIG. 3 illustrates the DC-to-DC path gate timing diagram, according to an example;
FIG. 4 illustrates a generalized block diagram of the multiport multilevel converter, according to an example; and
FIG. 5 illustrates a generalized schematic of the multiport multilevel converter, according to an example.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A multiport multilevel converter/inverter, comprising: a connection point comprising a two-line connection; a capacitor electrically coupled across the two-line con-nection of the connection point, the capacitor compris-ing a positive terminal and a negative terminal; a first flying capacitor multilevel path comprising: a first external two connection port configured to con-nect outside of the multiport multilevel converter/inverter; a first flying capacitor multilevel converter circuit path comprising a first plurality of capacitors selectively interconnected to one another by a first plurality of GaN transistors to operate as a first multilevel flying capacitor voltage converter; and a first interface comprising a first interface transistor and a second interface transistor conveying DC power and that is electrically coupled to the connec-tion point; a second flying capacitor multilevel path comprising: a second external two connection port configured to connect outside of the multiport multilevel con-verter/inverter; 20 a second flying capacitor multilevel converter circuit path comprising a second plurality of capacitors selectively interconnected to one another by a second plurality of GaN transistors to operate as a second multilevel flying capacitor voltage converter; and 25 a second interface comprising a third interface transis-tor and a fourth interface transistor conveying DC power and that is electrically coupled to the connec-tion point, a first connection point conductor ohmically connect-ing, through the connection point, the first interface transistor, the positive terminal of the capacitor, and the third interface transistor; and a second connection point conductor ohmically con-necting, through the connection point, the second interface transistor, the negative terminal of the capacitor, and the fourth interface transistor.
The multiport multilevel converter/inverter of claim 1, further comprising a DC electrical port coupled to the connection point.
The multiport multilevel converter/inverter of claim 1, further comprising: a third flying capacitor multilevel path comprising: a third flying capacitor multilevel converter circuit path comprising a third plurality of capacitors selectively interconnected to one another by a third plurality of GaN transistors to operate as a third multilevel flying capacitor voltage converter; and a third external two connection port configured to connect outside of the multiport multilevel con-verter/inverter; and a third interface comprising a fifth interface transistor and a sixth interface transistor conveying DC power and that is electrically coupled to the connection point, wherein the first connection point conductor ohmically con-nects, through the connection point, the first interface transistor, the positive terminal of the capacitor, the third interface transistor, and the fifth interface tran-sistor; and the second connection point conductor ohmically con-nects, through the connection point, the second interface transistor, the negative terminal of the capacitor, the fourth interface transistor, and the sixth interface transistor.
The multiport multilevel converter/inverter of claim 1, where the first flying capacitor multilevel path comprises an B₂ unfolder to convert the voltage waveform produced within the first flying capacitor multilevel path to an AC power at the first external two connection port.
The multiport multilevel converter/inverter of claim 1, where the first flying capacitor multilevel path performs bidirectional DC-to-AC or AC-to-DC power conversion between the first external two connection port and the first interface.
The multiport multilevel converter/inverter of claim 1, where the second flying capacitor multilevel path performs bidirectional DC-to-DC power conversion between the sec-ond external two connection port and the second interface.
The multiport multilevel converter/inverter of claim 1, wherein any of the first external two connection port or the second external two connection port are configurable to convey DC or AC power.
The multiport multilevel converter/inverter of claim 1, wherein the first flying capacitor multilevel path and the second flying capacitor multilevel path each comprises a respective four level flying capacitor multilevel voltage converter circuit.
The multiport multilevel converter/inverter of claim 1, wherein the first plurality of GaN transistors are controlled by a phase shifted pulse width modulated signals operating to balance voltages across the plurality of flying capacitors.
An N-port multilevel converter/inverter comprising: any N number of external two connection ports; (N−1) number of paths where the paths are individually able to deploy FCML with any respective m number of levels odd or even, where all paths have bidirectional capabilities, where each path in the N−1 number of paths is coupled to a connection point comprising a capacitor with a posi-tive terminal and a negative terminal, where each path comprises: an external two connection port configured to connect outside of the N-port multiport multilevel converter/inverter; a flying capacitor multilevel converter circuit path comprising a plurality of capacitors selectively interconnected to one another by a plurality of transistors to operate as a multilevel flying capacitor voltage converter; and an interface comprising a respective first interface transistor and a respective second interface transistor conveying DC power and that is electrically coupled to the connection point, and where first connection point further comprises: a first connection point conductor ohmically con-necting the respective first interface transistor of each path to the positive terminal of the capacitor; and a second connection point conductor ohmically con-necting the respective second interface transistor of each path to the negative terminal of the capaci-tor, and where the N-port multilevel converter/inverter is able to dispatch power from any external two connection port to any other external two connection port through the connection point, so as to perform conversion of any of DC-to-DC, DC-to-AC, AC-to-AC and AC-to-DC. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
multiport multilevel converter/inverter (two-path)
N-port multilevel converter/inverter
Materials described outside the worked examples.
GaN transistor
GaN
EPC₂₀₃₄C GaN switch
STL₅₇N₆₅M₅ MOSFET
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
DC-to-AC path efficiency (prototype) | 98.2 % | — |
AC voltage THD (prototype DC-to-AC path) |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Patent
Atlas literature
Patent
US 11,682,983 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B show an example three-port multilevel power converter/inverter, according to an example; B₂
FIG. 2 illustrates normalized inductor current ripple val- ues for two and four level FCML paths as a function of the duty cycle, according to an example;
FIG. 3 illustrates the DC-to-DC path gate timing diagram, according to an example;
FIG. 4 illustrates a generalized block diagram of the multiport multilevel converter, according to an example; and
FIG. 5 illustrates a generalized schematic of the multiport multilevel converter, according to an example.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A multiport multilevel converter/inverter, comprising: a connection point comprising a two-line connection; a capacitor electrically coupled across the two-line con-nection of the connection point, the capacitor compris-ing a positive terminal and a negative terminal; a first flying capacitor multilevel path comprising: a first external two connection port configured to con-nect outside of the multiport multilevel converter/inverter; a first flying capacitor multilevel converter circuit path comprising a first plurality of capacitors selectively interconnected to one another by a first plurality of GaN transistors to operate as a first multilevel flying capacitor voltage converter; and a first interface comprising a first interface transistor and a second interface transistor conveying DC power and that is electrically coupled to the connec-tion point; a second flying capacitor multilevel path comprising: a second external two connection port configured to connect outside of the multiport multilevel con-verter/inverter; 20 a second flying capacitor multilevel converter circuit path comprising a second plurality of capacitors selectively interconnected to one another by a second plurality of GaN transistors to operate as a second multilevel flying capacitor voltage converter; and 25 a second interface comprising a third interface transis-tor and a fourth interface transistor conveying DC power and that is electrically coupled to the connec-tion point, a first connection point conductor ohmically connect-ing, through the connection point, the first interface transistor, the positive terminal of the capacitor, and the third interface transistor; and a second connection point conductor ohmically con-necting, through the connection point, the second interface transistor, the negative terminal of the capacitor, and the fourth interface transistor.
The multiport multilevel converter/inverter of claim 1, further comprising a DC electrical port coupled to the connection point.
The multiport multilevel converter/inverter of claim 1, further comprising: a third flying capacitor multilevel path comprising: a third flying capacitor multilevel converter circuit path comprising a third plurality of capacitors selectively interconnected to one another by a third plurality of GaN transistors to operate as a third multilevel flying capacitor voltage converter; and a third external two connection port configured to connect outside of the multiport multilevel con-verter/inverter; and a third interface comprising a fifth interface transistor and a sixth interface transistor conveying DC power and that is electrically coupled to the connection point, wherein the first connection point conductor ohmically con-nects, through the connection point, the first interface transistor, the positive terminal of the capacitor, the third interface transistor, and the fifth interface tran-sistor; and the second connection point conductor ohmically con-nects, through the connection point, the second interface transistor, the negative terminal of the capacitor, the fourth interface transistor, and the sixth interface transistor.
The multiport multilevel converter/inverter of claim 1, where the first flying capacitor multilevel path comprises an B₂ unfolder to convert the voltage waveform produced within the first flying capacitor multilevel path to an AC power at the first external two connection port.
The multiport multilevel converter/inverter of claim 1, where the first flying capacitor multilevel path performs bidirectional DC-to-AC or AC-to-DC power conversion between the first external two connection port and the first interface.
The multiport multilevel converter/inverter of claim 1, where the second flying capacitor multilevel path performs bidirectional DC-to-DC power conversion between the sec-ond external two connection port and the second interface.
The multiport multilevel converter/inverter of claim 1, wherein any of the first external two connection port or the second external two connection port are configurable to convey DC or AC power.
The multiport multilevel converter/inverter of claim 1, wherein the first flying capacitor multilevel path and the second flying capacitor multilevel path each comprises a respective four level flying capacitor multilevel voltage converter circuit.
The multiport multilevel converter/inverter of claim 1, wherein the first plurality of GaN transistors are controlled by a phase shifted pulse width modulated signals operating to balance voltages across the plurality of flying capacitors.
An N-port multilevel converter/inverter comprising: any N number of external two connection ports; (N−1) number of paths where the paths are individually able to deploy FCML with any respective m number of levels odd or even, where all paths have bidirectional capabilities, where each path in the N−1 number of paths is coupled to a connection point comprising a capacitor with a posi-tive terminal and a negative terminal, where each path comprises: an external two connection port configured to connect outside of the N-port multiport multilevel converter/inverter; a flying capacitor multilevel converter circuit path comprising a plurality of capacitors selectively interconnected to one another by a plurality of transistors to operate as a multilevel flying capacitor voltage converter; and an interface comprising a respective first interface transistor and a respective second interface transistor conveying DC power and that is electrically coupled to the connection point, and where first connection point further comprises: a first connection point conductor ohmically con-necting the respective first interface transistor of each path to the positive terminal of the capacitor; and a second connection point conductor ohmically con-necting the respective second interface transistor of each path to the negative terminal of the capaci-tor, and where the N-port multilevel converter/inverter is able to dispatch power from any external two connection port to any other external two connection port through the connection point, so as to perform conversion of any of DC-to-DC, DC-to-AC, AC-to-AC and AC-to-DC. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
multiport multilevel converter/inverter (two-path)
N-port multilevel converter/inverter
Materials described outside the worked examples.
GaN transistor
GaN
EPC₂₀₃₄C GaN switch
STL₅₇N₆₅M₅ MOSFET
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
DC-to-AC path efficiency (prototype) | 98.2 % | — |
AC voltage THD (prototype DC-to-AC path) |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Patent
Atlas literature
Patent
US 11,682,983 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B show an example three-port multilevel power converter/inverter, according to an example; B₂
FIG. 2 illustrates normalized inductor current ripple val- ues for two and four level FCML paths as a function of the duty cycle, according to an example;
FIG. 3 illustrates the DC-to-DC path gate timing diagram, according to an example;
FIG. 4 illustrates a generalized block diagram of the multiport multilevel converter, according to an example; and
FIG. 5 illustrates a generalized schematic of the multiport multilevel converter, according to an example.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A multiport multilevel converter/inverter, comprising: a connection point comprising a two-line connection; a capacitor electrically coupled across the two-line con-nection of the connection point, the capacitor compris-ing a positive terminal and a negative terminal; a first flying capacitor multilevel path comprising: a first external two connection port configured to con-nect outside of the multiport multilevel converter/inverter; a first flying capacitor multilevel converter circuit path comprising a first plurality of capacitors selectively interconnected to one another by a first plurality of GaN transistors to operate as a first multilevel flying capacitor voltage converter; and a first interface comprising a first interface transistor and a second interface transistor conveying DC power and that is electrically coupled to the connec-tion point; a second flying capacitor multilevel path comprising: a second external two connection port configured to connect outside of the multiport multilevel con-verter/inverter; 20 a second flying capacitor multilevel converter circuit path comprising a second plurality of capacitors selectively interconnected to one another by a second plurality of GaN transistors to operate as a second multilevel flying capacitor voltage converter; and 25 a second interface comprising a third interface transis-tor and a fourth interface transistor conveying DC power and that is electrically coupled to the connec-tion point, a first connection point conductor ohmically connect-ing, through the connection point, the first interface transistor, the positive terminal of the capacitor, and the third interface transistor; and a second connection point conductor ohmically con-necting, through the connection point, the second interface transistor, the negative terminal of the capacitor, and the fourth interface transistor.
The multiport multilevel converter/inverter of claim 1, further comprising a DC electrical port coupled to the connection point.
The multiport multilevel converter/inverter of claim 1, further comprising: a third flying capacitor multilevel path comprising: a third flying capacitor multilevel converter circuit path comprising a third plurality of capacitors selectively interconnected to one another by a third plurality of GaN transistors to operate as a third multilevel flying capacitor voltage converter; and a third external two connection port configured to connect outside of the multiport multilevel con-verter/inverter; and a third interface comprising a fifth interface transistor and a sixth interface transistor conveying DC power and that is electrically coupled to the connection point, wherein the first connection point conductor ohmically con-nects, through the connection point, the first interface transistor, the positive terminal of the capacitor, the third interface transistor, and the fifth interface tran-sistor; and the second connection point conductor ohmically con-nects, through the connection point, the second interface transistor, the negative terminal of the capacitor, the fourth interface transistor, and the sixth interface transistor.
The multiport multilevel converter/inverter of claim 1, where the first flying capacitor multilevel path comprises an B₂ unfolder to convert the voltage waveform produced within the first flying capacitor multilevel path to an AC power at the first external two connection port.
The multiport multilevel converter/inverter of claim 1, where the first flying capacitor multilevel path performs bidirectional DC-to-AC or AC-to-DC power conversion between the first external two connection port and the first interface.
The multiport multilevel converter/inverter of claim 1, where the second flying capacitor multilevel path performs bidirectional DC-to-DC power conversion between the sec-ond external two connection port and the second interface.
The multiport multilevel converter/inverter of claim 1, wherein any of the first external two connection port or the second external two connection port are configurable to convey DC or AC power.
The multiport multilevel converter/inverter of claim 1, wherein the first flying capacitor multilevel path and the second flying capacitor multilevel path each comprises a respective four level flying capacitor multilevel voltage converter circuit.
The multiport multilevel converter/inverter of claim 1, wherein the first plurality of GaN transistors are controlled by a phase shifted pulse width modulated signals operating to balance voltages across the plurality of flying capacitors.
An N-port multilevel converter/inverter comprising: any N number of external two connection ports; (N−1) number of paths where the paths are individually able to deploy FCML with any respective m number of levels odd or even, where all paths have bidirectional capabilities, where each path in the N−1 number of paths is coupled to a connection point comprising a capacitor with a posi-tive terminal and a negative terminal, where each path comprises: an external two connection port configured to connect outside of the N-port multiport multilevel converter/inverter; a flying capacitor multilevel converter circuit path comprising a plurality of capacitors selectively interconnected to one another by a plurality of transistors to operate as a multilevel flying capacitor voltage converter; and an interface comprising a respective first interface transistor and a respective second interface transistor conveying DC power and that is electrically coupled to the connection point, and where first connection point further comprises: a first connection point conductor ohmically con-necting the respective first interface transistor of each path to the positive terminal of the capacitor; and a second connection point conductor ohmically con-necting the respective second interface transistor of each path to the negative terminal of the capaci-tor, and where the N-port multilevel converter/inverter is able to dispatch power from any external two connection port to any other external two connection port through the connection point, so as to perform conversion of any of DC-to-DC, DC-to-AC, AC-to-AC and AC-to-DC. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
multiport multilevel converter/inverter (two-path)
N-port multilevel converter/inverter
Materials described outside the worked examples.
GaN transistor
GaN
EPC₂₀₃₄C GaN switch
STL₅₇N₆₅M₅ MOSFET
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
DC-to-AC path efficiency (prototype) | 98.2 % | — |
AC voltage THD (prototype DC-to-AC path) |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Patent
Atlas literature
Patent
US 11,682,983 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A and 1B show an example three-port multilevel power converter/inverter, according to an example; B₂
FIG. 2 illustrates normalized inductor current ripple val- ues for two and four level FCML paths as a function of the duty cycle, according to an example;
FIG. 3 illustrates the DC-to-DC path gate timing diagram, according to an example;
FIG. 4 illustrates a generalized block diagram of the multiport multilevel converter, according to an example; and
FIG. 5 illustrates a generalized schematic of the multiport multilevel converter, according to an example.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A multiport multilevel converter/inverter, comprising: a connection point comprising a two-line connection; a capacitor electrically coupled across the two-line con-nection of the connection point, the capacitor compris-ing a positive terminal and a negative terminal; a first flying capacitor multilevel path comprising: a first external two connection port configured to con-nect outside of the multiport multilevel converter/inverter; a first flying capacitor multilevel converter circuit path comprising a first plurality of capacitors selectively interconnected to one another by a first plurality of GaN transistors to operate as a first multilevel flying capacitor voltage converter; and a first interface comprising a first interface transistor and a second interface transistor conveying DC power and that is electrically coupled to the connec-tion point; a second flying capacitor multilevel path comprising: a second external two connection port configured to connect outside of the multiport multilevel con-verter/inverter; 20 a second flying capacitor multilevel converter circuit path comprising a second plurality of capacitors selectively interconnected to one another by a second plurality of GaN transistors to operate as a second multilevel flying capacitor voltage converter; and 25 a second interface comprising a third interface transis-tor and a fourth interface transistor conveying DC power and that is electrically coupled to the connec-tion point, a first connection point conductor ohmically connect-ing, through the connection point, the first interface transistor, the positive terminal of the capacitor, and the third interface transistor; and a second connection point conductor ohmically con-necting, through the connection point, the second interface transistor, the negative terminal of the capacitor, and the fourth interface transistor.
The multiport multilevel converter/inverter of claim 1, further comprising a DC electrical port coupled to the connection point.
The multiport multilevel converter/inverter of claim 1, further comprising: a third flying capacitor multilevel path comprising: a third flying capacitor multilevel converter circuit path comprising a third plurality of capacitors selectively interconnected to one another by a third plurality of GaN transistors to operate as a third multilevel flying capacitor voltage converter; and a third external two connection port configured to connect outside of the multiport multilevel con-verter/inverter; and a third interface comprising a fifth interface transistor and a sixth interface transistor conveying DC power and that is electrically coupled to the connection point, wherein the first connection point conductor ohmically con-nects, through the connection point, the first interface transistor, the positive terminal of the capacitor, the third interface transistor, and the fifth interface tran-sistor; and the second connection point conductor ohmically con-nects, through the connection point, the second interface transistor, the negative terminal of the capacitor, the fourth interface transistor, and the sixth interface transistor.
The multiport multilevel converter/inverter of claim 1, where the first flying capacitor multilevel path comprises an B₂ unfolder to convert the voltage waveform produced within the first flying capacitor multilevel path to an AC power at the first external two connection port.
The multiport multilevel converter/inverter of claim 1, where the first flying capacitor multilevel path performs bidirectional DC-to-AC or AC-to-DC power conversion between the first external two connection port and the first interface.
The multiport multilevel converter/inverter of claim 1, where the second flying capacitor multilevel path performs bidirectional DC-to-DC power conversion between the sec-ond external two connection port and the second interface.
The multiport multilevel converter/inverter of claim 1, wherein any of the first external two connection port or the second external two connection port are configurable to convey DC or AC power.
The multiport multilevel converter/inverter of claim 1, wherein the first flying capacitor multilevel path and the second flying capacitor multilevel path each comprises a respective four level flying capacitor multilevel voltage converter circuit.
The multiport multilevel converter/inverter of claim 1, wherein the first plurality of GaN transistors are controlled by a phase shifted pulse width modulated signals operating to balance voltages across the plurality of flying capacitors.
An N-port multilevel converter/inverter comprising: any N number of external two connection ports; (N−1) number of paths where the paths are individually able to deploy FCML with any respective m number of levels odd or even, where all paths have bidirectional capabilities, where each path in the N−1 number of paths is coupled to a connection point comprising a capacitor with a posi-tive terminal and a negative terminal, where each path comprises: an external two connection port configured to connect outside of the N-port multiport multilevel converter/inverter; a flying capacitor multilevel converter circuit path comprising a plurality of capacitors selectively interconnected to one another by a plurality of transistors to operate as a multilevel flying capacitor voltage converter; and an interface comprising a respective first interface transistor and a respective second interface transistor conveying DC power and that is electrically coupled to the connection point, and where first connection point further comprises: a first connection point conductor ohmically con-necting the respective first interface transistor of each path to the positive terminal of the capacitor; and a second connection point conductor ohmically con-necting the respective second interface transistor of each path to the negative terminal of the capaci-tor, and where the N-port multilevel converter/inverter is able to dispatch power from any external two connection port to any other external two connection port through the connection point, so as to perform conversion of any of DC-to-DC, DC-to-AC, AC-to-AC and AC-to-DC. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
multiport multilevel converter/inverter (two-path)
N-port multilevel converter/inverter
Materials described outside the worked examples.
GaN transistor
GaN
EPC₂₀₃₄C GaN switch
STL₅₇N₆₅M₅ MOSFET
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
DC-to-AC path efficiency (prototype) | 98.2 % | — |
AC voltage THD (prototype DC-to-AC path) |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
three-port prototype converter/inverter (two 4-level FCML paths)
| — |
AC current THD (prototype DC-to-AC path) | 1.23 % | — |
DC-to-DC path peak efficiency (prototype) | 99.43 % | — |
Voltage | 108–180 V | — |
Cited non-patent literature · 6
three-port prototype converter/inverter (two 4-level FCML paths)
| — |
AC current THD (prototype DC-to-AC path) | 1.23 % | — |
DC-to-DC path peak efficiency (prototype) | 99.43 % | — |
Voltage | 108–180 V | — |
Cited non-patent literature · 6
three-port prototype converter/inverter (two 4-level FCML paths)
| — |
AC current THD (prototype DC-to-AC path) | 1.23 % | — |
DC-to-DC path peak efficiency (prototype) | 99.43 % | — |
Voltage | 108–180 V | — |
Cited non-patent literature · 6
three-port prototype converter/inverter (two 4-level FCML paths)
| — |
AC current THD (prototype DC-to-AC path) | 1.23 % | — |
DC-to-DC path peak efficiency (prototype) | 99.43 % | — |
Voltage | 108–180 V | — |
Cited non-patent literature · 6
