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A method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz, comprising the following steps: (1) sequentially growing, on a silicon substrate, an N-polar GaN buffer layer, a carbon doped semi-insulating N-polar GaN layer, a nondoped N-polar Al GaN layer, a non-doped N-polar GaN layer and a non-doped N-polar InGaN thin film to obtain a GaN rectifier epitaxial wafer; (2) placing the GaN rectifier epitaxial wafer obtained in step (1) sequentially into acetone, deionized water and anhydrous ethanol for an ultrasonic treatment, and cleaning the GaN rectifier epitaxial wafer with deionized water and then drying the GaN rectifier epitaxial wafer by hot and high purity nitrogen; (3) performing a lithographic preparation of a schottky contact electrode pattern on the GaN rectifier epitaxial wafer obtained in step (2) by spin-coating the GaN rectifier epitaxial wafer obtained in step (2) uniformly with a photoresist, pre-baking and then exposing the GaN rectifier epitaxial wafer coated with the photoresist in a lithography machine, and finally immersing the exposed GaN rectifier epitaxial wafer in a developing liquid for a lithographic development and cleaning; (4) performing a reactive ion etching on the GaN rectifier epitaxial wafer after the GaN rectifier epitaxial wafer is subjected to the lithographic process in step (3), and etching grooves along the schottky contact electrode patterns in the GaN rectifier epitaxial wafer to obtain an ohmic contact electrode; (5) placing the GaN rectifier epitaxial wafer having the etched grooves corresponding to patterns of the ohmic contact electrode obtained in step (4) into an evaporation chamber o f including an electron beam evaporation device and evacuating the evaporation chamber, followed by successively evaporating schottky contact electrode metals, and after the evaporation, annealing the GaN rectifier epitaxial wafer; (6) removing the photoresist by immersing the GaN rectifier epitaxial wafer into a degumming liquid, rinsing the GaN rectifier epitaxial wafer with deionized water and performing an ultrasonic treatment by using acetone to remove residual photoresist and evaporated metals on a surface of the GaN rectifier epitaxial wafer, and after the ultrasonic treatment, cleaning the GaN rectifier epitaxial wafer with the deionized water and drying the GaN rectifier epitaxial wafer with hot and high purity nitrogen; (7) aligning the GaN rectifier epitaxial wafer with an alignment mark in a mask, repeating the process in step (3) to perform a lithographic development at corresponding positions, and preparing device ohmic contact electrode patterns and cleaning the GaN rectifier epitaxial wafer; (8) conducting an ohmic contact electrode preparation on the GaN rectifier epitaxial wafer by placing the GaN rectifier epitaxial wafer with the developed ohmic contact electrode patterns obtained in step (7) into the electron beam evaporation device and evacuating the evaporation chamber, followed by successively evaporating the ohmic contact electrode metals, and after the evaporation, annealing the GaN rectifier epitaxial wafer; (9) repeating the process in step (6) to remove residual photoresist and evaporated metal on the surface of the GaN epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning; (10) preparing a silicon nitride passivation layer using a plasma enhanced chemical vapor deposition method by placing the GaN rectifier epitaxial wafer obtained in step (9) into a plasma enhanced chemical vapor deposition device, warming up the GaN rectifier epitaxial wafer and evacuating to a high vacuum, and then introducing a carrier gas and a reactive gas into the plasma enhanced chemical vapor deposition device, and then depositing an SiN x passivation layer on the surface of the GaN rectifier epitaxial wafer, where x = 1.33-1.5; (11) repeating the process in step (3), preparing a mask on the surface of the GaN epitaxial wafer by means of a lithographic development, and exposing the SiNx passivation layer on the patterns of the ohmic contact electrode and the schottky contact electrode; (12) etching away the exposed SiNx passivation la y er by using a wet etching method, and repeating the process in step (6) to remove residual photoresist on the surface of the GaN rectifier epitaxial wafer and the silicon nitride passivation layer and clean the GaN rectifier epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning; (13) performing alignment by means of the alignment mark in the mask, and repeating the process in step (3) to prepare mesa isolation patterns on the surface of the GaN rectifier epitaxial wafer by means of a lithographic development; (14) performing a mesa isolation process by repeating the process in step (4) to etch grooves on the surface of the GaN rectifier epitaxial wafer obtained in step (13) by using a reactive ion etching device and cleaning up the epitaxial wafer; (15) fabricating a mesa isolation passivation layer by placing the GaN rectifier epitaxial wafer obtained in step (14) into a plasma-assisted chemical vapor deposition device, and repeating the process in step (10) to deposit an SiN x passivation layer inside the etched grooves of the GaN rectifier epitaxial wafer; and (16) after removing an excessive SiNx layer on the surface of the GaN rectifier epitaxial wafer processed in step (15) by using the wet etching process in step (12), removing the residual SiNx and photoresist on the surface of the GaN rectifier epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning by using the process in step (6), so as to finally obtain a GaN rectifier chip, suitable for operating at an alternating current frequency of 35 GHz, on the silicon substrate. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the silicon substrate in step (1) has a (111) close-packed plane as an epitaxial plane; and all of the N-polar GaN buffer layer, the carbon doped semi-insulated N-polar GaN layer, the non-doped N-polar A l GaN layer, the non-doped N-polar GaN layer and the non- doped N-polar InGaN thin film take (0001) as an epitaxial direction. Original
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the durations for the ultrasonic treatment in steps (2) and (6) are both 3-15 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the photoresist in step (3) is 0.2-0.7 m in thickness; the time for exposure is 1-4 seconds; and the time for development is 45-95 seconds. Previously presented
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the grooves in step (4) i-s are 150-400 nm in depth. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein vacuum degrees of the vacuum in steps (5) and (8) are both 1-5 x 10- 5 Pa; the temperatures for annealing in steps (5) and (8) are both 450-800 ° C; and the durations for annealing are both 30-120 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the duration for the immersion in step (6) is 45-100 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the times for deposition of the SiN x passivation layer in steps (10) and (15) are both 60-120 minutes. Previously presented
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the grooves in step (14) i-s are 1-2.5 p m in depth. Currently amended
A GaN rectifier suitable for operating at an alternating current frequency of 35 GHz obtained by the method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN rectifier (Schottky diode) for 35 GHz AC operation
Materials described outside the worked examples.
silicon substrate
Si
N-polar GaN buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Pressure | 0.00001 Pa | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz, comprising the following steps: (1) sequentially growing, on a silicon substrate, an N-polar GaN buffer layer, a carbon doped semi-insulating N-polar GaN layer, a nondoped N-polar Al GaN layer, a non-doped N-polar GaN layer and a non-doped N-polar InGaN thin film to obtain a GaN rectifier epitaxial wafer; (2) placing the GaN rectifier epitaxial wafer obtained in step (1) sequentially into acetone, deionized water and anhydrous ethanol for an ultrasonic treatment, and cleaning the GaN rectifier epitaxial wafer with deionized water and then drying the GaN rectifier epitaxial wafer by hot and high purity nitrogen; (3) performing a lithographic preparation of a schottky contact electrode pattern on the GaN rectifier epitaxial wafer obtained in step (2) by spin-coating the GaN rectifier epitaxial wafer obtained in step (2) uniformly with a photoresist, pre-baking and then exposing the GaN rectifier epitaxial wafer coated with the photoresist in a lithography machine, and finally immersing the exposed GaN rectifier epitaxial wafer in a developing liquid for a lithographic development and cleaning; (4) performing a reactive ion etching on the GaN rectifier epitaxial wafer after the GaN rectifier epitaxial wafer is subjected to the lithographic process in step (3), and etching grooves along the schottky contact electrode patterns in the GaN rectifier epitaxial wafer to obtain an ohmic contact electrode; (5) placing the GaN rectifier epitaxial wafer having the etched grooves corresponding to patterns of the ohmic contact electrode obtained in step (4) into an evaporation chamber o f including an electron beam evaporation device and evacuating the evaporation chamber, followed by successively evaporating schottky contact electrode metals, and after the evaporation, annealing the GaN rectifier epitaxial wafer; (6) removing the photoresist by immersing the GaN rectifier epitaxial wafer into a degumming liquid, rinsing the GaN rectifier epitaxial wafer with deionized water and performing an ultrasonic treatment by using acetone to remove residual photoresist and evaporated metals on a surface of the GaN rectifier epitaxial wafer, and after the ultrasonic treatment, cleaning the GaN rectifier epitaxial wafer with the deionized water and drying the GaN rectifier epitaxial wafer with hot and high purity nitrogen; (7) aligning the GaN rectifier epitaxial wafer with an alignment mark in a mask, repeating the process in step (3) to perform a lithographic development at corresponding positions, and preparing device ohmic contact electrode patterns and cleaning the GaN rectifier epitaxial wafer; (8) conducting an ohmic contact electrode preparation on the GaN rectifier epitaxial wafer by placing the GaN rectifier epitaxial wafer with the developed ohmic contact electrode patterns obtained in step (7) into the electron beam evaporation device and evacuating the evaporation chamber, followed by successively evaporating the ohmic contact electrode metals, and after the evaporation, annealing the GaN rectifier epitaxial wafer; (9) repeating the process in step (6) to remove residual photoresist and evaporated metal on the surface of the GaN epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning; (10) preparing a silicon nitride passivation layer using a plasma enhanced chemical vapor deposition method by placing the GaN rectifier epitaxial wafer obtained in step (9) into a plasma enhanced chemical vapor deposition device, warming up the GaN rectifier epitaxial wafer and evacuating to a high vacuum, and then introducing a carrier gas and a reactive gas into the plasma enhanced chemical vapor deposition device, and then depositing an SiN x passivation layer on the surface of the GaN rectifier epitaxial wafer, where x = 1.33-1.5; (11) repeating the process in step (3), preparing a mask on the surface of the GaN epitaxial wafer by means of a lithographic development, and exposing the SiNx passivation layer on the patterns of the ohmic contact electrode and the schottky contact electrode; (12) etching away the exposed SiNx passivation la y er by using a wet etching method, and repeating the process in step (6) to remove residual photoresist on the surface of the GaN rectifier epitaxial wafer and the silicon nitride passivation layer and clean the GaN rectifier epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning; (13) performing alignment by means of the alignment mark in the mask, and repeating the process in step (3) to prepare mesa isolation patterns on the surface of the GaN rectifier epitaxial wafer by means of a lithographic development; (14) performing a mesa isolation process by repeating the process in step (4) to etch grooves on the surface of the GaN rectifier epitaxial wafer obtained in step (13) by using a reactive ion etching device and cleaning up the epitaxial wafer; (15) fabricating a mesa isolation passivation layer by placing the GaN rectifier epitaxial wafer obtained in step (14) into a plasma-assisted chemical vapor deposition device, and repeating the process in step (10) to deposit an SiN x passivation layer inside the etched grooves of the GaN rectifier epitaxial wafer; and (16) after removing an excessive SiNx layer on the surface of the GaN rectifier epitaxial wafer processed in step (15) by using the wet etching process in step (12), removing the residual SiNx and photoresist on the surface of the GaN rectifier epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning by using the process in step (6), so as to finally obtain a GaN rectifier chip, suitable for operating at an alternating current frequency of 35 GHz, on the silicon substrate. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the silicon substrate in step (1) has a (111) close-packed plane as an epitaxial plane; and all of the N-polar GaN buffer layer, the carbon doped semi-insulated N-polar GaN layer, the non-doped N-polar A l GaN layer, the non-doped N-polar GaN layer and the non- doped N-polar InGaN thin film take (0001) as an epitaxial direction. Original
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the durations for the ultrasonic treatment in steps (2) and (6) are both 3-15 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the photoresist in step (3) is 0.2-0.7 m in thickness; the time for exposure is 1-4 seconds; and the time for development is 45-95 seconds. Previously presented
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the grooves in step (4) i-s are 150-400 nm in depth. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein vacuum degrees of the vacuum in steps (5) and (8) are both 1-5 x 10- 5 Pa; the temperatures for annealing in steps (5) and (8) are both 450-800 ° C; and the durations for annealing are both 30-120 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the duration for the immersion in step (6) is 45-100 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the times for deposition of the SiN x passivation layer in steps (10) and (15) are both 60-120 minutes. Previously presented
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the grooves in step (14) i-s are 1-2.5 p m in depth. Currently amended
A GaN rectifier suitable for operating at an alternating current frequency of 35 GHz obtained by the method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN rectifier (Schottky diode) for 35 GHz AC operation
Materials described outside the worked examples.
silicon substrate
Si
N-polar GaN buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Pressure | 0.00001 Pa | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz, comprising the following steps: (1) sequentially growing, on a silicon substrate, an N-polar GaN buffer layer, a carbon doped semi-insulating N-polar GaN layer, a nondoped N-polar Al GaN layer, a non-doped N-polar GaN layer and a non-doped N-polar InGaN thin film to obtain a GaN rectifier epitaxial wafer; (2) placing the GaN rectifier epitaxial wafer obtained in step (1) sequentially into acetone, deionized water and anhydrous ethanol for an ultrasonic treatment, and cleaning the GaN rectifier epitaxial wafer with deionized water and then drying the GaN rectifier epitaxial wafer by hot and high purity nitrogen; (3) performing a lithographic preparation of a schottky contact electrode pattern on the GaN rectifier epitaxial wafer obtained in step (2) by spin-coating the GaN rectifier epitaxial wafer obtained in step (2) uniformly with a photoresist, pre-baking and then exposing the GaN rectifier epitaxial wafer coated with the photoresist in a lithography machine, and finally immersing the exposed GaN rectifier epitaxial wafer in a developing liquid for a lithographic development and cleaning; (4) performing a reactive ion etching on the GaN rectifier epitaxial wafer after the GaN rectifier epitaxial wafer is subjected to the lithographic process in step (3), and etching grooves along the schottky contact electrode patterns in the GaN rectifier epitaxial wafer to obtain an ohmic contact electrode; (5) placing the GaN rectifier epitaxial wafer having the etched grooves corresponding to patterns of the ohmic contact electrode obtained in step (4) into an evaporation chamber o f including an electron beam evaporation device and evacuating the evaporation chamber, followed by successively evaporating schottky contact electrode metals, and after the evaporation, annealing the GaN rectifier epitaxial wafer; (6) removing the photoresist by immersing the GaN rectifier epitaxial wafer into a degumming liquid, rinsing the GaN rectifier epitaxial wafer with deionized water and performing an ultrasonic treatment by using acetone to remove residual photoresist and evaporated metals on a surface of the GaN rectifier epitaxial wafer, and after the ultrasonic treatment, cleaning the GaN rectifier epitaxial wafer with the deionized water and drying the GaN rectifier epitaxial wafer with hot and high purity nitrogen; (7) aligning the GaN rectifier epitaxial wafer with an alignment mark in a mask, repeating the process in step (3) to perform a lithographic development at corresponding positions, and preparing device ohmic contact electrode patterns and cleaning the GaN rectifier epitaxial wafer; (8) conducting an ohmic contact electrode preparation on the GaN rectifier epitaxial wafer by placing the GaN rectifier epitaxial wafer with the developed ohmic contact electrode patterns obtained in step (7) into the electron beam evaporation device and evacuating the evaporation chamber, followed by successively evaporating the ohmic contact electrode metals, and after the evaporation, annealing the GaN rectifier epitaxial wafer; (9) repeating the process in step (6) to remove residual photoresist and evaporated metal on the surface of the GaN epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning; (10) preparing a silicon nitride passivation layer using a plasma enhanced chemical vapor deposition method by placing the GaN rectifier epitaxial wafer obtained in step (9) into a plasma enhanced chemical vapor deposition device, warming up the GaN rectifier epitaxial wafer and evacuating to a high vacuum, and then introducing a carrier gas and a reactive gas into the plasma enhanced chemical vapor deposition device, and then depositing an SiN x passivation layer on the surface of the GaN rectifier epitaxial wafer, where x = 1.33-1.5; (11) repeating the process in step (3), preparing a mask on the surface of the GaN epitaxial wafer by means of a lithographic development, and exposing the SiNx passivation layer on the patterns of the ohmic contact electrode and the schottky contact electrode; (12) etching away the exposed SiNx passivation la y er by using a wet etching method, and repeating the process in step (6) to remove residual photoresist on the surface of the GaN rectifier epitaxial wafer and the silicon nitride passivation layer and clean the GaN rectifier epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning; (13) performing alignment by means of the alignment mark in the mask, and repeating the process in step (3) to prepare mesa isolation patterns on the surface of the GaN rectifier epitaxial wafer by means of a lithographic development; (14) performing a mesa isolation process by repeating the process in step (4) to etch grooves on the surface of the GaN rectifier epitaxial wafer obtained in step (13) by using a reactive ion etching device and cleaning up the epitaxial wafer; (15) fabricating a mesa isolation passivation layer by placing the GaN rectifier epitaxial wafer obtained in step (14) into a plasma-assisted chemical vapor deposition device, and repeating the process in step (10) to deposit an SiN x passivation layer inside the etched grooves of the GaN rectifier epitaxial wafer; and (16) after removing an excessive SiNx layer on the surface of the GaN rectifier epitaxial wafer processed in step (15) by using the wet etching process in step (12), removing the residual SiNx and photoresist on the surface of the GaN rectifier epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning by using the process in step (6), so as to finally obtain a GaN rectifier chip, suitable for operating at an alternating current frequency of 35 GHz, on the silicon substrate. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the silicon substrate in step (1) has a (111) close-packed plane as an epitaxial plane; and all of the N-polar GaN buffer layer, the carbon doped semi-insulated N-polar GaN layer, the non-doped N-polar A l GaN layer, the non-doped N-polar GaN layer and the non- doped N-polar InGaN thin film take (0001) as an epitaxial direction. Original
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the durations for the ultrasonic treatment in steps (2) and (6) are both 3-15 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the photoresist in step (3) is 0.2-0.7 m in thickness; the time for exposure is 1-4 seconds; and the time for development is 45-95 seconds. Previously presented
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the grooves in step (4) i-s are 150-400 nm in depth. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein vacuum degrees of the vacuum in steps (5) and (8) are both 1-5 x 10- 5 Pa; the temperatures for annealing in steps (5) and (8) are both 450-800 ° C; and the durations for annealing are both 30-120 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the duration for the immersion in step (6) is 45-100 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the times for deposition of the SiN x passivation layer in steps (10) and (15) are both 60-120 minutes. Previously presented
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the grooves in step (14) i-s are 1-2.5 p m in depth. Currently amended
A GaN rectifier suitable for operating at an alternating current frequency of 35 GHz obtained by the method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN rectifier (Schottky diode) for 35 GHz AC operation
Materials described outside the worked examples.
silicon substrate
Si
N-polar GaN buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Pressure | 0.00001 Pa | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz, comprising the following steps: (1) sequentially growing, on a silicon substrate, an N-polar GaN buffer layer, a carbon doped semi-insulating N-polar GaN layer, a nondoped N-polar Al GaN layer, a non-doped N-polar GaN layer and a non-doped N-polar InGaN thin film to obtain a GaN rectifier epitaxial wafer; (2) placing the GaN rectifier epitaxial wafer obtained in step (1) sequentially into acetone, deionized water and anhydrous ethanol for an ultrasonic treatment, and cleaning the GaN rectifier epitaxial wafer with deionized water and then drying the GaN rectifier epitaxial wafer by hot and high purity nitrogen; (3) performing a lithographic preparation of a schottky contact electrode pattern on the GaN rectifier epitaxial wafer obtained in step (2) by spin-coating the GaN rectifier epitaxial wafer obtained in step (2) uniformly with a photoresist, pre-baking and then exposing the GaN rectifier epitaxial wafer coated with the photoresist in a lithography machine, and finally immersing the exposed GaN rectifier epitaxial wafer in a developing liquid for a lithographic development and cleaning; (4) performing a reactive ion etching on the GaN rectifier epitaxial wafer after the GaN rectifier epitaxial wafer is subjected to the lithographic process in step (3), and etching grooves along the schottky contact electrode patterns in the GaN rectifier epitaxial wafer to obtain an ohmic contact electrode; (5) placing the GaN rectifier epitaxial wafer having the etched grooves corresponding to patterns of the ohmic contact electrode obtained in step (4) into an evaporation chamber o f including an electron beam evaporation device and evacuating the evaporation chamber, followed by successively evaporating schottky contact electrode metals, and after the evaporation, annealing the GaN rectifier epitaxial wafer; (6) removing the photoresist by immersing the GaN rectifier epitaxial wafer into a degumming liquid, rinsing the GaN rectifier epitaxial wafer with deionized water and performing an ultrasonic treatment by using acetone to remove residual photoresist and evaporated metals on a surface of the GaN rectifier epitaxial wafer, and after the ultrasonic treatment, cleaning the GaN rectifier epitaxial wafer with the deionized water and drying the GaN rectifier epitaxial wafer with hot and high purity nitrogen; (7) aligning the GaN rectifier epitaxial wafer with an alignment mark in a mask, repeating the process in step (3) to perform a lithographic development at corresponding positions, and preparing device ohmic contact electrode patterns and cleaning the GaN rectifier epitaxial wafer; (8) conducting an ohmic contact electrode preparation on the GaN rectifier epitaxial wafer by placing the GaN rectifier epitaxial wafer with the developed ohmic contact electrode patterns obtained in step (7) into the electron beam evaporation device and evacuating the evaporation chamber, followed by successively evaporating the ohmic contact electrode metals, and after the evaporation, annealing the GaN rectifier epitaxial wafer; (9) repeating the process in step (6) to remove residual photoresist and evaporated metal on the surface of the GaN epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning; (10) preparing a silicon nitride passivation layer using a plasma enhanced chemical vapor deposition method by placing the GaN rectifier epitaxial wafer obtained in step (9) into a plasma enhanced chemical vapor deposition device, warming up the GaN rectifier epitaxial wafer and evacuating to a high vacuum, and then introducing a carrier gas and a reactive gas into the plasma enhanced chemical vapor deposition device, and then depositing an SiN x passivation layer on the surface of the GaN rectifier epitaxial wafer, where x = 1.33-1.5; (11) repeating the process in step (3), preparing a mask on the surface of the GaN epitaxial wafer by means of a lithographic development, and exposing the SiNx passivation layer on the patterns of the ohmic contact electrode and the schottky contact electrode; (12) etching away the exposed SiNx passivation la y er by using a wet etching method, and repeating the process in step (6) to remove residual photoresist on the surface of the GaN rectifier epitaxial wafer and the silicon nitride passivation layer and clean the GaN rectifier epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning; (13) performing alignment by means of the alignment mark in the mask, and repeating the process in step (3) to prepare mesa isolation patterns on the surface of the GaN rectifier epitaxial wafer by means of a lithographic development; (14) performing a mesa isolation process by repeating the process in step (4) to etch grooves on the surface of the GaN rectifier epitaxial wafer obtained in step (13) by using a reactive ion etching device and cleaning up the epitaxial wafer; (15) fabricating a mesa isolation passivation layer by placing the GaN rectifier epitaxial wafer obtained in step (14) into a plasma-assisted chemical vapor deposition device, and repeating the process in step (10) to deposit an SiN x passivation layer inside the etched grooves of the GaN rectifier epitaxial wafer; and (16) after removing an excessive SiNx layer on the surface of the GaN rectifier epitaxial wafer processed in step (15) by using the wet etching process in step (12), removing the residual SiNx and photoresist on the surface of the GaN rectifier epitaxial wafer by means of immersion in the degumming liquid and an ultrasonic cleaning by using the process in step (6), so as to finally obtain a GaN rectifier chip, suitable for operating at an alternating current frequency of 35 GHz, on the silicon substrate. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the silicon substrate in step (1) has a (111) close-packed plane as an epitaxial plane; and all of the N-polar GaN buffer layer, the carbon doped semi-insulated N-polar GaN layer, the non-doped N-polar A l GaN layer, the non-doped N-polar GaN layer and the non- doped N-polar InGaN thin film take (0001) as an epitaxial direction. Original
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the durations for the ultrasonic treatment in steps (2) and (6) are both 3-15 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the photoresist in step (3) is 0.2-0.7 m in thickness; the time for exposure is 1-4 seconds; and the time for development is 45-95 seconds. Previously presented
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the grooves in step (4) i-s are 150-400 nm in depth. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein vacuum degrees of the vacuum in steps (5) and (8) are both 1-5 x 10- 5 Pa; the temperatures for annealing in steps (5) and (8) are both 450-800 ° C; and the durations for annealing are both 30-120 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the duration for the immersion in step (6) is 45-100 minutes. Currently amended
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the times for deposition of the SiN x passivation layer in steps (10) and (15) are both 60-120 minutes. Previously presented
The method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1, wherein the grooves in step (14) i-s are 1-2.5 p m in depth. Currently amended
A GaN rectifier suitable for operating at an alternating current frequency of 35 GHz obtained by the method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz according to claim 1. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN rectifier (Schottky diode) for 35 GHz AC operation
Materials described outside the worked examples.
silicon substrate
Si
N-polar GaN buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Pressure | 0.00001 Pa | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
carbon doped semi-insulating N-polar GaN layer
GaN:C
non-doped N-polar AlGaN layer
AlGaN
non-doped N-polar InGaN thin film
InGaN
SiNx passivation layer
SiNx
| ≤ 0.9 Å |
| — |
Duration | 3–15 minutes | — |
Duration | 1–4 seconds | — |
Duration | 45–95 seconds | — |
Thickness | 150–400 nm | — |
Temperature | 450–800 °C | — |
Duration | 30–120 minutes | — |
Duration | 45–100 minutes | — |
Duration | 60–120 minutes | — |
Duration | 3–15 mins | — |
carbon doped semi-insulating N-polar GaN layer
GaN:C
non-doped N-polar AlGaN layer
AlGaN
non-doped N-polar InGaN thin film
InGaN
SiNx passivation layer
SiNx
| ≤ 0.9 Å |
| — |
Duration | 3–15 minutes | — |
Duration | 1–4 seconds | — |
Duration | 45–95 seconds | — |
Thickness | 150–400 nm | — |
Temperature | 450–800 °C | — |
Duration | 30–120 minutes | — |
Duration | 45–100 minutes | — |
Duration | 60–120 minutes | — |
Duration | 3–15 mins | — |
carbon doped semi-insulating N-polar GaN layer
GaN:C
non-doped N-polar AlGaN layer
AlGaN
non-doped N-polar InGaN thin film
InGaN
SiNx passivation layer
SiNx
| ≤ 0.9 Å |
| — |
Duration | 3–15 minutes | — |
Duration | 1–4 seconds | — |
Duration | 45–95 seconds | — |
Thickness | 150–400 nm | — |
Temperature | 450–800 °C | — |
Duration | 30–120 minutes | — |
Duration | 45–100 minutes | — |
Duration | 60–120 minutes | — |
Duration | 3–15 mins | — |
carbon doped semi-insulating N-polar GaN layer
GaN:C
non-doped N-polar AlGaN layer
AlGaN
non-doped N-polar InGaN thin film
InGaN
SiNx passivation layer
SiNx
| ≤ 0.9 Å |
| — |
Duration | 3–15 minutes | — |
Duration | 1–4 seconds | — |
Duration | 45–95 seconds | — |
Thickness | 150–400 nm | — |
Temperature | 450–800 °C | — |
Duration | 30–120 minutes | — |
Duration | 45–100 minutes | — |
Duration | 60–120 minutes | — |
Duration | 3–15 mins | — |