Patent
US 9,312,368GRAPHENE DEVICE INCLUDING SEPARATED JUNCTION CONTACTS AND METHOD OF MANUFACTURING THE SAME
Jae-ho LEE
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,312,368Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view schematically illustrating a structure of a graphene device according to at least one example embodiment; [26]
FIGS. 2A to 2 C are energy band diagrams schematically illustrating an operation of the graphene device of
FIGS. 3A to 3F are cross-sectional views schematically illustrating processes of manufacturing the graphene device of
FIG. 4 is a cross-sectional view schematically illustrating a structure of a graphene device according to another example embodiment; and [29]
FIG. 5 is a flow chart illustrating a method of manufacturing the graphene device, according to at least one example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene device, comprising: a graphene channel layer; a gate electrode configured to apply an electric field to the graphene channel layer; first and second junction contact layers contacting at least portions of the graphene channel layer, [[and l wherein the first and second junction contact layers are electrically and physically separated from each other; and wherein the graphene channel layer is on at least portions of top surfaces of the first junction contact layer and the second junction contact layer, and on a top surface of a separation film, and the second junction contact layer.
The graphene device of claim 1, further comprising a substrate, wherein the first and second junction contact layers are adjacently disposed on at least a portion of a top surface of the substrate.
The graphene device of claim 1, further comprising a gate insulating film on at least portions of the top surfaces of the first junction contact layer and the second junction contact layer and covering the graphene channel layer, wherein the gate electrode is on the gate insulating film opposite to the graphene channel layer.
The graphene device of claim 1, further comprising a substrate including an insulating material, wherein the gate electrode is on the substrate. withdrawn
The graphene device, of claim 1, wherein the separation film is between the first junction contact layer and the second junction contact layer. *** END CLAIM LISTING *** Page 6
canceled
A transistor comprising: a first junction layer coplanar with a second junction layer, the first junction layer and the second junction layer being separated by an insulating trench; a graphene channel layer in contact with at least portions of the first junction layer s and the second junction layer, and in contact with the insulating trench; a gate insulating layer in contact with the graphene channel layer and at least portions of the first junction-layer and the second junction layer; a gate in contact with the gate insulating layer; and a source electrode and a drain electrode on uncovered portions of the first junction layer and the second junction layer, respectively; the source electrode and the drain electrode being connected to the graphene channel layer via the first junction layer and the second junction layer, respectively.
The transistor of claim 15, wherein the insulating trench includes one of air and an insulating material.
The transistor of claim 15, wherein at least one of the first junction layer and the second junction layer comprises silicon.
The transistor of claim 15, wherein the first junction layer and the second junction layer are doped to have a same conduction type.
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET with separated junction contacts (top-gate, bottom-junction configuration)
Materials described outside the worked examples.
graphene
doped semiconductor junction contact layer
silicon
Si
Additional fabrication and treatment steps described in the patent.
Patent
Atlas literature
Patent
US 9,312,368Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view schematically illustrating a structure of a graphene device according to at least one example embodiment; [26]
FIGS. 2A to 2 C are energy band diagrams schematically illustrating an operation of the graphene device of
FIGS. 3A to 3F are cross-sectional views schematically illustrating processes of manufacturing the graphene device of
FIG. 4 is a cross-sectional view schematically illustrating a structure of a graphene device according to another example embodiment; and [29]
FIG. 5 is a flow chart illustrating a method of manufacturing the graphene device, according to at least one example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene device, comprising: a graphene channel layer; a gate electrode configured to apply an electric field to the graphene channel layer; first and second junction contact layers contacting at least portions of the graphene channel layer, [[and l wherein the first and second junction contact layers are electrically and physically separated from each other; and wherein the graphene channel layer is on at least portions of top surfaces of the first junction contact layer and the second junction contact layer, and on a top surface of a separation film, and the second junction contact layer.
The graphene device of claim 1, further comprising a substrate, wherein the first and second junction contact layers are adjacently disposed on at least a portion of a top surface of the substrate.
The graphene device of claim 1, further comprising a gate insulating film on at least portions of the top surfaces of the first junction contact layer and the second junction contact layer and covering the graphene channel layer, wherein the gate electrode is on the gate insulating film opposite to the graphene channel layer.
The graphene device of claim 1, further comprising a substrate including an insulating material, wherein the gate electrode is on the substrate. withdrawn
The graphene device, of claim 1, wherein the separation film is between the first junction contact layer and the second junction contact layer. *** END CLAIM LISTING *** Page 6
canceled
A transistor comprising: a first junction layer coplanar with a second junction layer, the first junction layer and the second junction layer being separated by an insulating trench; a graphene channel layer in contact with at least portions of the first junction layer s and the second junction layer, and in contact with the insulating trench; a gate insulating layer in contact with the graphene channel layer and at least portions of the first junction-layer and the second junction layer; a gate in contact with the gate insulating layer; and a source electrode and a drain electrode on uncovered portions of the first junction layer and the second junction layer, respectively; the source electrode and the drain electrode being connected to the graphene channel layer via the first junction layer and the second junction layer, respectively.
The transistor of claim 15, wherein the insulating trench includes one of air and an insulating material.
The transistor of claim 15, wherein at least one of the first junction layer and the second junction layer comprises silicon.
The transistor of claim 15, wherein the first junction layer and the second junction layer are doped to have a same conduction type.
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET with separated junction contacts (top-gate, bottom-junction configuration)
Materials described outside the worked examples.
graphene
doped semiconductor junction contact layer
silicon
Si
Additional fabrication and treatment steps described in the patent.
Patent
Atlas literature
Patent
US 9,312,368Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view schematically illustrating a structure of a graphene device according to at least one example embodiment; [26]
FIGS. 2A to 2 C are energy band diagrams schematically illustrating an operation of the graphene device of
FIGS. 3A to 3F are cross-sectional views schematically illustrating processes of manufacturing the graphene device of
FIG. 4 is a cross-sectional view schematically illustrating a structure of a graphene device according to another example embodiment; and [29]
FIG. 5 is a flow chart illustrating a method of manufacturing the graphene device, according to at least one example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene device, comprising: a graphene channel layer; a gate electrode configured to apply an electric field to the graphene channel layer; first and second junction contact layers contacting at least portions of the graphene channel layer, [[and l wherein the first and second junction contact layers are electrically and physically separated from each other; and wherein the graphene channel layer is on at least portions of top surfaces of the first junction contact layer and the second junction contact layer, and on a top surface of a separation film, and the second junction contact layer.
The graphene device of claim 1, further comprising a substrate, wherein the first and second junction contact layers are adjacently disposed on at least a portion of a top surface of the substrate.
The graphene device of claim 1, further comprising a gate insulating film on at least portions of the top surfaces of the first junction contact layer and the second junction contact layer and covering the graphene channel layer, wherein the gate electrode is on the gate insulating film opposite to the graphene channel layer.
The graphene device of claim 1, further comprising a substrate including an insulating material, wherein the gate electrode is on the substrate. withdrawn
The graphene device, of claim 1, wherein the separation film is between the first junction contact layer and the second junction contact layer. *** END CLAIM LISTING *** Page 6
canceled
A transistor comprising: a first junction layer coplanar with a second junction layer, the first junction layer and the second junction layer being separated by an insulating trench; a graphene channel layer in contact with at least portions of the first junction layer s and the second junction layer, and in contact with the insulating trench; a gate insulating layer in contact with the graphene channel layer and at least portions of the first junction-layer and the second junction layer; a gate in contact with the gate insulating layer; and a source electrode and a drain electrode on uncovered portions of the first junction layer and the second junction layer, respectively; the source electrode and the drain electrode being connected to the graphene channel layer via the first junction layer and the second junction layer, respectively.
The transistor of claim 15, wherein the insulating trench includes one of air and an insulating material.
The transistor of claim 15, wherein at least one of the first junction layer and the second junction layer comprises silicon.
The transistor of claim 15, wherein the first junction layer and the second junction layer are doped to have a same conduction type.
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET with separated junction contacts (top-gate, bottom-junction configuration)
Materials described outside the worked examples.
graphene
doped semiconductor junction contact layer
silicon
Si
Additional fabrication and treatment steps described in the patent.
Patent
Atlas literature
Patent
US 9,312,368Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view schematically illustrating a structure of a graphene device according to at least one example embodiment; [26]
FIGS. 2A to 2 C are energy band diagrams schematically illustrating an operation of the graphene device of
FIGS. 3A to 3F are cross-sectional views schematically illustrating processes of manufacturing the graphene device of
FIG. 4 is a cross-sectional view schematically illustrating a structure of a graphene device according to another example embodiment; and [29]
FIG. 5 is a flow chart illustrating a method of manufacturing the graphene device, according to at least one example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene device, comprising: a graphene channel layer; a gate electrode configured to apply an electric field to the graphene channel layer; first and second junction contact layers contacting at least portions of the graphene channel layer, [[and l wherein the first and second junction contact layers are electrically and physically separated from each other; and wherein the graphene channel layer is on at least portions of top surfaces of the first junction contact layer and the second junction contact layer, and on a top surface of a separation film, and the second junction contact layer.
The graphene device of claim 1, further comprising a substrate, wherein the first and second junction contact layers are adjacently disposed on at least a portion of a top surface of the substrate.
The graphene device of claim 1, further comprising a gate insulating film on at least portions of the top surfaces of the first junction contact layer and the second junction contact layer and covering the graphene channel layer, wherein the gate electrode is on the gate insulating film opposite to the graphene channel layer.
The graphene device of claim 1, further comprising a substrate including an insulating material, wherein the gate electrode is on the substrate. withdrawn
The graphene device, of claim 1, wherein the separation film is between the first junction contact layer and the second junction contact layer. *** END CLAIM LISTING *** Page 6
canceled
A transistor comprising: a first junction layer coplanar with a second junction layer, the first junction layer and the second junction layer being separated by an insulating trench; a graphene channel layer in contact with at least portions of the first junction layer s and the second junction layer, and in contact with the insulating trench; a gate insulating layer in contact with the graphene channel layer and at least portions of the first junction-layer and the second junction layer; a gate in contact with the gate insulating layer; and a source electrode and a drain electrode on uncovered portions of the first junction layer and the second junction layer, respectively; the source electrode and the drain electrode being connected to the graphene channel layer via the first junction layer and the second junction layer, respectively.
The transistor of claim 15, wherein the insulating trench includes one of air and an insulating material.
The transistor of claim 15, wherein at least one of the first junction layer and the second junction layer comprises silicon.
The transistor of claim 15, wherein the first junction layer and the second junction layer are doped to have a same conduction type.
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET with separated junction contacts (top-gate, bottom-junction configuration)
Materials described outside the worked examples.
graphene
doped semiconductor junction contact layer
silicon
Si
Additional fabrication and treatment steps described in the patent.
graphene FET with separated junction contacts (bottom-gate configuration)
graphene transistor with coplanar junction layers separated by insulating trench
graphene FET with separated junction contacts (bottom-gate configuration)
graphene transistor with coplanar junction layers separated by insulating trench
graphene FET with separated junction contacts (bottom-gate configuration)
graphene transistor with coplanar junction layers separated by insulating trench
graphene FET with separated junction contacts (bottom-gate configuration)
graphene transistor with coplanar junction layers separated by insulating trench