Patent
US 9,831,313METHOD TO THIN DOWN INDIUM PHOSPHIDE LAYER
HAIYANG ZHANG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,831,313Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a flowchart of an exemplary fabrication process consistent with disclosed embodiments; and -3- Attorney Docket No.: 00158.0327. O₀US Cl ent Ref No.: 20 1 5-0029 1 -SH-US [014]
Figures 2 -7 illustrate schematic views of semiconductor structures corresponding to certain stages of another exemplary fabrication method consistent with disclosed embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for thinning down an InP layer formed on a fin structure, comprising: providing a fin structure, wherein the fin structure is made of InGaAs; forming an InP layer to cover the fin structure; converting a surface portion of the InP layer into a Phosphorus-rich layer; and removing the Phosphorus-rich layer, wherein a remaining portion of the InP layer becomes a thinned-down InP layer. Currently amended
The method for thinning down the InP layer according to claim 1, after removing the Phosphorus-rich layer, further including: forming a dielectric layer to cover the thinned-down InP layer; and forming a gate electrode on the dielectric layer. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is formed by a dry etching process using an etch gas including C₁ 2 and Ar. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is removed by a dry etching process using HBr as an etch gas. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is removed by a method including: performing an oxygen treatment process on the Phosphorus-rich layer; and removing the oxygen-treated Phosphorus-rich layer by a dry etching process using H₂ as an etch gas. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the process to form a Phosphorus-rich layer and the process to remove the formed Phosphorus-rich layer are repeated at least 2 times. Currently amended
The method for thinning down the InP layer according to claim 1, wherein a thickness of the ultimately thinned-down InP layer is smaller than or equal to 1 nm. Original
-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
Fin-FET with thinned-down InP layer
Materials described outside the worked examples.
InGaAs
InP
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
thinned-down InP layer thickness (claimed upper bound) | 1 | InP |
Phosphorus-rich layer thickness after dry etching (claimed upper bound) | 1 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,831,313Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a flowchart of an exemplary fabrication process consistent with disclosed embodiments; and -3- Attorney Docket No.: 00158.0327. O₀US Cl ent Ref No.: 20 1 5-0029 1 -SH-US [014]
Figures 2 -7 illustrate schematic views of semiconductor structures corresponding to certain stages of another exemplary fabrication method consistent with disclosed embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for thinning down an InP layer formed on a fin structure, comprising: providing a fin structure, wherein the fin structure is made of InGaAs; forming an InP layer to cover the fin structure; converting a surface portion of the InP layer into a Phosphorus-rich layer; and removing the Phosphorus-rich layer, wherein a remaining portion of the InP layer becomes a thinned-down InP layer. Currently amended
The method for thinning down the InP layer according to claim 1, after removing the Phosphorus-rich layer, further including: forming a dielectric layer to cover the thinned-down InP layer; and forming a gate electrode on the dielectric layer. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is formed by a dry etching process using an etch gas including C₁ 2 and Ar. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is removed by a dry etching process using HBr as an etch gas. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is removed by a method including: performing an oxygen treatment process on the Phosphorus-rich layer; and removing the oxygen-treated Phosphorus-rich layer by a dry etching process using H₂ as an etch gas. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the process to form a Phosphorus-rich layer and the process to remove the formed Phosphorus-rich layer are repeated at least 2 times. Currently amended
The method for thinning down the InP layer according to claim 1, wherein a thickness of the ultimately thinned-down InP layer is smaller than or equal to 1 nm. Original
-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
Fin-FET with thinned-down InP layer
Materials described outside the worked examples.
InGaAs
InP
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
thinned-down InP layer thickness (claimed upper bound) | 1 | InP |
Phosphorus-rich layer thickness after dry etching (claimed upper bound) | 1 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,831,313Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a flowchart of an exemplary fabrication process consistent with disclosed embodiments; and -3- Attorney Docket No.: 00158.0327. O₀US Cl ent Ref No.: 20 1 5-0029 1 -SH-US [014]
Figures 2 -7 illustrate schematic views of semiconductor structures corresponding to certain stages of another exemplary fabrication method consistent with disclosed embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for thinning down an InP layer formed on a fin structure, comprising: providing a fin structure, wherein the fin structure is made of InGaAs; forming an InP layer to cover the fin structure; converting a surface portion of the InP layer into a Phosphorus-rich layer; and removing the Phosphorus-rich layer, wherein a remaining portion of the InP layer becomes a thinned-down InP layer. Currently amended
The method for thinning down the InP layer according to claim 1, after removing the Phosphorus-rich layer, further including: forming a dielectric layer to cover the thinned-down InP layer; and forming a gate electrode on the dielectric layer. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is formed by a dry etching process using an etch gas including C₁ 2 and Ar. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is removed by a dry etching process using HBr as an etch gas. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is removed by a method including: performing an oxygen treatment process on the Phosphorus-rich layer; and removing the oxygen-treated Phosphorus-rich layer by a dry etching process using H₂ as an etch gas. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the process to form a Phosphorus-rich layer and the process to remove the formed Phosphorus-rich layer are repeated at least 2 times. Currently amended
The method for thinning down the InP layer according to claim 1, wherein a thickness of the ultimately thinned-down InP layer is smaller than or equal to 1 nm. Original
-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
Fin-FET with thinned-down InP layer
Materials described outside the worked examples.
InGaAs
InP
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
thinned-down InP layer thickness (claimed upper bound) | 1 | InP |
Phosphorus-rich layer thickness after dry etching (claimed upper bound) | 1 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,831,313Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a flowchart of an exemplary fabrication process consistent with disclosed embodiments; and -3- Attorney Docket No.: 00158.0327. O₀US Cl ent Ref No.: 20 1 5-0029 1 -SH-US [014]
Figures 2 -7 illustrate schematic views of semiconductor structures corresponding to certain stages of another exemplary fabrication method consistent with disclosed embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for thinning down an InP layer formed on a fin structure, comprising: providing a fin structure, wherein the fin structure is made of InGaAs; forming an InP layer to cover the fin structure; converting a surface portion of the InP layer into a Phosphorus-rich layer; and removing the Phosphorus-rich layer, wherein a remaining portion of the InP layer becomes a thinned-down InP layer. Currently amended
The method for thinning down the InP layer according to claim 1, after removing the Phosphorus-rich layer, further including: forming a dielectric layer to cover the thinned-down InP layer; and forming a gate electrode on the dielectric layer. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is formed by a dry etching process using an etch gas including C₁ 2 and Ar. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is removed by a dry etching process using HBr as an etch gas. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the Phosphorus-rich layer is removed by a method including: performing an oxygen treatment process on the Phosphorus-rich layer; and removing the oxygen-treated Phosphorus-rich layer by a dry etching process using H₂ as an etch gas. Currently amended
The method for thinning down the InP layer according to claim 1, wherein the process to form a Phosphorus-rich layer and the process to remove the formed Phosphorus-rich layer are repeated at least 2 times. Currently amended
The method for thinning down the InP layer according to claim 1, wherein a thickness of the ultimately thinned-down InP layer is smaller than or equal to 1 nm. Original
-20. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
Fin-FET with thinned-down InP layer
Materials described outside the worked examples.
InGaAs
InP
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
thinned-down InP layer thickness (claimed upper bound) | 1 | InP |
Phosphorus-rich layer thickness after dry etching (claimed upper bound) | 1 |
Related documents with shared materials, methods, properties, or citations.
Phosphorus-rich layer
dielectric layer
Cl₂
Ar
HBr
O₂
H₂
initial InP layer thickness (MOCVD, described embodiment) | 30 | InP |
Temperature | 10–200 °C | — |
Pressure | 5–500 mTorr | — |
— | 100–1000 W | — |
— | 20–1000 W | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 nm | — |
Flow Rate | 10–200 sccm | — |
Flow Rate | 10–500 sccm | — |
Flow Rate | 50–500 sccm | — |
Phosphorus-rich layer
dielectric layer
Cl₂
Ar
HBr
O₂
H₂
initial InP layer thickness (MOCVD, described embodiment) | 30 | InP |
Temperature | 10–200 °C | — |
Pressure | 5–500 mTorr | — |
— | 100–1000 W | — |
— | 20–1000 W | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 nm | — |
Flow Rate | 10–200 sccm | — |
Flow Rate | 10–500 sccm | — |
Flow Rate | 50–500 sccm | — |
Phosphorus-rich layer
dielectric layer
Cl₂
Ar
HBr
O₂
H₂
initial InP layer thickness (MOCVD, described embodiment) | 30 | InP |
Temperature | 10–200 °C | — |
Pressure | 5–500 mTorr | — |
— | 100–1000 W | — |
— | 20–1000 W | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 nm | — |
Flow Rate | 10–200 sccm | — |
Flow Rate | 10–500 sccm | — |
Flow Rate | 50–500 sccm | — |
Phosphorus-rich layer
dielectric layer
Cl₂
Ar
HBr
O₂
H₂
initial InP layer thickness (MOCVD, described embodiment) | 30 | InP |
Temperature | 10–200 °C | — |
Pressure | 5–500 mTorr | — |
— | 100–1000 W | — |
— | 20–1000 W | — |
Thickness | ≤ 1 nm | — |
Thickness | ≥ 1 nm | — |
Flow Rate | 10–200 sccm | — |
Flow Rate | 10–500 sccm | — |
Flow Rate | 50–500 sccm | — |