Patent
US 10,204,860SEMICONDUCTOR DEVICE WITH GRAPHENE ENCAPSULATED METAL AND METHOD THEREFOR
DOUGLAS M. REBER
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,204,860Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates, in cross-sectional form, a semiconductor structure 10 at a stage in processing. Structure 10 includes a substrate 12 having a plurality of …
FIG. 2 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Metal layer 22 is patterned, using, for example, a …
FIG. 3 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A graphene layer 24 is formed such that it …
FIG. 4 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. An ILD 26 is formed over metal portion 22 and ILD …
FIG. 5 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A patterned masking layer 28 is formed over ILD 26 …
FIG. 6 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Opening 30 is extended through ILD 26 and through …
FIG. 7 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A metal layer 32 is formed, such as by blanket …
FIG. 8 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Metal layer 32 is patterned to result in a …
FIG. 9. Although the graphene layer may be formed on only the bottom major surface of a metal interconnect (such as if no additional carbon driving step is …
FIG. 10 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. An ILD 38 is formed over metal portion 32 and ILD …
FIG. 11 illustrates a structure 100 at a stage in processing in which like numerals with structure 10 indicate like elements. Note that in
FIG. 12 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. ARC layer 102 is a carbon layer or a …
FIG. 13 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. An oxide layer 103 is formed over ARC layer 102, …
FIG. 14 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Metal layer 22, graphene 104, ARC layer 102, and …
FIG. 15 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Patterned masking layer 106 is removed. After …
FIG. 16 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Since the graphene is removed from the top and …
FIG. 17 illustrates a semiconductor structure in accordance with one embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
-12. Canceled
Canceled
A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least a bottom major surface of the first metal interconnect such that the first graphene layer is between the first metal interconnect and the first dielectric layer; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; and a second graphene layer on at least one major surface of the second metal interconnect, wherein the first crap hene l aver surrounds the first metal l aver and the second crap hene l aver surrounds the second metal l aver, wherein the first crap hene l aver contacts the second grap hene l aver in the o p enin c. Currently amended
The semiconductor structure of claim 13, wherein the first metal interconnect and second metal interconnect comprise nickel. Original
The semiconductor structure of claim 13, wherein the first graphene layer is on a top major surface of the first metal interconnect, on the bottom major surface of the first metal interconnect, and at least a side surface of the first metal interconnect. Previously presented
The semiconductor structure of claim 13, further comprising: a third metal interconnect with a third graphene layer surrounding the third metal interconnect, wherein the third graphene layer is on the first graphene layer, and wherein the first metal and the third metal are different metals. New
The semiconductor structure of claim 13, wherein the first metal interconnect is one of nickel or aluminum and the third metal interconnect is another one of nickel or aluminum. New
The semiconductor structure of claim 13, wherein the first metal interconnect is one of nickel, aluminum, titanium, or tungsten and the third metal interconnect is another one of nickel, aluminum, titanium, or tungsten. New
A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least one major surface of the first metal interconnect; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; a second graphene layer on at least one major surface of the second metal interconnect; a third dielectric layer over the second metal interconnect and second graphene layer; and a void between the third dielectric layer and a portion of the second metal interconnect which extends to the electrically contact the first metal layer. Previously presented
The semiconductor structure of claim 15 4 3, wherein the first graphene layer surrounds the first metal interconnect and the second graphene layer surrounds the second metal interconnect. Currently amended
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A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least one major surface of the first metal interconnect; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; and a second graphene layer on at least one major surface of the second metal interconnect, wherein the first graphene layer surrounds the first metal interconnect and the second graphene layer surrounds the second metal interconnect; and a third metal interconnect with a third graphene layer surrounding the third metal interconnect, wherein the third graphene layer is on and in physical contact with the first graphene layer, and wherein the first metal and the third metal are different metals. Previously presented
The semiconductor structure of claim 23, wherein the first metal layer is one of nickel, aluminum, titanium, or tungsten and the third metal layer is another one of nickel, aluminum, titanium, or tungsten. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene-encapsulated metal interconnect semiconductor structure (two metal levels, graphene contacts in via)
Materials described outside the worked examples.
graphene
metal interconnect (generic)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,204,860Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates, in cross-sectional form, a semiconductor structure 10 at a stage in processing. Structure 10 includes a substrate 12 having a plurality of …
FIG. 2 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Metal layer 22 is patterned, using, for example, a …
FIG. 3 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A graphene layer 24 is formed such that it …
FIG. 4 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. An ILD 26 is formed over metal portion 22 and ILD …
FIG. 5 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A patterned masking layer 28 is formed over ILD 26 …
FIG. 6 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Opening 30 is extended through ILD 26 and through …
FIG. 7 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A metal layer 32 is formed, such as by blanket …
FIG. 8 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Metal layer 32 is patterned to result in a …
FIG. 9. Although the graphene layer may be formed on only the bottom major surface of a metal interconnect (such as if no additional carbon driving step is …
FIG. 10 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. An ILD 38 is formed over metal portion 32 and ILD …
FIG. 11 illustrates a structure 100 at a stage in processing in which like numerals with structure 10 indicate like elements. Note that in
FIG. 12 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. ARC layer 102 is a carbon layer or a …
FIG. 13 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. An oxide layer 103 is formed over ARC layer 102, …
FIG. 14 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Metal layer 22, graphene 104, ARC layer 102, and …
FIG. 15 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Patterned masking layer 106 is removed. After …
FIG. 16 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Since the graphene is removed from the top and …
FIG. 17 illustrates a semiconductor structure in accordance with one embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
-12. Canceled
Canceled
A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least a bottom major surface of the first metal interconnect such that the first graphene layer is between the first metal interconnect and the first dielectric layer; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; and a second graphene layer on at least one major surface of the second metal interconnect, wherein the first crap hene l aver surrounds the first metal l aver and the second crap hene l aver surrounds the second metal l aver, wherein the first crap hene l aver contacts the second grap hene l aver in the o p enin c. Currently amended
The semiconductor structure of claim 13, wherein the first metal interconnect and second metal interconnect comprise nickel. Original
The semiconductor structure of claim 13, wherein the first graphene layer is on a top major surface of the first metal interconnect, on the bottom major surface of the first metal interconnect, and at least a side surface of the first metal interconnect. Previously presented
The semiconductor structure of claim 13, further comprising: a third metal interconnect with a third graphene layer surrounding the third metal interconnect, wherein the third graphene layer is on the first graphene layer, and wherein the first metal and the third metal are different metals. New
The semiconductor structure of claim 13, wherein the first metal interconnect is one of nickel or aluminum and the third metal interconnect is another one of nickel or aluminum. New
The semiconductor structure of claim 13, wherein the first metal interconnect is one of nickel, aluminum, titanium, or tungsten and the third metal interconnect is another one of nickel, aluminum, titanium, or tungsten. New
A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least one major surface of the first metal interconnect; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; a second graphene layer on at least one major surface of the second metal interconnect; a third dielectric layer over the second metal interconnect and second graphene layer; and a void between the third dielectric layer and a portion of the second metal interconnect which extends to the electrically contact the first metal layer. Previously presented
The semiconductor structure of claim 15 4 3, wherein the first graphene layer surrounds the first metal interconnect and the second graphene layer surrounds the second metal interconnect. Currently amended
(Cancel) Canceled
(Cancel) Canceled
(Cancel) Canceled
A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least one major surface of the first metal interconnect; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; and a second graphene layer on at least one major surface of the second metal interconnect, wherein the first graphene layer surrounds the first metal interconnect and the second graphene layer surrounds the second metal interconnect; and a third metal interconnect with a third graphene layer surrounding the third metal interconnect, wherein the third graphene layer is on and in physical contact with the first graphene layer, and wherein the first metal and the third metal are different metals. Previously presented
The semiconductor structure of claim 23, wherein the first metal layer is one of nickel, aluminum, titanium, or tungsten and the third metal layer is another one of nickel, aluminum, titanium, or tungsten. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene-encapsulated metal interconnect semiconductor structure (two metal levels, graphene contacts in via)
Materials described outside the worked examples.
graphene
metal interconnect (generic)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,204,860Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates, in cross-sectional form, a semiconductor structure 10 at a stage in processing. Structure 10 includes a substrate 12 having a plurality of …
FIG. 2 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Metal layer 22 is patterned, using, for example, a …
FIG. 3 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A graphene layer 24 is formed such that it …
FIG. 4 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. An ILD 26 is formed over metal portion 22 and ILD …
FIG. 5 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A patterned masking layer 28 is formed over ILD 26 …
FIG. 6 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Opening 30 is extended through ILD 26 and through …
FIG. 7 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A metal layer 32 is formed, such as by blanket …
FIG. 8 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Metal layer 32 is patterned to result in a …
FIG. 9. Although the graphene layer may be formed on only the bottom major surface of a metal interconnect (such as if no additional carbon driving step is …
FIG. 10 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. An ILD 38 is formed over metal portion 32 and ILD …
FIG. 11 illustrates a structure 100 at a stage in processing in which like numerals with structure 10 indicate like elements. Note that in
FIG. 12 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. ARC layer 102 is a carbon layer or a …
FIG. 13 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. An oxide layer 103 is formed over ARC layer 102, …
FIG. 14 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Metal layer 22, graphene 104, ARC layer 102, and …
FIG. 15 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Patterned masking layer 106 is removed. After …
FIG. 16 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Since the graphene is removed from the top and …
FIG. 17 illustrates a semiconductor structure in accordance with one embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
-12. Canceled
Canceled
A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least a bottom major surface of the first metal interconnect such that the first graphene layer is between the first metal interconnect and the first dielectric layer; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; and a second graphene layer on at least one major surface of the second metal interconnect, wherein the first crap hene l aver surrounds the first metal l aver and the second crap hene l aver surrounds the second metal l aver, wherein the first crap hene l aver contacts the second grap hene l aver in the o p enin c. Currently amended
The semiconductor structure of claim 13, wherein the first metal interconnect and second metal interconnect comprise nickel. Original
The semiconductor structure of claim 13, wherein the first graphene layer is on a top major surface of the first metal interconnect, on the bottom major surface of the first metal interconnect, and at least a side surface of the first metal interconnect. Previously presented
The semiconductor structure of claim 13, further comprising: a third metal interconnect with a third graphene layer surrounding the third metal interconnect, wherein the third graphene layer is on the first graphene layer, and wherein the first metal and the third metal are different metals. New
The semiconductor structure of claim 13, wherein the first metal interconnect is one of nickel or aluminum and the third metal interconnect is another one of nickel or aluminum. New
The semiconductor structure of claim 13, wherein the first metal interconnect is one of nickel, aluminum, titanium, or tungsten and the third metal interconnect is another one of nickel, aluminum, titanium, or tungsten. New
A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least one major surface of the first metal interconnect; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; a second graphene layer on at least one major surface of the second metal interconnect; a third dielectric layer over the second metal interconnect and second graphene layer; and a void between the third dielectric layer and a portion of the second metal interconnect which extends to the electrically contact the first metal layer. Previously presented
The semiconductor structure of claim 15 4 3, wherein the first graphene layer surrounds the first metal interconnect and the second graphene layer surrounds the second metal interconnect. Currently amended
(Cancel) Canceled
(Cancel) Canceled
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A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least one major surface of the first metal interconnect; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; and a second graphene layer on at least one major surface of the second metal interconnect, wherein the first graphene layer surrounds the first metal interconnect and the second graphene layer surrounds the second metal interconnect; and a third metal interconnect with a third graphene layer surrounding the third metal interconnect, wherein the third graphene layer is on and in physical contact with the first graphene layer, and wherein the first metal and the third metal are different metals. Previously presented
The semiconductor structure of claim 23, wherein the first metal layer is one of nickel, aluminum, titanium, or tungsten and the third metal layer is another one of nickel, aluminum, titanium, or tungsten. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene-encapsulated metal interconnect semiconductor structure (two metal levels, graphene contacts in via)
Materials described outside the worked examples.
graphene
metal interconnect (generic)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,204,860Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates, in cross-sectional form, a semiconductor structure 10 at a stage in processing. Structure 10 includes a substrate 12 having a plurality of …
FIG. 2 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Metal layer 22 is patterned, using, for example, a …
FIG. 3 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A graphene layer 24 is formed such that it …
FIG. 4 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. An ILD 26 is formed over metal portion 22 and ILD …
FIG. 5 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A patterned masking layer 28 is formed over ILD 26 …
FIG. 6 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Opening 30 is extended through ILD 26 and through …
FIG. 7 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. A metal layer 32 is formed, such as by blanket …
FIG. 8 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. Metal layer 32 is patterned to result in a …
FIG. 9. Although the graphene layer may be formed on only the bottom major surface of a metal interconnect (such as if no additional carbon driving step is …
FIG. 10 illustrates, in cross-sectional form, semiconductor structure 10 at a subsequent stage in processing. An ILD 38 is formed over metal portion 32 and ILD …
FIG. 11 illustrates a structure 100 at a stage in processing in which like numerals with structure 10 indicate like elements. Note that in
FIG. 12 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. ARC layer 102 is a carbon layer or a …
FIG. 13 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. An oxide layer 103 is formed over ARC layer 102, …
FIG. 14 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Metal layer 22, graphene 104, ARC layer 102, and …
FIG. 15 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Patterned masking layer 106 is removed. After …
FIG. 16 illustrates, in cross-sectional form, semiconductor structure 100 at a subsequent stage in processing. Since the graphene is removed from the top and …
FIG. 17 illustrates a semiconductor structure in accordance with one embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
-12. Canceled
Canceled
A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least a bottom major surface of the first metal interconnect such that the first graphene layer is between the first metal interconnect and the first dielectric layer; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; and a second graphene layer on at least one major surface of the second metal interconnect, wherein the first crap hene l aver surrounds the first metal l aver and the second crap hene l aver surrounds the second metal l aver, wherein the first crap hene l aver contacts the second grap hene l aver in the o p enin c. Currently amended
The semiconductor structure of claim 13, wherein the first metal interconnect and second metal interconnect comprise nickel. Original
The semiconductor structure of claim 13, wherein the first graphene layer is on a top major surface of the first metal interconnect, on the bottom major surface of the first metal interconnect, and at least a side surface of the first metal interconnect. Previously presented
The semiconductor structure of claim 13, further comprising: a third metal interconnect with a third graphene layer surrounding the third metal interconnect, wherein the third graphene layer is on the first graphene layer, and wherein the first metal and the third metal are different metals. New
The semiconductor structure of claim 13, wherein the first metal interconnect is one of nickel or aluminum and the third metal interconnect is another one of nickel or aluminum. New
The semiconductor structure of claim 13, wherein the first metal interconnect is one of nickel, aluminum, titanium, or tungsten and the third metal interconnect is another one of nickel, aluminum, titanium, or tungsten. New
A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least one major surface of the first metal interconnect; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; a second graphene layer on at least one major surface of the second metal interconnect; a third dielectric layer over the second metal interconnect and second graphene layer; and a void between the third dielectric layer and a portion of the second metal interconnect which extends to the electrically contact the first metal layer. Previously presented
The semiconductor structure of claim 15 4 3, wherein the first graphene layer surrounds the first metal interconnect and the second graphene layer surrounds the second metal interconnect. Currently amended
(Cancel) Canceled
(Cancel) Canceled
(Cancel) Canceled
A semiconductor structure comprising: a first metal interconnect over a first dielectric layer; a first graphene layer on at least one major surface of the first metal interconnect; a second dielectric layer over the graphene layer and the first metal interconnect; a second metal interconnect over the second dielectric layer and extending through the second dielectric layer to electrically contact the first metal interconnect; and a second graphene layer on at least one major surface of the second metal interconnect, wherein the first graphene layer surrounds the first metal interconnect and the second graphene layer surrounds the second metal interconnect; and a third metal interconnect with a third graphene layer surrounding the third metal interconnect, wherein the third graphene layer is on and in physical contact with the first graphene layer, and wherein the first metal and the third metal are different metals. Previously presented
The semiconductor structure of claim 23, wherein the first metal layer is one of nickel, aluminum, titanium, or tungsten and the third metal layer is another one of nickel, aluminum, titanium, or tungsten. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
graphene-encapsulated metal interconnect semiconductor structure (two metal levels, graphene contacts in via)
Materials described outside the worked examples.
graphene
metal interconnect (generic)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
graphene-encapsulated metal interconnect semiconductor structure with void in via (three dielectric levels)
graphene-encapsulated multi-metal interconnect semiconductor structure (three metal interconnects, different metals)
dielectric layer (generic)
nickel
Ni
third metal interconnect (different from first)
aluminum
Al
titanium
Ti
tungsten
W
silicon dioxide
SiO₂
low-k dielectric
acetylene
C₂H₂
methane
CH₄
amorphous carbon anti-reflective coating (ARC) layer
TEOS oxide
carbon-containing paste
graphene-encapsulated metal interconnect semiconductor structure with void in via (three dielectric levels)
graphene-encapsulated multi-metal interconnect semiconductor structure (three metal interconnects, different metals)
dielectric layer (generic)
nickel
Ni
third metal interconnect (different from first)
aluminum
Al
titanium
Ti
tungsten
W
silicon dioxide
SiO₂
low-k dielectric
acetylene
C₂H₂
methane
CH₄
amorphous carbon anti-reflective coating (ARC) layer
TEOS oxide
carbon-containing paste
graphene-encapsulated metal interconnect semiconductor structure with void in via (three dielectric levels)
graphene-encapsulated multi-metal interconnect semiconductor structure (three metal interconnects, different metals)
dielectric layer (generic)
nickel
Ni
third metal interconnect (different from first)
aluminum
Al
titanium
Ti
tungsten
W
silicon dioxide
SiO₂
low-k dielectric
acetylene
C₂H₂
methane
CH₄
amorphous carbon anti-reflective coating (ARC) layer
TEOS oxide
carbon-containing paste
graphene-encapsulated metal interconnect semiconductor structure with void in via (three dielectric levels)
graphene-encapsulated multi-metal interconnect semiconductor structure (three metal interconnects, different metals)
dielectric layer (generic)
nickel
Ni
third metal interconnect (different from first)
aluminum
Al
titanium
Ti
tungsten
W
silicon dioxide
SiO₂
low-k dielectric
acetylene
C₂H₂
methane
CH₄
amorphous carbon anti-reflective coating (ARC) layer
TEOS oxide
carbon-containing paste