Patent
US 11,205,617INTERCONNECT STRUCTURE HAVING A GRAPHENE LAYER
Ming Zhou
Semiconductor Manufacturing International (Shanghai) Corporation·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,205,617Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flowchart illustrating a method for manufacturing an interconnect structure according to one embodiment of the present invention. The method may …
FIGS. 2A through 2F are cross-sectional views illustrating intermediate stages of an interconnect structure according to one embodiment of the present …
FIG. 3H. In an example embodiment, second through- hole 330 may include tantalum nitride and tantalum. [0090] Next, referring to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An interconnect structure comprising: a substrate; a first dielectric layer comprising a first silicon carbon nitride (SiCN) layer directly on the substrate, a first silicon dioxide layer directly on the first SiCN layer, and a first hydrogenated silicon-carbide (SiOCH) layer directly on the first silicon dioxide layer; a first metal interconnect layer in the first dielectric layer and in contact with the substrate, the first metal interconnect layer having an upper surface flush with an upper surface of the first dielectric layer; a first barrier layer disposed between the first dielectric layer and the first metal interconnect layer and between a bottom of the first metal interconnect layer and the substrate, the first barrier layer having an upper surface flush with the upper surface of the first dielectric layer, wherein the first metal interconnect layer and the first barrier layer go through sequentially the first hydrogenated silicon-carbide (SiOCH) layer, the first silicon dioxide layer, and the first SiCN layer; a second dielectric layer on the first dielectric layer; a second metal interconnect layer in the second dielectric layer and in contact with the first metal interconnect layer; a second barrier layer disposed between the first metal interconnect layer and the second metal interconnect layer and comprising a bottom in direct contact with the first metal interconnect layer and the first barrier layer; a graphene layer on the second metal interconnect layer and directly contacting an upper surface of the second barrier layer; and an amorphous carbon layer on the second dielectric layer and having an upper surface flush with an upper surface of the graphene layer, wherein the amorphous carbon layer is not in contact with the second barrier layer, and an interface surface between the graphene layer and the amorphous carbon layer is aligned an interface surface between the second barrier layer and the second dielectric layer. Currently amended
The interconnect structure of claim 1, wherein the amorphous carbon layer is adjacent to the graphene layer. Previously presented
The interconnect structure of claim 1, wherein: the substrate comprises a semiconductor substrate; and the second dielectric layer comprises a second silicon carbon nitride (SiCN) layer. Previously presented
The interconnect structure of claim 1, wherein the upper surface of the second barrier layer is flush with an upper surface of the second dielectric layer. Previously presented
The interconnect structure of claim 1, wherein the graphene layer comprises 1 to 30 layers of graphene monoatomic layers. Original
The interconnect structure of claim 1, wherein the second metal interconnect layer comprises a damascene structure. Previously presented
The interconnect structure of claim 1, wherein: the second barrier layer comprises tantalum nitride and tantalum; and the second metal interconnect layer comprises copper. Previously presented
The interconnect structure of claim 1, wherein: the second barrier layer is formed directly on the first barrier layer and the first metal interconnect layer and covers completely a top surface of the first metal interconnect layer, and a size of a bottom of the second barrier layer is smaller than a size of a bottom of the first barrier layer. Currently amended
Canceled
An interconnect structure comprising: a substrate; a dielectric layer comprising a silicon carbon nitride layer (SiCN) directly on the substrate, a silicon dioxide layer directly on the silicon carbon nitride layer, and a hydrogenated silicon-carbide layer (SiOCH) directly on the silicon dioxide layer; a metal interconnect layer in the dielectric layer and having an upper surface flush with an upper surface of the dielectric layer; a barrier layer disposed between the dielectric layer and the metal interconnect layer and between the metal interconnect layer and the substrate, the barrier layer having an upper surface flush with the upper surface of the dielectric layer, wherein th metal interconnect layer and th barrier layer go through sequentially the hydrogenated silicon-carbide layer(SiOCH), the silicon dioxide layer, and the silicon carbon nitride layer (SiCN); a graphene layer on the metal interconnect layer and directly contacting the upper surface of the barrier layer; and an amorphous carbon layer on the dielectric layer and having an upper surface flush with an upper surface of the graphene layer, wherein the amorphous carbon layer is not in contact with the barrier layer, and an interface surface between the graphene layer and the amorphous carbon layer is aligned an interface surface between the second barrier layer and the second dielectric la y er. Currently amended
The interconnect structure of claim 13, wherein the amorphous carbon layer is adjacent to the graphene layer. Previously presented
The interconnect structure of claim 13, wherein: the substrate comprises a semiconductor substrate; the dielectric layer further comprises a first dielectric layer on the semiconductor substrate; and the metal interconnect layer comprises a first metal interconnect layer formed in the first dielectric layer and having a bottom in contact with the barrier layer. Previously presented
The interconnect structure of claim 13, wherein the graphene layer comprises 1 to 30 layers of graphene monoatomic layers. Previously presented
The interconnect structure of claim 13, wherein the metal interconnect layer comprises a damascene structure. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
interconnect structure with two metal layers and graphene capping (claim 1)
Materials described outside the worked examples.
silicon carbon nitride (SiCN)
SiCN
silicon dioxide
SiO₂
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,205,617Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flowchart illustrating a method for manufacturing an interconnect structure according to one embodiment of the present invention. The method may …
FIGS. 2A through 2F are cross-sectional views illustrating intermediate stages of an interconnect structure according to one embodiment of the present …
FIG. 3H. In an example embodiment, second through- hole 330 may include tantalum nitride and tantalum. [0090] Next, referring to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An interconnect structure comprising: a substrate; a first dielectric layer comprising a first silicon carbon nitride (SiCN) layer directly on the substrate, a first silicon dioxide layer directly on the first SiCN layer, and a first hydrogenated silicon-carbide (SiOCH) layer directly on the first silicon dioxide layer; a first metal interconnect layer in the first dielectric layer and in contact with the substrate, the first metal interconnect layer having an upper surface flush with an upper surface of the first dielectric layer; a first barrier layer disposed between the first dielectric layer and the first metal interconnect layer and between a bottom of the first metal interconnect layer and the substrate, the first barrier layer having an upper surface flush with the upper surface of the first dielectric layer, wherein the first metal interconnect layer and the first barrier layer go through sequentially the first hydrogenated silicon-carbide (SiOCH) layer, the first silicon dioxide layer, and the first SiCN layer; a second dielectric layer on the first dielectric layer; a second metal interconnect layer in the second dielectric layer and in contact with the first metal interconnect layer; a second barrier layer disposed between the first metal interconnect layer and the second metal interconnect layer and comprising a bottom in direct contact with the first metal interconnect layer and the first barrier layer; a graphene layer on the second metal interconnect layer and directly contacting an upper surface of the second barrier layer; and an amorphous carbon layer on the second dielectric layer and having an upper surface flush with an upper surface of the graphene layer, wherein the amorphous carbon layer is not in contact with the second barrier layer, and an interface surface between the graphene layer and the amorphous carbon layer is aligned an interface surface between the second barrier layer and the second dielectric layer. Currently amended
The interconnect structure of claim 1, wherein the amorphous carbon layer is adjacent to the graphene layer. Previously presented
The interconnect structure of claim 1, wherein: the substrate comprises a semiconductor substrate; and the second dielectric layer comprises a second silicon carbon nitride (SiCN) layer. Previously presented
The interconnect structure of claim 1, wherein the upper surface of the second barrier layer is flush with an upper surface of the second dielectric layer. Previously presented
The interconnect structure of claim 1, wherein the graphene layer comprises 1 to 30 layers of graphene monoatomic layers. Original
The interconnect structure of claim 1, wherein the second metal interconnect layer comprises a damascene structure. Previously presented
The interconnect structure of claim 1, wherein: the second barrier layer comprises tantalum nitride and tantalum; and the second metal interconnect layer comprises copper. Previously presented
The interconnect structure of claim 1, wherein: the second barrier layer is formed directly on the first barrier layer and the first metal interconnect layer and covers completely a top surface of the first metal interconnect layer, and a size of a bottom of the second barrier layer is smaller than a size of a bottom of the first barrier layer. Currently amended
Canceled
An interconnect structure comprising: a substrate; a dielectric layer comprising a silicon carbon nitride layer (SiCN) directly on the substrate, a silicon dioxide layer directly on the silicon carbon nitride layer, and a hydrogenated silicon-carbide layer (SiOCH) directly on the silicon dioxide layer; a metal interconnect layer in the dielectric layer and having an upper surface flush with an upper surface of the dielectric layer; a barrier layer disposed between the dielectric layer and the metal interconnect layer and between the metal interconnect layer and the substrate, the barrier layer having an upper surface flush with the upper surface of the dielectric layer, wherein th metal interconnect layer and th barrier layer go through sequentially the hydrogenated silicon-carbide layer(SiOCH), the silicon dioxide layer, and the silicon carbon nitride layer (SiCN); a graphene layer on the metal interconnect layer and directly contacting the upper surface of the barrier layer; and an amorphous carbon layer on the dielectric layer and having an upper surface flush with an upper surface of the graphene layer, wherein the amorphous carbon layer is not in contact with the barrier layer, and an interface surface between the graphene layer and the amorphous carbon layer is aligned an interface surface between the second barrier layer and the second dielectric la y er. Currently amended
The interconnect structure of claim 13, wherein the amorphous carbon layer is adjacent to the graphene layer. Previously presented
The interconnect structure of claim 13, wherein: the substrate comprises a semiconductor substrate; the dielectric layer further comprises a first dielectric layer on the semiconductor substrate; and the metal interconnect layer comprises a first metal interconnect layer formed in the first dielectric layer and having a bottom in contact with the barrier layer. Previously presented
The interconnect structure of claim 13, wherein the graphene layer comprises 1 to 30 layers of graphene monoatomic layers. Previously presented
The interconnect structure of claim 13, wherein the metal interconnect layer comprises a damascene structure. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
interconnect structure with two metal layers and graphene capping (claim 1)
Materials described outside the worked examples.
silicon carbon nitride (SiCN)
SiCN
silicon dioxide
SiO₂
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,205,617Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flowchart illustrating a method for manufacturing an interconnect structure according to one embodiment of the present invention. The method may …
FIGS. 2A through 2F are cross-sectional views illustrating intermediate stages of an interconnect structure according to one embodiment of the present …
FIG. 3H. In an example embodiment, second through- hole 330 may include tantalum nitride and tantalum. [0090] Next, referring to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An interconnect structure comprising: a substrate; a first dielectric layer comprising a first silicon carbon nitride (SiCN) layer directly on the substrate, a first silicon dioxide layer directly on the first SiCN layer, and a first hydrogenated silicon-carbide (SiOCH) layer directly on the first silicon dioxide layer; a first metal interconnect layer in the first dielectric layer and in contact with the substrate, the first metal interconnect layer having an upper surface flush with an upper surface of the first dielectric layer; a first barrier layer disposed between the first dielectric layer and the first metal interconnect layer and between a bottom of the first metal interconnect layer and the substrate, the first barrier layer having an upper surface flush with the upper surface of the first dielectric layer, wherein the first metal interconnect layer and the first barrier layer go through sequentially the first hydrogenated silicon-carbide (SiOCH) layer, the first silicon dioxide layer, and the first SiCN layer; a second dielectric layer on the first dielectric layer; a second metal interconnect layer in the second dielectric layer and in contact with the first metal interconnect layer; a second barrier layer disposed between the first metal interconnect layer and the second metal interconnect layer and comprising a bottom in direct contact with the first metal interconnect layer and the first barrier layer; a graphene layer on the second metal interconnect layer and directly contacting an upper surface of the second barrier layer; and an amorphous carbon layer on the second dielectric layer and having an upper surface flush with an upper surface of the graphene layer, wherein the amorphous carbon layer is not in contact with the second barrier layer, and an interface surface between the graphene layer and the amorphous carbon layer is aligned an interface surface between the second barrier layer and the second dielectric layer. Currently amended
The interconnect structure of claim 1, wherein the amorphous carbon layer is adjacent to the graphene layer. Previously presented
The interconnect structure of claim 1, wherein: the substrate comprises a semiconductor substrate; and the second dielectric layer comprises a second silicon carbon nitride (SiCN) layer. Previously presented
The interconnect structure of claim 1, wherein the upper surface of the second barrier layer is flush with an upper surface of the second dielectric layer. Previously presented
The interconnect structure of claim 1, wherein the graphene layer comprises 1 to 30 layers of graphene monoatomic layers. Original
The interconnect structure of claim 1, wherein the second metal interconnect layer comprises a damascene structure. Previously presented
The interconnect structure of claim 1, wherein: the second barrier layer comprises tantalum nitride and tantalum; and the second metal interconnect layer comprises copper. Previously presented
The interconnect structure of claim 1, wherein: the second barrier layer is formed directly on the first barrier layer and the first metal interconnect layer and covers completely a top surface of the first metal interconnect layer, and a size of a bottom of the second barrier layer is smaller than a size of a bottom of the first barrier layer. Currently amended
Canceled
An interconnect structure comprising: a substrate; a dielectric layer comprising a silicon carbon nitride layer (SiCN) directly on the substrate, a silicon dioxide layer directly on the silicon carbon nitride layer, and a hydrogenated silicon-carbide layer (SiOCH) directly on the silicon dioxide layer; a metal interconnect layer in the dielectric layer and having an upper surface flush with an upper surface of the dielectric layer; a barrier layer disposed between the dielectric layer and the metal interconnect layer and between the metal interconnect layer and the substrate, the barrier layer having an upper surface flush with the upper surface of the dielectric layer, wherein th metal interconnect layer and th barrier layer go through sequentially the hydrogenated silicon-carbide layer(SiOCH), the silicon dioxide layer, and the silicon carbon nitride layer (SiCN); a graphene layer on the metal interconnect layer and directly contacting the upper surface of the barrier layer; and an amorphous carbon layer on the dielectric layer and having an upper surface flush with an upper surface of the graphene layer, wherein the amorphous carbon layer is not in contact with the barrier layer, and an interface surface between the graphene layer and the amorphous carbon layer is aligned an interface surface between the second barrier layer and the second dielectric la y er. Currently amended
The interconnect structure of claim 13, wherein the amorphous carbon layer is adjacent to the graphene layer. Previously presented
The interconnect structure of claim 13, wherein: the substrate comprises a semiconductor substrate; the dielectric layer further comprises a first dielectric layer on the semiconductor substrate; and the metal interconnect layer comprises a first metal interconnect layer formed in the first dielectric layer and having a bottom in contact with the barrier layer. Previously presented
The interconnect structure of claim 13, wherein the graphene layer comprises 1 to 30 layers of graphene monoatomic layers. Previously presented
The interconnect structure of claim 13, wherein the metal interconnect layer comprises a damascene structure. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
interconnect structure with two metal layers and graphene capping (claim 1)
Materials described outside the worked examples.
silicon carbon nitride (SiCN)
SiCN
silicon dioxide
SiO₂
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,205,617Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flowchart illustrating a method for manufacturing an interconnect structure according to one embodiment of the present invention. The method may …
FIGS. 2A through 2F are cross-sectional views illustrating intermediate stages of an interconnect structure according to one embodiment of the present …
FIG. 3H. In an example embodiment, second through- hole 330 may include tantalum nitride and tantalum. [0090] Next, referring to
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An interconnect structure comprising: a substrate; a first dielectric layer comprising a first silicon carbon nitride (SiCN) layer directly on the substrate, a first silicon dioxide layer directly on the first SiCN layer, and a first hydrogenated silicon-carbide (SiOCH) layer directly on the first silicon dioxide layer; a first metal interconnect layer in the first dielectric layer and in contact with the substrate, the first metal interconnect layer having an upper surface flush with an upper surface of the first dielectric layer; a first barrier layer disposed between the first dielectric layer and the first metal interconnect layer and between a bottom of the first metal interconnect layer and the substrate, the first barrier layer having an upper surface flush with the upper surface of the first dielectric layer, wherein the first metal interconnect layer and the first barrier layer go through sequentially the first hydrogenated silicon-carbide (SiOCH) layer, the first silicon dioxide layer, and the first SiCN layer; a second dielectric layer on the first dielectric layer; a second metal interconnect layer in the second dielectric layer and in contact with the first metal interconnect layer; a second barrier layer disposed between the first metal interconnect layer and the second metal interconnect layer and comprising a bottom in direct contact with the first metal interconnect layer and the first barrier layer; a graphene layer on the second metal interconnect layer and directly contacting an upper surface of the second barrier layer; and an amorphous carbon layer on the second dielectric layer and having an upper surface flush with an upper surface of the graphene layer, wherein the amorphous carbon layer is not in contact with the second barrier layer, and an interface surface between the graphene layer and the amorphous carbon layer is aligned an interface surface between the second barrier layer and the second dielectric layer. Currently amended
The interconnect structure of claim 1, wherein the amorphous carbon layer is adjacent to the graphene layer. Previously presented
The interconnect structure of claim 1, wherein: the substrate comprises a semiconductor substrate; and the second dielectric layer comprises a second silicon carbon nitride (SiCN) layer. Previously presented
The interconnect structure of claim 1, wherein the upper surface of the second barrier layer is flush with an upper surface of the second dielectric layer. Previously presented
The interconnect structure of claim 1, wherein the graphene layer comprises 1 to 30 layers of graphene monoatomic layers. Original
The interconnect structure of claim 1, wherein the second metal interconnect layer comprises a damascene structure. Previously presented
The interconnect structure of claim 1, wherein: the second barrier layer comprises tantalum nitride and tantalum; and the second metal interconnect layer comprises copper. Previously presented
The interconnect structure of claim 1, wherein: the second barrier layer is formed directly on the first barrier layer and the first metal interconnect layer and covers completely a top surface of the first metal interconnect layer, and a size of a bottom of the second barrier layer is smaller than a size of a bottom of the first barrier layer. Currently amended
Canceled
An interconnect structure comprising: a substrate; a dielectric layer comprising a silicon carbon nitride layer (SiCN) directly on the substrate, a silicon dioxide layer directly on the silicon carbon nitride layer, and a hydrogenated silicon-carbide layer (SiOCH) directly on the silicon dioxide layer; a metal interconnect layer in the dielectric layer and having an upper surface flush with an upper surface of the dielectric layer; a barrier layer disposed between the dielectric layer and the metal interconnect layer and between the metal interconnect layer and the substrate, the barrier layer having an upper surface flush with the upper surface of the dielectric layer, wherein th metal interconnect layer and th barrier layer go through sequentially the hydrogenated silicon-carbide layer(SiOCH), the silicon dioxide layer, and the silicon carbon nitride layer (SiCN); a graphene layer on the metal interconnect layer and directly contacting the upper surface of the barrier layer; and an amorphous carbon layer on the dielectric layer and having an upper surface flush with an upper surface of the graphene layer, wherein the amorphous carbon layer is not in contact with the barrier layer, and an interface surface between the graphene layer and the amorphous carbon layer is aligned an interface surface between the second barrier layer and the second dielectric la y er. Currently amended
The interconnect structure of claim 13, wherein the amorphous carbon layer is adjacent to the graphene layer. Previously presented
The interconnect structure of claim 13, wherein: the substrate comprises a semiconductor substrate; the dielectric layer further comprises a first dielectric layer on the semiconductor substrate; and the metal interconnect layer comprises a first metal interconnect layer formed in the first dielectric layer and having a bottom in contact with the barrier layer. Previously presented
The interconnect structure of claim 13, wherein the graphene layer comprises 1 to 30 layers of graphene monoatomic layers. Previously presented
The interconnect structure of claim 13, wherein the metal interconnect layer comprises a damascene structure. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
interconnect structure with two metal layers and graphene capping (claim 1)
Materials described outside the worked examples.
silicon carbon nitride (SiCN)
SiCN
silicon dioxide
SiO₂
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
interconnect structure with single metal layer and graphene capping (claim 13)
hydrogenated silicon-carbide (SiOCH)
SiOCH
tantalum nitride and tantalum
graphene
C
amorphous carbon
copper
Cu
methane
CH₄
nitrogen or hydrogen carrier gas
interconnect structure with single metal layer and graphene capping (claim 13)
hydrogenated silicon-carbide (SiOCH)
SiOCH
tantalum nitride and tantalum
graphene
C
amorphous carbon
copper
Cu
methane
CH₄
nitrogen or hydrogen carrier gas
interconnect structure with single metal layer and graphene capping (claim 13)
hydrogenated silicon-carbide (SiOCH)
SiOCH
tantalum nitride and tantalum
graphene
C
amorphous carbon
copper
Cu
methane
CH₄
nitrogen or hydrogen carrier gas
interconnect structure with single metal layer and graphene capping (claim 13)
hydrogenated silicon-carbide (SiOCH)
SiOCH
tantalum nitride and tantalum
graphene
C
amorphous carbon
copper
Cu
methane
CH₄
nitrogen or hydrogen carrier gas