Patent
US 12,176,887 B2TRANSFORMER-BASED DRIVE FOR GaN DEVICES
Derek Bernardon, Thomas Ferianz, Kennith Kin Leong
Infineon Technologies Austria AG, Villach (AT)·Dec. 24, 2024·US
Copyright © 2026 Matter42. All rights reserved.
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US 12,176,887 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a circuit schematic of an embodiment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 2 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 3 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 4 illustrates a cross-sectional view of an embodiment of a depletion mode GaN device for use in any of the power stages shown in
FIG. 5 illustrates a cross-sectional view of an embodiment of an enhancement mode GaN device for use in any of the power stages shown in
FIG. 6 illustrates a dual-coil transformer embodiment for the transformers in
FIG. 7 illustrates a single-coil transformer embodiment for the transformers in
FIG. 8 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power stage, comprising: a first transformer; a second transformer; a third transformer; a GaN (gallium nitride) enhancement mode power tran-sistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer; and a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer.
The power stage of claim 1, wherein a primary winding of the second transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the second transformer has a center tap that is coupled to the source of the GaN depletion mode transistor and to a source of the GaN enhancement mode transistor.
The power stage of claim 1, wherein a primary winding of the third transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the third transformer has a center tap that is coupled to the gate of the GaN depletion mode transistor and to a drain of the GaN enhancement mode transistor.
The power stage of claim 1, wherein a primary winding of the second transformer has a center tap that is grounded or disconnected, wherein a secondary winding of the second transformer has a center tap that is coupled to the source of the GaN depletion mode transistor and to a source of the GaN enhancement mode transistor, wherein a primary wind-ing of the third transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the third transformer has a center tap that is coupled to the gate of the GaN depletion mode transistor and to a drain of the GaN enhancement mode transistor.
The power stage of claim 1, wherein the voltage clamping device or circuit comprises a Zener diode having an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically con-nected to the source of the GaN depletion mode transistor.
The power stage of claim 1, wherein the voltage clamping device or circuit comprises a GaN-gated diode having an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically connected to the source of the GaN depletion mode transis-tor.
The power stage of claim 1, wherein a primary winding of the second transformer comprises a single coil, and wherein a secondary winding of the second transformer comprises a single coil.
The power stage of claim 1, wherein a primary winding of the third transformer comprises a single coil, and wherein a secondary winding of the third transformer comprises a single coil.
A GaN (gallium nitride) die, comprising: a GaN enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by a first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by a second transformer; and 45 a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by a third transformer.
The GaN die of claim 13, wherein the voltage clamp-ing device or circuit comprises a Zener diode having an anode electrically connected to the gate of the GaN deple-tion mode transistor and a cathode electrically connected to the source of the GaN depletion mode transistor.
The GaN die of claim 13, wherein the voltage clamp-ing device or circuit comprises a MOS-gated diode having B₂ an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically con-nected to the source of the GaN depletion mode transistor.
The GaN die of claim 13, further comprising: a rectification circuit having an input configured to be coupled across a single coil of a secondary winding of the second transformer and an output configured to deliver the bias current to the voltage clamping device or circuit.
The GaN die of claim 13, further comprising: a diode having an anode configured to be coupled to a first end of a single coil of a secondary winding of the third transformer and a cathode configured to deliver the bias current to the voltage clamping device or circuit.
A power stage, comprising: a first transformer; a GaN (gallium nitride) enhancement mode power tran-sistor; a first rectification circuit having an input coupled across a secondary coil of the first transformer and an output configured to deliver current to a gate of the GaN enhancement mode power transistor; a second transformer having a primary coil with a center tap that is grounded or disconnected; a GaN enhancement mode transistor electrically con-nected between the gate and a source of the GaN enhancement mode power transistor; a resistor electrically connected between a gate and a source of the GaN enhancement mode transistor; and a second rectification circuit having an input coupled across a secondary coil of the second transformer and an output configured to deliver current to the gate of the GaN enhancement mode transistor, wherein a center tap of the secondary coil is coupled to the source of the GaN enhancement mode transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
triple-transformer GaN power stage
GaN die with integrated triple-transformer drive circuits
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 49
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 12,176,887 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a circuit schematic of an embodiment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 2 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 3 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 4 illustrates a cross-sectional view of an embodiment of a depletion mode GaN device for use in any of the power stages shown in
FIG. 5 illustrates a cross-sectional view of an embodiment of an enhancement mode GaN device for use in any of the power stages shown in
FIG. 6 illustrates a dual-coil transformer embodiment for the transformers in
FIG. 7 illustrates a single-coil transformer embodiment for the transformers in
FIG. 8 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power stage, comprising: a first transformer; a second transformer; a third transformer; a GaN (gallium nitride) enhancement mode power tran-sistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer; and a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer.
The power stage of claim 1, wherein a primary winding of the second transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the second transformer has a center tap that is coupled to the source of the GaN depletion mode transistor and to a source of the GaN enhancement mode transistor.
The power stage of claim 1, wherein a primary winding of the third transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the third transformer has a center tap that is coupled to the gate of the GaN depletion mode transistor and to a drain of the GaN enhancement mode transistor.
The power stage of claim 1, wherein a primary winding of the second transformer has a center tap that is grounded or disconnected, wherein a secondary winding of the second transformer has a center tap that is coupled to the source of the GaN depletion mode transistor and to a source of the GaN enhancement mode transistor, wherein a primary wind-ing of the third transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the third transformer has a center tap that is coupled to the gate of the GaN depletion mode transistor and to a drain of the GaN enhancement mode transistor.
The power stage of claim 1, wherein the voltage clamping device or circuit comprises a Zener diode having an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically con-nected to the source of the GaN depletion mode transistor.
The power stage of claim 1, wherein the voltage clamping device or circuit comprises a GaN-gated diode having an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically connected to the source of the GaN depletion mode transis-tor.
The power stage of claim 1, wherein a primary winding of the second transformer comprises a single coil, and wherein a secondary winding of the second transformer comprises a single coil.
The power stage of claim 1, wherein a primary winding of the third transformer comprises a single coil, and wherein a secondary winding of the third transformer comprises a single coil.
A GaN (gallium nitride) die, comprising: a GaN enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by a first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by a second transformer; and 45 a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by a third transformer.
The GaN die of claim 13, wherein the voltage clamp-ing device or circuit comprises a Zener diode having an anode electrically connected to the gate of the GaN deple-tion mode transistor and a cathode electrically connected to the source of the GaN depletion mode transistor.
The GaN die of claim 13, wherein the voltage clamp-ing device or circuit comprises a MOS-gated diode having B₂ an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically con-nected to the source of the GaN depletion mode transistor.
The GaN die of claim 13, further comprising: a rectification circuit having an input configured to be coupled across a single coil of a secondary winding of the second transformer and an output configured to deliver the bias current to the voltage clamping device or circuit.
The GaN die of claim 13, further comprising: a diode having an anode configured to be coupled to a first end of a single coil of a secondary winding of the third transformer and a cathode configured to deliver the bias current to the voltage clamping device or circuit.
A power stage, comprising: a first transformer; a GaN (gallium nitride) enhancement mode power tran-sistor; a first rectification circuit having an input coupled across a secondary coil of the first transformer and an output configured to deliver current to a gate of the GaN enhancement mode power transistor; a second transformer having a primary coil with a center tap that is grounded or disconnected; a GaN enhancement mode transistor electrically con-nected between the gate and a source of the GaN enhancement mode power transistor; a resistor electrically connected between a gate and a source of the GaN enhancement mode transistor; and a second rectification circuit having an input coupled across a secondary coil of the second transformer and an output configured to deliver current to the gate of the GaN enhancement mode transistor, wherein a center tap of the secondary coil is coupled to the source of the GaN enhancement mode transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
triple-transformer GaN power stage
GaN die with integrated triple-transformer drive circuits
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 49
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,176,887 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a circuit schematic of an embodiment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 2 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 3 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 4 illustrates a cross-sectional view of an embodiment of a depletion mode GaN device for use in any of the power stages shown in
FIG. 5 illustrates a cross-sectional view of an embodiment of an enhancement mode GaN device for use in any of the power stages shown in
FIG. 6 illustrates a dual-coil transformer embodiment for the transformers in
FIG. 7 illustrates a single-coil transformer embodiment for the transformers in
FIG. 8 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power stage, comprising: a first transformer; a second transformer; a third transformer; a GaN (gallium nitride) enhancement mode power tran-sistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer; and a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer.
The power stage of claim 1, wherein a primary winding of the second transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the second transformer has a center tap that is coupled to the source of the GaN depletion mode transistor and to a source of the GaN enhancement mode transistor.
The power stage of claim 1, wherein a primary winding of the third transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the third transformer has a center tap that is coupled to the gate of the GaN depletion mode transistor and to a drain of the GaN enhancement mode transistor.
The power stage of claim 1, wherein a primary winding of the second transformer has a center tap that is grounded or disconnected, wherein a secondary winding of the second transformer has a center tap that is coupled to the source of the GaN depletion mode transistor and to a source of the GaN enhancement mode transistor, wherein a primary wind-ing of the third transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the third transformer has a center tap that is coupled to the gate of the GaN depletion mode transistor and to a drain of the GaN enhancement mode transistor.
The power stage of claim 1, wherein the voltage clamping device or circuit comprises a Zener diode having an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically con-nected to the source of the GaN depletion mode transistor.
The power stage of claim 1, wherein the voltage clamping device or circuit comprises a GaN-gated diode having an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically connected to the source of the GaN depletion mode transis-tor.
The power stage of claim 1, wherein a primary winding of the second transformer comprises a single coil, and wherein a secondary winding of the second transformer comprises a single coil.
The power stage of claim 1, wherein a primary winding of the third transformer comprises a single coil, and wherein a secondary winding of the third transformer comprises a single coil.
A GaN (gallium nitride) die, comprising: a GaN enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by a first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by a second transformer; and 45 a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by a third transformer.
The GaN die of claim 13, wherein the voltage clamp-ing device or circuit comprises a Zener diode having an anode electrically connected to the gate of the GaN deple-tion mode transistor and a cathode electrically connected to the source of the GaN depletion mode transistor.
The GaN die of claim 13, wherein the voltage clamp-ing device or circuit comprises a MOS-gated diode having B₂ an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically con-nected to the source of the GaN depletion mode transistor.
The GaN die of claim 13, further comprising: a rectification circuit having an input configured to be coupled across a single coil of a secondary winding of the second transformer and an output configured to deliver the bias current to the voltage clamping device or circuit.
The GaN die of claim 13, further comprising: a diode having an anode configured to be coupled to a first end of a single coil of a secondary winding of the third transformer and a cathode configured to deliver the bias current to the voltage clamping device or circuit.
A power stage, comprising: a first transformer; a GaN (gallium nitride) enhancement mode power tran-sistor; a first rectification circuit having an input coupled across a secondary coil of the first transformer and an output configured to deliver current to a gate of the GaN enhancement mode power transistor; a second transformer having a primary coil with a center tap that is grounded or disconnected; a GaN enhancement mode transistor electrically con-nected between the gate and a source of the GaN enhancement mode power transistor; a resistor electrically connected between a gate and a source of the GaN enhancement mode transistor; and a second rectification circuit having an input coupled across a secondary coil of the second transformer and an output configured to deliver current to the gate of the GaN enhancement mode transistor, wherein a center tap of the secondary coil is coupled to the source of the GaN enhancement mode transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
triple-transformer GaN power stage
GaN die with integrated triple-transformer drive circuits
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 49
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,176,887 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a circuit schematic of an embodiment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 2 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 3 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
FIG. 4 illustrates a cross-sectional view of an embodiment of a depletion mode GaN device for use in any of the power stages shown in
FIG. 5 illustrates a cross-sectional view of an embodiment of an enhancement mode GaN device for use in any of the power stages shown in
FIG. 6 illustrates a dual-coil transformer embodiment for the transformers in
FIG. 7 illustrates a single-coil transformer embodiment for the transformers in
FIG. 8 illustrates a circuit schematic of another embodi- ment of a power stage that implements a transformer-based drive approach for a GaN power device.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A power stage, comprising: a first transformer; a second transformer; a third transformer; a GaN (gallium nitride) enhancement mode power tran-sistor configured to conduct a load current when driven by a gate current derived from energy transferred by the first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by the second transformer; and a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by the third transformer.
The power stage of claim 1, wherein a primary winding of the second transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the second transformer has a center tap that is coupled to the source of the GaN depletion mode transistor and to a source of the GaN enhancement mode transistor.
The power stage of claim 1, wherein a primary winding of the third transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the third transformer has a center tap that is coupled to the gate of the GaN depletion mode transistor and to a drain of the GaN enhancement mode transistor.
The power stage of claim 1, wherein a primary winding of the second transformer has a center tap that is grounded or disconnected, wherein a secondary winding of the second transformer has a center tap that is coupled to the source of the GaN depletion mode transistor and to a source of the GaN enhancement mode transistor, wherein a primary wind-ing of the third transformer has a center tap that is grounded or disconnected, and wherein a secondary winding of the third transformer has a center tap that is coupled to the gate of the GaN depletion mode transistor and to a drain of the GaN enhancement mode transistor.
The power stage of claim 1, wherein the voltage clamping device or circuit comprises a Zener diode having an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically con-nected to the source of the GaN depletion mode transistor.
The power stage of claim 1, wherein the voltage clamping device or circuit comprises a GaN-gated diode having an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically connected to the source of the GaN depletion mode transis-tor.
The power stage of claim 1, wherein a primary winding of the second transformer comprises a single coil, and wherein a secondary winding of the second transformer comprises a single coil.
The power stage of claim 1, wherein a primary winding of the third transformer comprises a single coil, and wherein a secondary winding of the third transformer comprises a single coil.
A GaN (gallium nitride) die, comprising: a GaN enhancement mode power transistor configured to conduct a load current when driven by a gate current derived from energy transferred by a first transformer; a GaN depletion mode transistor configured to turn off the GaN enhancement mode power transistor absent a threshold voltage applied across a gate and a source of the GaN depletion mode transistor; a voltage clamping device or circuit configured to turn off the GaN depletion mode transistor when reverse biased by a bias current derived from energy transferred by a second transformer; and 45 a GaN enhancement mode transistor configured to turn on the GaN depletion mode transistor when driven by a gate current derived from energy transferred by a third transformer.
The GaN die of claim 13, wherein the voltage clamp-ing device or circuit comprises a Zener diode having an anode electrically connected to the gate of the GaN deple-tion mode transistor and a cathode electrically connected to the source of the GaN depletion mode transistor.
The GaN die of claim 13, wherein the voltage clamp-ing device or circuit comprises a MOS-gated diode having B₂ an anode electrically connected to the gate of the GaN depletion mode transistor and a cathode electrically con-nected to the source of the GaN depletion mode transistor.
The GaN die of claim 13, further comprising: a rectification circuit having an input configured to be coupled across a single coil of a secondary winding of the second transformer and an output configured to deliver the bias current to the voltage clamping device or circuit.
The GaN die of claim 13, further comprising: a diode having an anode configured to be coupled to a first end of a single coil of a secondary winding of the third transformer and a cathode configured to deliver the bias current to the voltage clamping device or circuit.
A power stage, comprising: a first transformer; a GaN (gallium nitride) enhancement mode power tran-sistor; a first rectification circuit having an input coupled across a secondary coil of the first transformer and an output configured to deliver current to a gate of the GaN enhancement mode power transistor; a second transformer having a primary coil with a center tap that is grounded or disconnected; a GaN enhancement mode transistor electrically con-nected between the gate and a source of the GaN enhancement mode power transistor; a resistor electrically connected between a gate and a source of the GaN enhancement mode transistor; and a second rectification circuit having an input coupled across a secondary coil of the second transformer and an output configured to deliver current to the gate of the GaN enhancement mode transistor, wherein a center tap of the secondary coil is coupled to the source of the GaN enhancement mode transistor. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
triple-transformer GaN power stage
GaN die with integrated triple-transformer drive circuits
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 49
Related documents with shared materials, methods, properties, or citations.
dual-transformer GaN power stage (enhancement mode only)
Cited non-patent literature · 5
dual-transformer GaN power stage (enhancement mode only)
Cited non-patent literature · 5
dual-transformer GaN power stage (enhancement mode only)
Cited non-patent literature · 5
dual-transformer GaN power stage (enhancement mode only)
Cited non-patent literature · 5