Patent
US 8,686,430BUFFER LAYER FOR GAN-ON-SI LED
Zhen Chen
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,686,430Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional diagram of a white LED assembly in accordance with one novel aspect. [0022]
FIG. 2 is a top-down diagram of the white LED assembly of
FIG. 3 is simplified and expanded cross-sectional diagram of the white LED assembly of
FIG. 4 is a top-down diagram of the blue LED device of the white LED assembly of
FIG. 5 is a cross-sectional diagram of a portion of the blue LED device of the white LED assembly of
FIGS. 6-18, except that all LRL is removed and some of the n-type layer is removed in the removal step illustrated in
FIG. 7 is a diagram that illustrates a step in a method of manufacturing where current blocking structures are added to the structure of
FIG. 8 is a diagram that illustrates a step in the method of manufacturing where a highly reflective layer is added to the structure of
FIG. 9 is a diagram that illustrates a step in the method of manufacturing where an encapsulation layer is formed over the structure of
FIG. 10 is a diagram that illustrates a step in the method of manufacturing where bond metal is added to the structure of
FIG. 11 is a diagram that illustrates a step in the method of manufacturing where a carrier wafer structure is wafer bonded to the structure of
FIG. 12 is a graph that shows the temperature cycle of the thermal compressing wafer bonding process used. [0033]
FIG. 13 is a diagram that illustrates a step in the method of manufacturing where the wafer bonded structure is flipped. [0034]
FIG. 14 is a diagram that illustrates a step in the method of manufacturing where the silicon substrate, the buffer layer, and the template layer are removed …
FIG. 15 is a top-down diagram of the wafer bonded structure after the removal step of
FIG. 16 is a cross-sectional diagram of
FIG. 17 is a diagram that illustrates a step in the method of manufacturing where the surface of the LRL is roughened. [0038]
FIG. 18 is a diagram that illustrates a step in the method of manufacturing where electrodes are added to the structure of
FIGS. 19A and 19B together are a table that sets forth details about each of the steps in the method of manufacturing of
FIG. 20 is a cross-sectional diagram of a blue LED device that is formed by the method of manufacture set forth above in connection with
FIG. 21 is a cross-sectional diagram of a blue LED device that is formed by the method of manufacture set forth above in connection with
FIG. 22 is a flowchart of a method in accordance with a first novel aspect. [0043]
FIG. 23 is a flowchart of a method in accordance with a second novel aspect. [0044]
FIG. 24 is a flowchart of a method in accordance with a third novel aspect. [0045]
FIG. 25 is a flowchart of a method in accordance with a fourth novel aspect. [0046]
FIG. 26 is a cross-sectional diagram of the epitaxial PAN structure layers of the blue LED device of
FIG. 27 is a diagram of a method in which the epitaxial layers of a blue LED are grown on a silicon substrate using a ZnTe or Ti O 2 buffer layer.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 12. canceled
An apparatus, comprising: a silicon substrate; a buffer layer disposed directly on the silicon substrate and comprising an aluminum nitride (A l N) layer and a zinc telluride (ZnTe) layer formed between the silicon substrate and the Al N layer,; and a gallium nitride (GaN) template layer disposed on the buffer layer; and an epitaxial light emitting diode (LED) structure disposed on the GaN template layer, wherein the buffer layer is disposed between the silicon substrate and the epitaxial LED structure, wherein the epitaxial LED structure comprises an active layer disposed between a p- type layer and an n-type layer, and wherein the active layer comprises gallium and nitrogen.
The apparatus of claim 13, wherein the b uffe r ZnTe layer is a single substantially homogenous layer of zinc telluride (ZnTe).
The apparatus of claim 13, w esfwherein the buffer layer is less than one hundred nanometers thick.
The apparatus of claim 13, wherein the n-type layer of the epitaxial LED structure has a thickness of at least two thousand nanometers.
The apparatus of claim 13, wherein the ZnTe layer is directly disposed on the silicon substrate.
The apparatus of claim 13, wherein the buffer layer further comprises an aluminum gallium nitride layer disposed between the A l N layer and the GaN template layer.
The apparatus of claim 13, wherein the GaN template layer is an undoped GaN layer.
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An apparatus, comprising: a silicon substrate; a buffer layer disposed directly on the silicon substrate and comprising an aluminum nitride (A l N) layer and a titanium dioxide (TiO 2) layer formed between the silicon substrate and the A l N layer,; and a gallium nitride (GaN) template layer disposed on the buffer layer; and an epitaxial light emitting diode (LED) structure disposed on the GaN template layer, wherein the buffer layer is disposed between the silicon substrate and the epitaxial LED structure, wherein the epitaxial LED structure comprises an active layer disposed between a p- type layer and an n-type layer, and wherein the active layer comprises gallium and nitrogen.
The apparatus of claim 24, wherein the buffer TiO 2 layer is a single substantially homogenous layer of titanium dioxide (Ti O 2).
The apparatus of claim 24, w essentially of titaniumn and ox ygen, andwherein the buffer layer is less than one hundred nanometers thick.
The apparatus of claim 24, wherein the TiO₂ layer is directly disposed on the silicon substrate.
The apparatus of claim 24, wherein the buffer layer further comprises an aluminum gallium nitride layer disposed between the A l N layer and the GaN template layer.
The apparatus of claim 24, wherein the GaN template layer is an undoped GaN layer.
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Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si epitaxial LED structure with ZnTe buffer
GaN-on-Si epitaxial LED structure with TiO₂ buffer
Materials described outside the worked examples.
zinc telluride
ZnTe
aluminum nitride
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–250 um | — |
Thickness | 440–490 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,686,430Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional diagram of a white LED assembly in accordance with one novel aspect. [0022]
FIG. 2 is a top-down diagram of the white LED assembly of
FIG. 3 is simplified and expanded cross-sectional diagram of the white LED assembly of
FIG. 4 is a top-down diagram of the blue LED device of the white LED assembly of
FIG. 5 is a cross-sectional diagram of a portion of the blue LED device of the white LED assembly of
FIGS. 6-18, except that all LRL is removed and some of the n-type layer is removed in the removal step illustrated in
FIG. 7 is a diagram that illustrates a step in a method of manufacturing where current blocking structures are added to the structure of
FIG. 8 is a diagram that illustrates a step in the method of manufacturing where a highly reflective layer is added to the structure of
FIG. 9 is a diagram that illustrates a step in the method of manufacturing where an encapsulation layer is formed over the structure of
FIG. 10 is a diagram that illustrates a step in the method of manufacturing where bond metal is added to the structure of
FIG. 11 is a diagram that illustrates a step in the method of manufacturing where a carrier wafer structure is wafer bonded to the structure of
FIG. 12 is a graph that shows the temperature cycle of the thermal compressing wafer bonding process used. [0033]
FIG. 13 is a diagram that illustrates a step in the method of manufacturing where the wafer bonded structure is flipped. [0034]
FIG. 14 is a diagram that illustrates a step in the method of manufacturing where the silicon substrate, the buffer layer, and the template layer are removed …
FIG. 15 is a top-down diagram of the wafer bonded structure after the removal step of
FIG. 16 is a cross-sectional diagram of
FIG. 17 is a diagram that illustrates a step in the method of manufacturing where the surface of the LRL is roughened. [0038]
FIG. 18 is a diagram that illustrates a step in the method of manufacturing where electrodes are added to the structure of
FIGS. 19A and 19B together are a table that sets forth details about each of the steps in the method of manufacturing of
FIG. 20 is a cross-sectional diagram of a blue LED device that is formed by the method of manufacture set forth above in connection with
FIG. 21 is a cross-sectional diagram of a blue LED device that is formed by the method of manufacture set forth above in connection with
FIG. 22 is a flowchart of a method in accordance with a first novel aspect. [0043]
FIG. 23 is a flowchart of a method in accordance with a second novel aspect. [0044]
FIG. 24 is a flowchart of a method in accordance with a third novel aspect. [0045]
FIG. 25 is a flowchart of a method in accordance with a fourth novel aspect. [0046]
FIG. 26 is a cross-sectional diagram of the epitaxial PAN structure layers of the blue LED device of
FIG. 27 is a diagram of a method in which the epitaxial layers of a blue LED are grown on a silicon substrate using a ZnTe or Ti O 2 buffer layer.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 12. canceled
An apparatus, comprising: a silicon substrate; a buffer layer disposed directly on the silicon substrate and comprising an aluminum nitride (A l N) layer and a zinc telluride (ZnTe) layer formed between the silicon substrate and the Al N layer,; and a gallium nitride (GaN) template layer disposed on the buffer layer; and an epitaxial light emitting diode (LED) structure disposed on the GaN template layer, wherein the buffer layer is disposed between the silicon substrate and the epitaxial LED structure, wherein the epitaxial LED structure comprises an active layer disposed between a p- type layer and an n-type layer, and wherein the active layer comprises gallium and nitrogen.
The apparatus of claim 13, wherein the b uffe r ZnTe layer is a single substantially homogenous layer of zinc telluride (ZnTe).
The apparatus of claim 13, w esfwherein the buffer layer is less than one hundred nanometers thick.
The apparatus of claim 13, wherein the n-type layer of the epitaxial LED structure has a thickness of at least two thousand nanometers.
The apparatus of claim 13, wherein the ZnTe layer is directly disposed on the silicon substrate.
The apparatus of claim 13, wherein the buffer layer further comprises an aluminum gallium nitride layer disposed between the A l N layer and the GaN template layer.
The apparatus of claim 13, wherein the GaN template layer is an undoped GaN layer.
15-16. canceled
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An apparatus, comprising: a silicon substrate; a buffer layer disposed directly on the silicon substrate and comprising an aluminum nitride (A l N) layer and a titanium dioxide (TiO 2) layer formed between the silicon substrate and the A l N layer,; and a gallium nitride (GaN) template layer disposed on the buffer layer; and an epitaxial light emitting diode (LED) structure disposed on the GaN template layer, wherein the buffer layer is disposed between the silicon substrate and the epitaxial LED structure, wherein the epitaxial LED structure comprises an active layer disposed between a p- type layer and an n-type layer, and wherein the active layer comprises gallium and nitrogen.
The apparatus of claim 24, wherein the buffer TiO 2 layer is a single substantially homogenous layer of titanium dioxide (Ti O 2).
The apparatus of claim 24, w essentially of titaniumn and ox ygen, andwherein the buffer layer is less than one hundred nanometers thick.
The apparatus of claim 24, wherein the TiO₂ layer is directly disposed on the silicon substrate.
The apparatus of claim 24, wherein the buffer layer further comprises an aluminum gallium nitride layer disposed between the A l N layer and the GaN template layer.
The apparatus of claim 24, wherein the GaN template layer is an undoped GaN layer.
26-27. canceled
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Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si epitaxial LED structure with ZnTe buffer
GaN-on-Si epitaxial LED structure with TiO₂ buffer
Materials described outside the worked examples.
zinc telluride
ZnTe
aluminum nitride
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–250 um | — |
Thickness | 440–490 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,686,430Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional diagram of a white LED assembly in accordance with one novel aspect. [0022]
FIG. 2 is a top-down diagram of the white LED assembly of
FIG. 3 is simplified and expanded cross-sectional diagram of the white LED assembly of
FIG. 4 is a top-down diagram of the blue LED device of the white LED assembly of
FIG. 5 is a cross-sectional diagram of a portion of the blue LED device of the white LED assembly of
FIGS. 6-18, except that all LRL is removed and some of the n-type layer is removed in the removal step illustrated in
FIG. 7 is a diagram that illustrates a step in a method of manufacturing where current blocking structures are added to the structure of
FIG. 8 is a diagram that illustrates a step in the method of manufacturing where a highly reflective layer is added to the structure of
FIG. 9 is a diagram that illustrates a step in the method of manufacturing where an encapsulation layer is formed over the structure of
FIG. 10 is a diagram that illustrates a step in the method of manufacturing where bond metal is added to the structure of
FIG. 11 is a diagram that illustrates a step in the method of manufacturing where a carrier wafer structure is wafer bonded to the structure of
FIG. 12 is a graph that shows the temperature cycle of the thermal compressing wafer bonding process used. [0033]
FIG. 13 is a diagram that illustrates a step in the method of manufacturing where the wafer bonded structure is flipped. [0034]
FIG. 14 is a diagram that illustrates a step in the method of manufacturing where the silicon substrate, the buffer layer, and the template layer are removed …
FIG. 15 is a top-down diagram of the wafer bonded structure after the removal step of
FIG. 16 is a cross-sectional diagram of
FIG. 17 is a diagram that illustrates a step in the method of manufacturing where the surface of the LRL is roughened. [0038]
FIG. 18 is a diagram that illustrates a step in the method of manufacturing where electrodes are added to the structure of
FIGS. 19A and 19B together are a table that sets forth details about each of the steps in the method of manufacturing of
FIG. 20 is a cross-sectional diagram of a blue LED device that is formed by the method of manufacture set forth above in connection with
FIG. 21 is a cross-sectional diagram of a blue LED device that is formed by the method of manufacture set forth above in connection with
FIG. 22 is a flowchart of a method in accordance with a first novel aspect. [0043]
FIG. 23 is a flowchart of a method in accordance with a second novel aspect. [0044]
FIG. 24 is a flowchart of a method in accordance with a third novel aspect. [0045]
FIG. 25 is a flowchart of a method in accordance with a fourth novel aspect. [0046]
FIG. 26 is a cross-sectional diagram of the epitaxial PAN structure layers of the blue LED device of
FIG. 27 is a diagram of a method in which the epitaxial layers of a blue LED are grown on a silicon substrate using a ZnTe or Ti O 2 buffer layer.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 12. canceled
An apparatus, comprising: a silicon substrate; a buffer layer disposed directly on the silicon substrate and comprising an aluminum nitride (A l N) layer and a zinc telluride (ZnTe) layer formed between the silicon substrate and the Al N layer,; and a gallium nitride (GaN) template layer disposed on the buffer layer; and an epitaxial light emitting diode (LED) structure disposed on the GaN template layer, wherein the buffer layer is disposed between the silicon substrate and the epitaxial LED structure, wherein the epitaxial LED structure comprises an active layer disposed between a p- type layer and an n-type layer, and wherein the active layer comprises gallium and nitrogen.
The apparatus of claim 13, wherein the b uffe r ZnTe layer is a single substantially homogenous layer of zinc telluride (ZnTe).
The apparatus of claim 13, w esfwherein the buffer layer is less than one hundred nanometers thick.
The apparatus of claim 13, wherein the n-type layer of the epitaxial LED structure has a thickness of at least two thousand nanometers.
The apparatus of claim 13, wherein the ZnTe layer is directly disposed on the silicon substrate.
The apparatus of claim 13, wherein the buffer layer further comprises an aluminum gallium nitride layer disposed between the A l N layer and the GaN template layer.
The apparatus of claim 13, wherein the GaN template layer is an undoped GaN layer.
15-16. canceled
canceled
19-23. canceled
canceled
canceled
canceled
canceled
An apparatus, comprising: a silicon substrate; a buffer layer disposed directly on the silicon substrate and comprising an aluminum nitride (A l N) layer and a titanium dioxide (TiO 2) layer formed between the silicon substrate and the A l N layer,; and a gallium nitride (GaN) template layer disposed on the buffer layer; and an epitaxial light emitting diode (LED) structure disposed on the GaN template layer, wherein the buffer layer is disposed between the silicon substrate and the epitaxial LED structure, wherein the epitaxial LED structure comprises an active layer disposed between a p- type layer and an n-type layer, and wherein the active layer comprises gallium and nitrogen.
The apparatus of claim 24, wherein the buffer TiO 2 layer is a single substantially homogenous layer of titanium dioxide (Ti O 2).
The apparatus of claim 24, w essentially of titaniumn and ox ygen, andwherein the buffer layer is less than one hundred nanometers thick.
The apparatus of claim 24, wherein the TiO₂ layer is directly disposed on the silicon substrate.
The apparatus of claim 24, wherein the buffer layer further comprises an aluminum gallium nitride layer disposed between the A l N layer and the GaN template layer.
The apparatus of claim 24, wherein the GaN template layer is an undoped GaN layer.
26-27. canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si epitaxial LED structure with ZnTe buffer
GaN-on-Si epitaxial LED structure with TiO₂ buffer
Materials described outside the worked examples.
zinc telluride
ZnTe
aluminum nitride
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–250 um | — |
Thickness | 440–490 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,686,430Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional diagram of a white LED assembly in accordance with one novel aspect. [0022]
FIG. 2 is a top-down diagram of the white LED assembly of
FIG. 3 is simplified and expanded cross-sectional diagram of the white LED assembly of
FIG. 4 is a top-down diagram of the blue LED device of the white LED assembly of
FIG. 5 is a cross-sectional diagram of a portion of the blue LED device of the white LED assembly of
FIGS. 6-18, except that all LRL is removed and some of the n-type layer is removed in the removal step illustrated in
FIG. 7 is a diagram that illustrates a step in a method of manufacturing where current blocking structures are added to the structure of
FIG. 8 is a diagram that illustrates a step in the method of manufacturing where a highly reflective layer is added to the structure of
FIG. 9 is a diagram that illustrates a step in the method of manufacturing where an encapsulation layer is formed over the structure of
FIG. 10 is a diagram that illustrates a step in the method of manufacturing where bond metal is added to the structure of
FIG. 11 is a diagram that illustrates a step in the method of manufacturing where a carrier wafer structure is wafer bonded to the structure of
FIG. 12 is a graph that shows the temperature cycle of the thermal compressing wafer bonding process used. [0033]
FIG. 13 is a diagram that illustrates a step in the method of manufacturing where the wafer bonded structure is flipped. [0034]
FIG. 14 is a diagram that illustrates a step in the method of manufacturing where the silicon substrate, the buffer layer, and the template layer are removed …
FIG. 15 is a top-down diagram of the wafer bonded structure after the removal step of
FIG. 16 is a cross-sectional diagram of
FIG. 17 is a diagram that illustrates a step in the method of manufacturing where the surface of the LRL is roughened. [0038]
FIG. 18 is a diagram that illustrates a step in the method of manufacturing where electrodes are added to the structure of
FIGS. 19A and 19B together are a table that sets forth details about each of the steps in the method of manufacturing of
FIG. 20 is a cross-sectional diagram of a blue LED device that is formed by the method of manufacture set forth above in connection with
FIG. 21 is a cross-sectional diagram of a blue LED device that is formed by the method of manufacture set forth above in connection with
FIG. 22 is a flowchart of a method in accordance with a first novel aspect. [0043]
FIG. 23 is a flowchart of a method in accordance with a second novel aspect. [0044]
FIG. 24 is a flowchart of a method in accordance with a third novel aspect. [0045]
FIG. 25 is a flowchart of a method in accordance with a fourth novel aspect. [0046]
FIG. 26 is a cross-sectional diagram of the epitaxial PAN structure layers of the blue LED device of
FIG. 27 is a diagram of a method in which the epitaxial layers of a blue LED are grown on a silicon substrate using a ZnTe or Ti O 2 buffer layer.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 12. canceled
An apparatus, comprising: a silicon substrate; a buffer layer disposed directly on the silicon substrate and comprising an aluminum nitride (A l N) layer and a zinc telluride (ZnTe) layer formed between the silicon substrate and the Al N layer,; and a gallium nitride (GaN) template layer disposed on the buffer layer; and an epitaxial light emitting diode (LED) structure disposed on the GaN template layer, wherein the buffer layer is disposed between the silicon substrate and the epitaxial LED structure, wherein the epitaxial LED structure comprises an active layer disposed between a p- type layer and an n-type layer, and wherein the active layer comprises gallium and nitrogen.
The apparatus of claim 13, wherein the b uffe r ZnTe layer is a single substantially homogenous layer of zinc telluride (ZnTe).
The apparatus of claim 13, w esfwherein the buffer layer is less than one hundred nanometers thick.
The apparatus of claim 13, wherein the n-type layer of the epitaxial LED structure has a thickness of at least two thousand nanometers.
The apparatus of claim 13, wherein the ZnTe layer is directly disposed on the silicon substrate.
The apparatus of claim 13, wherein the buffer layer further comprises an aluminum gallium nitride layer disposed between the A l N layer and the GaN template layer.
The apparatus of claim 13, wherein the GaN template layer is an undoped GaN layer.
15-16. canceled
canceled
19-23. canceled
canceled
canceled
canceled
canceled
An apparatus, comprising: a silicon substrate; a buffer layer disposed directly on the silicon substrate and comprising an aluminum nitride (A l N) layer and a titanium dioxide (TiO 2) layer formed between the silicon substrate and the A l N layer,; and a gallium nitride (GaN) template layer disposed on the buffer layer; and an epitaxial light emitting diode (LED) structure disposed on the GaN template layer, wherein the buffer layer is disposed between the silicon substrate and the epitaxial LED structure, wherein the epitaxial LED structure comprises an active layer disposed between a p- type layer and an n-type layer, and wherein the active layer comprises gallium and nitrogen.
The apparatus of claim 24, wherein the buffer TiO 2 layer is a single substantially homogenous layer of titanium dioxide (Ti O 2).
The apparatus of claim 24, w essentially of titaniumn and ox ygen, andwherein the buffer layer is less than one hundred nanometers thick.
The apparatus of claim 24, wherein the TiO₂ layer is directly disposed on the silicon substrate.
The apparatus of claim 24, wherein the buffer layer further comprises an aluminum gallium nitride layer disposed between the A l N layer and the GaN template layer.
The apparatus of claim 24, wherein the GaN template layer is an undoped GaN layer.
26-27. canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-Si epitaxial LED structure with ZnTe buffer
GaN-on-Si epitaxial LED structure with TiO₂ buffer
Materials described outside the worked examples.
zinc telluride
ZnTe
aluminum nitride
AlN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–250 um | — |
Thickness | 440–490 nm |
Related documents with shared materials, methods, properties, or citations.
gallium nitride
GaN
titanium dioxide
TiO₂
aluminum gallium nitride
AlGaN
zinc sulfide
ZnS
| — |
— | 3.4–6.2 eV | — |
Thickness | 0.2–1.5 mm | — |
Thickness | 0.5–3 mm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 300 nm | — |
Thickness | ≤ 2000 nm | — |
Thickness | ≤ 25 nm | — |
Thickness | ≤ 200 nm | — |
Temperature | ≥ 280 °C | — |
Thickness | ≥ 50 nm | — |
gallium nitride
GaN
titanium dioxide
TiO₂
aluminum gallium nitride
AlGaN
zinc sulfide
ZnS
| — |
— | 3.4–6.2 eV | — |
Thickness | 0.2–1.5 mm | — |
Thickness | 0.5–3 mm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 300 nm | — |
Thickness | ≤ 2000 nm | — |
Thickness | ≤ 25 nm | — |
Thickness | ≤ 200 nm | — |
Temperature | ≥ 280 °C | — |
Thickness | ≥ 50 nm | — |
gallium nitride
GaN
titanium dioxide
TiO₂
aluminum gallium nitride
AlGaN
zinc sulfide
ZnS
| — |
— | 3.4–6.2 eV | — |
Thickness | 0.2–1.5 mm | — |
Thickness | 0.5–3 mm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 300 nm | — |
Thickness | ≤ 2000 nm | — |
Thickness | ≤ 25 nm | — |
Thickness | ≤ 200 nm | — |
Temperature | ≥ 280 °C | — |
Thickness | ≥ 50 nm | — |
gallium nitride
GaN
titanium dioxide
TiO₂
aluminum gallium nitride
AlGaN
zinc sulfide
ZnS
| — |
— | 3.4–6.2 eV | — |
Thickness | 0.2–1.5 mm | — |
Thickness | 0.5–3 mm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 300 nm | — |
Thickness | ≤ 2000 nm | — |
Thickness | ≤ 25 nm | — |
Thickness | ≤ 200 nm | — |
Temperature | ≥ 280 °C | — |
Thickness | ≥ 50 nm | — |