Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1D illustrate cross-sectional views representing 30 various operations in a method of fabricating a co-integrated gallium nitride (GaN) complementary …
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIGS. 4A-4C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 5 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure. 45
FIG. 6 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 7C illustrates a fuse which is in an open state or a “blown” state in accordance with an embodiment of the present disclosure.
FIG. 8 illustrates cross-sectional views representing a stacked gate-all-around integrated circuit structure, in accor- 55 dance with an embodiment of the …
FIG. 9 illustrates cross-sectional views representing a stacked gate-all-around integrated circuit structure having a depopulated channel structure, in …
FIG. 10 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 11 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 12 is an isometric view of a mobile computing 65 platform employing an IC fabricated according to one or more processes described herein or including one …
FIG. 55 2. In an embodiment, high-k dielectric 272 is the same high-k dielectric material as gate dielectric layer 274 of gate structure 208.
FIG. 65 2. Gate structure 208 may include a gate dielectric 210, such as a high k gate dielectric, such as but not limited to hafnium B₂ oxide (e.g., HfO₂) and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a silicon (111) substrate having a first region and a second region; a structure comprising gallium and nitrogen on the first region of the silicon (111) substrate, the structure comprising gallium and nitrogen having an uppermost surface and a bottommost surface; a structure comprising germanium on the second region of the silicon (111) substrate, the structure comprising germanium having an uppermost surface co-planar with the uppermost surface of the structure comprising gallium and nitrogen, and the structure comprising germanium having a bottommost surface co-planar with the bottommost surface of the structure compris-ing gallium and nitrogen; and a dielectric spacer laterally between and in contact with the structure comprising gallium and nitrogen and the structure comprising germanium, the dielectric spacer on the silicon (111) substrate, wherein the dielectric spacer has an uppermost surface co-planar with the uppermost surface of the structure comprising germa-nium and with the uppermost surface of the structure comprising gallium and nitrogen, and wherein the dielectric spacer has a bottommost surface co-planar with the bottommost surface of the structure compris-ing germanium and with the bottommost surface of the structure comprising gallium and nitrogen.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen comprises a polarization layer on a gallium nitride layer.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen comprises a gal-lium nitride layer on an AlN layer.
The semiconductor structure of claim 1, wherein the structure comprising germanium comprises a layer of SiGe on a layer of Ge.
The semiconductor structure of claim 1, wherein the structure comprising germanium comprises a first layer of SiGe on a second layer of SiGe, the second layer of SiGe having a greater germanium concentration than the first layer of SiGe.
The semiconductor structure of claim 1, wherein the dielectric spacer comprises silicon nitride or silicon oxide.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen has a first plural-ity of semiconductor devices thereon, the first plurality of semiconductor devices having a voltage supply in a range of 5-10 Volts, and wherein the structure comprising germanium has a second plurality of semiconductor devices thereon, the second plurality of semiconductor devices having a voltage supply of approximately 1 Volt.
Layer stacks claimed or described, ordered top of device to substrate.
co-integrated GaN and Ge semiconductor structure on Si(111)
GaN RF/power semiconductor devices (5-10 V supply)
CMOS semiconductor devices (~1 V supply)
Materials described outside the worked examples.
silicon (111) substrate
Si
structure comprising gallium and nitrogen
structure comprising germanium
dielectric spacer
polarization layer
gallium nitride layer
GaN
AlGaN
InAlGaN
AlN layer
AlN
SiGe layer
SiGe
Ge layer
Ge
silicon nitride
Si₃N₄
silicon oxide
SiO₂
GaN stack
Ge or Ge-rich alloy
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIGS. 4A-4C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 5 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure. 45
FIG. 6 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 7C illustrates a fuse which is in an open state or a “blown” state in accordance with an embodiment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.6–1 V | — |
Voltage | ≥ 2 V | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Apparatus and Method of Fabrication for GaN/Si Transistors Isolation
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1D illustrate cross-sectional views representing 30 various operations in a method of fabricating a co-integrated gallium nitride (GaN) complementary …
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIGS. 4A-4C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 5 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure. 45
FIG. 6 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 7C illustrates a fuse which is in an open state or a “blown” state in accordance with an embodiment of the present disclosure.
FIG. 8 illustrates cross-sectional views representing a stacked gate-all-around integrated circuit structure, in accor- 55 dance with an embodiment of the …
FIG. 9 illustrates cross-sectional views representing a stacked gate-all-around integrated circuit structure having a depopulated channel structure, in …
FIG. 10 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 11 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 12 is an isometric view of a mobile computing 65 platform employing an IC fabricated according to one or more processes described herein or including one …
FIG. 55 2. In an embodiment, high-k dielectric 272 is the same high-k dielectric material as gate dielectric layer 274 of gate structure 208.
FIG. 65 2. Gate structure 208 may include a gate dielectric 210, such as a high k gate dielectric, such as but not limited to hafnium B₂ oxide (e.g., HfO₂) and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a silicon (111) substrate having a first region and a second region; a structure comprising gallium and nitrogen on the first region of the silicon (111) substrate, the structure comprising gallium and nitrogen having an uppermost surface and a bottommost surface; a structure comprising germanium on the second region of the silicon (111) substrate, the structure comprising germanium having an uppermost surface co-planar with the uppermost surface of the structure comprising gallium and nitrogen, and the structure comprising germanium having a bottommost surface co-planar with the bottommost surface of the structure compris-ing gallium and nitrogen; and a dielectric spacer laterally between and in contact with the structure comprising gallium and nitrogen and the structure comprising germanium, the dielectric spacer on the silicon (111) substrate, wherein the dielectric spacer has an uppermost surface co-planar with the uppermost surface of the structure comprising germa-nium and with the uppermost surface of the structure comprising gallium and nitrogen, and wherein the dielectric spacer has a bottommost surface co-planar with the bottommost surface of the structure compris-ing germanium and with the bottommost surface of the structure comprising gallium and nitrogen.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen comprises a polarization layer on a gallium nitride layer.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen comprises a gal-lium nitride layer on an AlN layer.
The semiconductor structure of claim 1, wherein the structure comprising germanium comprises a layer of SiGe on a layer of Ge.
The semiconductor structure of claim 1, wherein the structure comprising germanium comprises a first layer of SiGe on a second layer of SiGe, the second layer of SiGe having a greater germanium concentration than the first layer of SiGe.
The semiconductor structure of claim 1, wherein the dielectric spacer comprises silicon nitride or silicon oxide.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen has a first plural-ity of semiconductor devices thereon, the first plurality of semiconductor devices having a voltage supply in a range of 5-10 Volts, and wherein the structure comprising germanium has a second plurality of semiconductor devices thereon, the second plurality of semiconductor devices having a voltage supply of approximately 1 Volt.
Layer stacks claimed or described, ordered top of device to substrate.
co-integrated GaN and Ge semiconductor structure on Si(111)
GaN RF/power semiconductor devices (5-10 V supply)
CMOS semiconductor devices (~1 V supply)
Materials described outside the worked examples.
silicon (111) substrate
Si
structure comprising gallium and nitrogen
structure comprising germanium
dielectric spacer
polarization layer
gallium nitride layer
GaN
AlGaN
InAlGaN
AlN layer
AlN
SiGe layer
SiGe
Ge layer
Ge
silicon nitride
Si₃N₄
silicon oxide
SiO₂
GaN stack
Ge or Ge-rich alloy
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIGS. 4A-4C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 5 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure. 45
FIG. 6 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 7C illustrates a fuse which is in an open state or a “blown” state in accordance with an embodiment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.6–1 V | — |
Voltage | ≥ 2 V | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Apparatus and Method of Fabrication for GaN/Si Transistors Isolation
GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
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N-CHANNEL GALLIUM NITRIDE TRANSISTORS
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ENHANCEMENT-MODE N-CHANNEL AND P-CHANNEL GAN DEVICE INTEGRATION STRUCTURE
GAN DEVICES ON ENGINEERED SILICON SUBSTRATES
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1D illustrate cross-sectional views representing 30 various operations in a method of fabricating a co-integrated gallium nitride (GaN) complementary …
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIGS. 4A-4C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 5 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure. 45
FIG. 6 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 7C illustrates a fuse which is in an open state or a “blown” state in accordance with an embodiment of the present disclosure.
FIG. 8 illustrates cross-sectional views representing a stacked gate-all-around integrated circuit structure, in accor- 55 dance with an embodiment of the …
FIG. 9 illustrates cross-sectional views representing a stacked gate-all-around integrated circuit structure having a depopulated channel structure, in …
FIG. 10 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 11 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 12 is an isometric view of a mobile computing 65 platform employing an IC fabricated according to one or more processes described herein or including one …
FIG. 55 2. In an embodiment, high-k dielectric 272 is the same high-k dielectric material as gate dielectric layer 274 of gate structure 208.
FIG. 65 2. Gate structure 208 may include a gate dielectric 210, such as a high k gate dielectric, such as but not limited to hafnium B₂ oxide (e.g., HfO₂) and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a silicon (111) substrate having a first region and a second region; a structure comprising gallium and nitrogen on the first region of the silicon (111) substrate, the structure comprising gallium and nitrogen having an uppermost surface and a bottommost surface; a structure comprising germanium on the second region of the silicon (111) substrate, the structure comprising germanium having an uppermost surface co-planar with the uppermost surface of the structure comprising gallium and nitrogen, and the structure comprising germanium having a bottommost surface co-planar with the bottommost surface of the structure compris-ing gallium and nitrogen; and a dielectric spacer laterally between and in contact with the structure comprising gallium and nitrogen and the structure comprising germanium, the dielectric spacer on the silicon (111) substrate, wherein the dielectric spacer has an uppermost surface co-planar with the uppermost surface of the structure comprising germa-nium and with the uppermost surface of the structure comprising gallium and nitrogen, and wherein the dielectric spacer has a bottommost surface co-planar with the bottommost surface of the structure compris-ing germanium and with the bottommost surface of the structure comprising gallium and nitrogen.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen comprises a polarization layer on a gallium nitride layer.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen comprises a gal-lium nitride layer on an AlN layer.
The semiconductor structure of claim 1, wherein the structure comprising germanium comprises a layer of SiGe on a layer of Ge.
The semiconductor structure of claim 1, wherein the structure comprising germanium comprises a first layer of SiGe on a second layer of SiGe, the second layer of SiGe having a greater germanium concentration than the first layer of SiGe.
The semiconductor structure of claim 1, wherein the dielectric spacer comprises silicon nitride or silicon oxide.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen has a first plural-ity of semiconductor devices thereon, the first plurality of semiconductor devices having a voltage supply in a range of 5-10 Volts, and wherein the structure comprising germanium has a second plurality of semiconductor devices thereon, the second plurality of semiconductor devices having a voltage supply of approximately 1 Volt.
Layer stacks claimed or described, ordered top of device to substrate.
co-integrated GaN and Ge semiconductor structure on Si(111)
GaN RF/power semiconductor devices (5-10 V supply)
CMOS semiconductor devices (~1 V supply)
Materials described outside the worked examples.
silicon (111) substrate
Si
structure comprising gallium and nitrogen
structure comprising germanium
dielectric spacer
polarization layer
gallium nitride layer
GaN
AlGaN
InAlGaN
AlN layer
AlN
SiGe layer
SiGe
Ge layer
Ge
silicon nitride
Si₃N₄
silicon oxide
SiO₂
GaN stack
Ge or Ge-rich alloy
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIGS. 4A-4C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 5 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure. 45
FIG. 6 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 7C illustrates a fuse which is in an open state or a “blown” state in accordance with an embodiment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.6–1 V | — |
Voltage | ≥ 2 V | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Apparatus and Method of Fabrication for GaN/Si Transistors Isolation
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ENHANCEMENT-MODE N-CHANNEL AND P-CHANNEL GAN DEVICE INTEGRATION STRUCTURE
GAN DEVICES ON ENGINEERED SILICON SUBSTRATES
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1D illustrate cross-sectional views representing 30 various operations in a method of fabricating a co-integrated gallium nitride (GaN) complementary …
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIGS. 4A-4C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 5 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure. 45
FIG. 6 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 7C illustrates a fuse which is in an open state or a “blown” state in accordance with an embodiment of the present disclosure.
FIG. 8 illustrates cross-sectional views representing a stacked gate-all-around integrated circuit structure, in accor- 55 dance with an embodiment of the …
FIG. 9 illustrates cross-sectional views representing a stacked gate-all-around integrated circuit structure having a depopulated channel structure, in …
FIG. 10 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 11 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 12 is an isometric view of a mobile computing 65 platform employing an IC fabricated according to one or more processes described herein or including one …
FIG. 55 2. In an embodiment, high-k dielectric 272 is the same high-k dielectric material as gate dielectric layer 274 of gate structure 208.
FIG. 65 2. Gate structure 208 may include a gate dielectric 210, such as a high k gate dielectric, such as but not limited to hafnium B₂ oxide (e.g., HfO₂) and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a silicon (111) substrate having a first region and a second region; a structure comprising gallium and nitrogen on the first region of the silicon (111) substrate, the structure comprising gallium and nitrogen having an uppermost surface and a bottommost surface; a structure comprising germanium on the second region of the silicon (111) substrate, the structure comprising germanium having an uppermost surface co-planar with the uppermost surface of the structure comprising gallium and nitrogen, and the structure comprising germanium having a bottommost surface co-planar with the bottommost surface of the structure compris-ing gallium and nitrogen; and a dielectric spacer laterally between and in contact with the structure comprising gallium and nitrogen and the structure comprising germanium, the dielectric spacer on the silicon (111) substrate, wherein the dielectric spacer has an uppermost surface co-planar with the uppermost surface of the structure comprising germa-nium and with the uppermost surface of the structure comprising gallium and nitrogen, and wherein the dielectric spacer has a bottommost surface co-planar with the bottommost surface of the structure compris-ing germanium and with the bottommost surface of the structure comprising gallium and nitrogen.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen comprises a polarization layer on a gallium nitride layer.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen comprises a gal-lium nitride layer on an AlN layer.
The semiconductor structure of claim 1, wherein the structure comprising germanium comprises a layer of SiGe on a layer of Ge.
The semiconductor structure of claim 1, wherein the structure comprising germanium comprises a first layer of SiGe on a second layer of SiGe, the second layer of SiGe having a greater germanium concentration than the first layer of SiGe.
The semiconductor structure of claim 1, wherein the dielectric spacer comprises silicon nitride or silicon oxide.
The semiconductor structure of claim 1, wherein the structure comprising gallium and nitrogen has a first plural-ity of semiconductor devices thereon, the first plurality of semiconductor devices having a voltage supply in a range of 5-10 Volts, and wherein the structure comprising germanium has a second plurality of semiconductor devices thereon, the second plurality of semiconductor devices having a voltage supply of approximately 1 Volt.
Layer stacks claimed or described, ordered top of device to substrate.
co-integrated GaN and Ge semiconductor structure on Si(111)
GaN RF/power semiconductor devices (5-10 V supply)
CMOS semiconductor devices (~1 V supply)
Materials described outside the worked examples.
silicon (111) substrate
Si
structure comprising gallium and nitrogen
structure comprising germanium
dielectric spacer
polarization layer
gallium nitride layer
GaN
AlGaN
InAlGaN
AlN layer
AlN
SiGe layer
SiGe
Ge layer
Ge
silicon nitride
Si₃N₄
silicon oxide
SiO₂
GaN stack
Ge or Ge-rich alloy
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIGS. 4A-4C illustrate a GaN transistor in accordance with embodiments of the present disclosure.
FIG. 5 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure. 45
FIG. 6 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 7C illustrates a fuse which is in an open state or a “blown” state in accordance with an embodiment of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.6–1 V | — |
Voltage | ≥ 2 V | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Apparatus and Method of Fabrication for GaN/Si Transistors Isolation
GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER
N-CHANNEL GALLIUM NITRIDE TRANSISTORS
GALLIUM NITRIDE TRANSISTORS FOR HIGH-VOLTAGE RADIO FREQUENCY SWITCHES
BUMPED, SELF-ISOLATED GaN TRANSISTOR CHIP WITH ELECTRICALLY ISOLATED BACK SURFACE
POLARIZATION FREE GALLIUM NITRIDE-BASED PHOTONIC DEVICES ON NANOPATTERNED SILICON
ULTRA LOW PARASITIC INDUCTANCE INTEGRATED CASCODE GaN DEVICES
HIGH-QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON
GALLIUM NITRIDE TRANSISTOR WITH A DOPED REGION
ENHANCEMENT-MODE N-CHANNEL AND P-CHANNEL GAN DEVICE INTEGRATION STRUCTURE
GAN DEVICES ON ENGINEERED SILICON SUBSTRATES
