Patent
US 8,785,974BUMPED, SELF ISOLATED GaN TRANSISTOR CHIP WITH ELECTRICALLY
Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,785,974Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a side view of a prior art device. [0008]
FIG. 2 shows a side view of the prior art device of
FIG. 3 shows a side view of a device according to the present invention. [0010]
FIG. 4 shows a side view of the device of the present invention with a heat sink attached.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The device in -e lai m-1 of claim 9, wherein the compound material is formed of various layers comprised of a combination of Indium, Gallium, Nitrogen, and Aluminum.
The device of claim 2, wherein the device is an enhancement mode GaN transistor.
The device of claim [[1]] 9, wherein the device is an enhancement mode transistor.
: The device of claim 3, wherein multiple active devices are integrated onto the silicon substrate.
: The device of claim 3, wherein the transistors are in a half bridge or a full bridge configuration.
: The device of claim 3, wherein the transistors are driven by smaller driver transistors on the same silicon substrate. 3
The device of claim [[1]] 9, further comprising a second passivation material of polyimide plastic.
The device of claim [[1]] 9, wherein the active area does not extend to the edges of the device.
The device of claim [[1]] 9, further comprising a heatsink mounted directly to a second surface of the silicon substrate without a layer of insulation between the substrate and the heat sink.
The device of claim [[1]] 9, wherein the electrical connection comprises a solder bump formed of various combinations of copper, lead, silver, antimony and tin.
A semiconductor device comprising: a silicon substrate; a compound semiconductor material including an active area [[,]] 2 Application No. 12/7 56,975 Docket No E O 10 1 0005/P 005 Reply to Office Action of an insulating material between the silicon substrate and the active area[[,]]; and a top surface comprising: means of electrical connection to the active area, and a first passivation material, wherein the passivation material is silicon nitride, silicon dioxide, or a combination of both, and wherein the electrical connection includes at least one gate electrode, at least one drain electrode, and at least two source electrodes, wherein one of the source electrodes is used as a Kelvin connection.
Layer stacks claimed or described, ordered top of device to substrate.
bumped self-isolated GaN transistor chip with electrically isolated back surface
Materials described outside the worked examples.
compound semiconductor material (InGaAlN-based)
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,974Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a side view of a prior art device. [0008]
FIG. 2 shows a side view of the prior art device of
FIG. 3 shows a side view of a device according to the present invention. [0010]
FIG. 4 shows a side view of the device of the present invention with a heat sink attached.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The device in -e lai m-1 of claim 9, wherein the compound material is formed of various layers comprised of a combination of Indium, Gallium, Nitrogen, and Aluminum.
The device of claim 2, wherein the device is an enhancement mode GaN transistor.
The device of claim [[1]] 9, wherein the device is an enhancement mode transistor.
: The device of claim 3, wherein multiple active devices are integrated onto the silicon substrate.
: The device of claim 3, wherein the transistors are in a half bridge or a full bridge configuration.
: The device of claim 3, wherein the transistors are driven by smaller driver transistors on the same silicon substrate. 3
The device of claim [[1]] 9, further comprising a second passivation material of polyimide plastic.
The device of claim [[1]] 9, wherein the active area does not extend to the edges of the device.
The device of claim [[1]] 9, further comprising a heatsink mounted directly to a second surface of the silicon substrate without a layer of insulation between the substrate and the heat sink.
The device of claim [[1]] 9, wherein the electrical connection comprises a solder bump formed of various combinations of copper, lead, silver, antimony and tin.
A semiconductor device comprising: a silicon substrate; a compound semiconductor material including an active area [[,]] 2 Application No. 12/7 56,975 Docket No E O 10 1 0005/P 005 Reply to Office Action of an insulating material between the silicon substrate and the active area[[,]]; and a top surface comprising: means of electrical connection to the active area, and a first passivation material, wherein the passivation material is silicon nitride, silicon dioxide, or a combination of both, and wherein the electrical connection includes at least one gate electrode, at least one drain electrode, and at least two source electrodes, wherein one of the source electrodes is used as a Kelvin connection.
Layer stacks claimed or described, ordered top of device to substrate.
bumped self-isolated GaN transistor chip with electrically isolated back surface
Materials described outside the worked examples.
compound semiconductor material (InGaAlN-based)
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,974Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a side view of a prior art device. [0008]
FIG. 2 shows a side view of the prior art device of
FIG. 3 shows a side view of a device according to the present invention. [0010]
FIG. 4 shows a side view of the device of the present invention with a heat sink attached.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The device in -e lai m-1 of claim 9, wherein the compound material is formed of various layers comprised of a combination of Indium, Gallium, Nitrogen, and Aluminum.
The device of claim 2, wherein the device is an enhancement mode GaN transistor.
The device of claim [[1]] 9, wherein the device is an enhancement mode transistor.
: The device of claim 3, wherein multiple active devices are integrated onto the silicon substrate.
: The device of claim 3, wherein the transistors are in a half bridge or a full bridge configuration.
: The device of claim 3, wherein the transistors are driven by smaller driver transistors on the same silicon substrate. 3
The device of claim [[1]] 9, further comprising a second passivation material of polyimide plastic.
The device of claim [[1]] 9, wherein the active area does not extend to the edges of the device.
The device of claim [[1]] 9, further comprising a heatsink mounted directly to a second surface of the silicon substrate without a layer of insulation between the substrate and the heat sink.
The device of claim [[1]] 9, wherein the electrical connection comprises a solder bump formed of various combinations of copper, lead, silver, antimony and tin.
A semiconductor device comprising: a silicon substrate; a compound semiconductor material including an active area [[,]] 2 Application No. 12/7 56,975 Docket No E O 10 1 0005/P 005 Reply to Office Action of an insulating material between the silicon substrate and the active area[[,]]; and a top surface comprising: means of electrical connection to the active area, and a first passivation material, wherein the passivation material is silicon nitride, silicon dioxide, or a combination of both, and wherein the electrical connection includes at least one gate electrode, at least one drain electrode, and at least two source electrodes, wherein one of the source electrodes is used as a Kelvin connection.
Layer stacks claimed or described, ordered top of device to substrate.
bumped self-isolated GaN transistor chip with electrically isolated back surface
Materials described outside the worked examples.
compound semiconductor material (InGaAlN-based)
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,785,974Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a side view of a prior art device. [0008]
FIG. 2 shows a side view of the prior art device of
FIG. 3 shows a side view of a device according to the present invention. [0010]
FIG. 4 shows a side view of the device of the present invention with a heat sink attached.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The device in -e lai m-1 of claim 9, wherein the compound material is formed of various layers comprised of a combination of Indium, Gallium, Nitrogen, and Aluminum.
The device of claim 2, wherein the device is an enhancement mode GaN transistor.
The device of claim [[1]] 9, wherein the device is an enhancement mode transistor.
: The device of claim 3, wherein multiple active devices are integrated onto the silicon substrate.
: The device of claim 3, wherein the transistors are in a half bridge or a full bridge configuration.
: The device of claim 3, wherein the transistors are driven by smaller driver transistors on the same silicon substrate. 3
The device of claim [[1]] 9, further comprising a second passivation material of polyimide plastic.
The device of claim [[1]] 9, wherein the active area does not extend to the edges of the device.
The device of claim [[1]] 9, further comprising a heatsink mounted directly to a second surface of the silicon substrate without a layer of insulation between the substrate and the heat sink.
The device of claim [[1]] 9, wherein the electrical connection comprises a solder bump formed of various combinations of copper, lead, silver, antimony and tin.
A semiconductor device comprising: a silicon substrate; a compound semiconductor material including an active area [[,]] 2 Application No. 12/7 56,975 Docket No E O 10 1 0005/P 005 Reply to Office Action of an insulating material between the silicon substrate and the active area[[,]]; and a top surface comprising: means of electrical connection to the active area, and a first passivation material, wherein the passivation material is silicon nitride, silicon dioxide, or a combination of both, and wherein the electrical connection includes at least one gate electrode, at least one drain electrode, and at least two source electrodes, wherein one of the source electrodes is used as a Kelvin connection.
Layer stacks claimed or described, ordered top of device to substrate.
bumped self-isolated GaN transistor chip with electrically isolated back surface
Materials described outside the worked examples.
compound semiconductor material (InGaAlN-based)
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
silicon substrate
Si
silicon nitride
Si₃N₄
silicon dioxide
SiO₂
aluminum nitride seed layer
AlN
polyimide plastic
solder bump (Cu/Pb/Ag/Sb/Sn combinations)
AlGaN buffer layer
AlGaN
InAlGaN
silicon substrate
Si
silicon nitride
Si₃N₄
silicon dioxide
SiO₂
aluminum nitride seed layer
AlN
polyimide plastic
solder bump (Cu/Pb/Ag/Sb/Sn combinations)
AlGaN buffer layer
AlGaN
InAlGaN
silicon substrate
Si
silicon nitride
Si₃N₄
silicon dioxide
SiO₂
aluminum nitride seed layer
AlN
polyimide plastic
solder bump (Cu/Pb/Ag/Sb/Sn combinations)
AlGaN buffer layer
AlGaN
InAlGaN
silicon substrate
Si
silicon nitride
Si₃N₄
silicon dioxide
SiO₂
aluminum nitride seed layer
AlN
polyimide plastic
solder bump (Cu/Pb/Ag/Sb/Sn combinations)
AlGaN buffer layer
AlGaN
InAlGaN