Patent
US 11,699,750 B2GALLIUM NITRIDE EPITAXIAL STRUCTURES FOR POWER DEVICES
Vladimir Odnoblyudov, Steve Lester, Ozgur Aktas
QROMIS, INC., Santa Clara, CA (US)·Jul. 11, 2023·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 11,699,750 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to an embodiment of …
FIG. 2 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to another …
FIG. 3 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure with a back-side contact …
FIG. 4 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure with a front-side contact …
FIG. 5 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to an embodiment of …
FIG. 6 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to another …
FIG. 7 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to a further …
FIG. 8 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to some other …
FIG. 9B illustrates an exemplary conduction band dia- gram of a HEMT with an AlGaN back barrier layer accord- ing to some other embodiments.
FIG. 10 is a simplified schematic cross-sectional diagram illustrating a substrate structure suitable for use in the fabrication of power devices according to …
FIG. 11 is a simplified schematic cross-sectional diagram illustrating an engineered substrate structure according to an embodiment of the present invention.
FIG. 12 is a simplified schematic diagram illustrating an engineered substrate structure according to some embodi- 5 ments of the present invention.
FIG. 13 is a simplified schematic diagram illustrating an engineered substrate structure according to some other embodiments of the present invention.
FIG. 14 is a simplified schematic diagram illustrating an 10 engineered substrate structure according to some further embodiments of the present invention.
FIG. 15 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to some embodiments of the present invention. 15
FIG. 16 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate according to some embodiments of the present …
FIG. 17 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate 20 according to some other embodiments of the …
FIG. 18 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate according to some further embodiments of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An epitaxial semiconductor structure comprising: an engineered substrate having a substrate coefficient of thermal expansion, the engineered substrate compris-ing: a polycrystalline ceramic core; a barrier layer encapsulating the polycrystalline ceramic core; a bonding layer coupled to the barrier layer; and a single crystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the single crystalline silicon layer; a silicon nitride partial layer coupled to the buffer layer; and an epitaxial layer formed on the silicon nitride partial layer, wherein the epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
The epitaxial semiconductor structure of claim 1 wherein the silicon nitride partial layer comprises a partial monolayer of silicon nitride.
The epitaxial semiconductor structure of claim 1 wherein the epitaxial layer comprises gallium nitride (GaN).
An epitaxial semiconductor structure comprising: an engineered substrate characterized by a substrate coef-ficient of thermal expansion and comprising: a polycrystalline ceramic core; a barrier layer encapsulating the polycrystalline ceramic core; a bonding layer coupled to the barrier layer; and a single crystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the single crystalline silicon layer; a silicon nitride partial layer coupled to the buffer layer; and a gallium nitride (GaN) epitaxial layer formed on the silicon nitride partial layer, wherein the GaN epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
The epitaxial semiconductor structure of claim 16 further comprising one or more doped GaN layers coupled to the GaN epitaxial layer, wherein the one or more doped GaN layers are characterized by a doping density greater than 1×1016 cm⁻³.
The epitaxial semiconductor structure of claim 16 wherein the silicon nitride partial layer comprises a partial monolayer of silicon nitride.
The epitaxial semiconductor structure of claim 16 further comprising an additional silicon nitride partial layer coupled to the GaN epitaxial layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
epitaxial semiconductor structure on engineered substrate
Materials described outside the worked examples.
polycrystalline ceramic core
barrier layer (encapsulating ceramic core)
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage of GaN power device | ≥ 500 V | GaN |
background free carrier density in C-GaN or Fe-GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 19
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,699,750 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to an embodiment of …
FIG. 2 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to another …
FIG. 3 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure with a back-side contact …
FIG. 4 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure with a front-side contact …
FIG. 5 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to an embodiment of …
FIG. 6 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to another …
FIG. 7 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to a further …
FIG. 8 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to some other …
FIG. 9B illustrates an exemplary conduction band dia- gram of a HEMT with an AlGaN back barrier layer accord- ing to some other embodiments.
FIG. 10 is a simplified schematic cross-sectional diagram illustrating a substrate structure suitable for use in the fabrication of power devices according to …
FIG. 11 is a simplified schematic cross-sectional diagram illustrating an engineered substrate structure according to an embodiment of the present invention.
FIG. 12 is a simplified schematic diagram illustrating an engineered substrate structure according to some embodi- 5 ments of the present invention.
FIG. 13 is a simplified schematic diagram illustrating an engineered substrate structure according to some other embodiments of the present invention.
FIG. 14 is a simplified schematic diagram illustrating an 10 engineered substrate structure according to some further embodiments of the present invention.
FIG. 15 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to some embodiments of the present invention. 15
FIG. 16 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate according to some embodiments of the present …
FIG. 17 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate 20 according to some other embodiments of the …
FIG. 18 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate according to some further embodiments of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An epitaxial semiconductor structure comprising: an engineered substrate having a substrate coefficient of thermal expansion, the engineered substrate compris-ing: a polycrystalline ceramic core; a barrier layer encapsulating the polycrystalline ceramic core; a bonding layer coupled to the barrier layer; and a single crystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the single crystalline silicon layer; a silicon nitride partial layer coupled to the buffer layer; and an epitaxial layer formed on the silicon nitride partial layer, wherein the epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
The epitaxial semiconductor structure of claim 1 wherein the silicon nitride partial layer comprises a partial monolayer of silicon nitride.
The epitaxial semiconductor structure of claim 1 wherein the epitaxial layer comprises gallium nitride (GaN).
An epitaxial semiconductor structure comprising: an engineered substrate characterized by a substrate coef-ficient of thermal expansion and comprising: a polycrystalline ceramic core; a barrier layer encapsulating the polycrystalline ceramic core; a bonding layer coupled to the barrier layer; and a single crystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the single crystalline silicon layer; a silicon nitride partial layer coupled to the buffer layer; and a gallium nitride (GaN) epitaxial layer formed on the silicon nitride partial layer, wherein the GaN epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
The epitaxial semiconductor structure of claim 16 further comprising one or more doped GaN layers coupled to the GaN epitaxial layer, wherein the one or more doped GaN layers are characterized by a doping density greater than 1×1016 cm⁻³.
The epitaxial semiconductor structure of claim 16 wherein the silicon nitride partial layer comprises a partial monolayer of silicon nitride.
The epitaxial semiconductor structure of claim 16 further comprising an additional silicon nitride partial layer coupled to the GaN epitaxial layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
epitaxial semiconductor structure on engineered substrate
Materials described outside the worked examples.
polycrystalline ceramic core
barrier layer (encapsulating ceramic core)
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage of GaN power device | ≥ 500 V | GaN |
background free carrier density in C-GaN or Fe-GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 19
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,699,750 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to an embodiment of …
FIG. 2 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to another …
FIG. 3 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure with a back-side contact …
FIG. 4 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure with a front-side contact …
FIG. 5 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to an embodiment of …
FIG. 6 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to another …
FIG. 7 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to a further …
FIG. 8 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to some other …
FIG. 9B illustrates an exemplary conduction band dia- gram of a HEMT with an AlGaN back barrier layer accord- ing to some other embodiments.
FIG. 10 is a simplified schematic cross-sectional diagram illustrating a substrate structure suitable for use in the fabrication of power devices according to …
FIG. 11 is a simplified schematic cross-sectional diagram illustrating an engineered substrate structure according to an embodiment of the present invention.
FIG. 12 is a simplified schematic diagram illustrating an engineered substrate structure according to some embodi- 5 ments of the present invention.
FIG. 13 is a simplified schematic diagram illustrating an engineered substrate structure according to some other embodiments of the present invention.
FIG. 14 is a simplified schematic diagram illustrating an 10 engineered substrate structure according to some further embodiments of the present invention.
FIG. 15 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to some embodiments of the present invention. 15
FIG. 16 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate according to some embodiments of the present …
FIG. 17 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate 20 according to some other embodiments of the …
FIG. 18 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate according to some further embodiments of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An epitaxial semiconductor structure comprising: an engineered substrate having a substrate coefficient of thermal expansion, the engineered substrate compris-ing: a polycrystalline ceramic core; a barrier layer encapsulating the polycrystalline ceramic core; a bonding layer coupled to the barrier layer; and a single crystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the single crystalline silicon layer; a silicon nitride partial layer coupled to the buffer layer; and an epitaxial layer formed on the silicon nitride partial layer, wherein the epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
The epitaxial semiconductor structure of claim 1 wherein the silicon nitride partial layer comprises a partial monolayer of silicon nitride.
The epitaxial semiconductor structure of claim 1 wherein the epitaxial layer comprises gallium nitride (GaN).
An epitaxial semiconductor structure comprising: an engineered substrate characterized by a substrate coef-ficient of thermal expansion and comprising: a polycrystalline ceramic core; a barrier layer encapsulating the polycrystalline ceramic core; a bonding layer coupled to the barrier layer; and a single crystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the single crystalline silicon layer; a silicon nitride partial layer coupled to the buffer layer; and a gallium nitride (GaN) epitaxial layer formed on the silicon nitride partial layer, wherein the GaN epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
The epitaxial semiconductor structure of claim 16 further comprising one or more doped GaN layers coupled to the GaN epitaxial layer, wherein the one or more doped GaN layers are characterized by a doping density greater than 1×1016 cm⁻³.
The epitaxial semiconductor structure of claim 16 wherein the silicon nitride partial layer comprises a partial monolayer of silicon nitride.
The epitaxial semiconductor structure of claim 16 further comprising an additional silicon nitride partial layer coupled to the GaN epitaxial layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
epitaxial semiconductor structure on engineered substrate
Materials described outside the worked examples.
polycrystalline ceramic core
barrier layer (encapsulating ceramic core)
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage of GaN power device | ≥ 500 V | GaN |
background free carrier density in C-GaN or Fe-GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 19
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,699,750 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to an embodiment of …
FIG. 2 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to another …
FIG. 3 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure with a back-side contact …
FIG. 4 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure with a front-side contact …
FIG. 5 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to an embodiment of …
FIG. 6 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to another …
FIG. 7 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to a further …
FIG. 8 is a simplified schematic cross-sectional diagram illustrating a power device formed on an engineered sub- strate structure according to some other …
FIG. 9B illustrates an exemplary conduction band dia- gram of a HEMT with an AlGaN back barrier layer accord- ing to some other embodiments.
FIG. 10 is a simplified schematic cross-sectional diagram illustrating a substrate structure suitable for use in the fabrication of power devices according to …
FIG. 11 is a simplified schematic cross-sectional diagram illustrating an engineered substrate structure according to an embodiment of the present invention.
FIG. 12 is a simplified schematic diagram illustrating an engineered substrate structure according to some embodi- 5 ments of the present invention.
FIG. 13 is a simplified schematic diagram illustrating an engineered substrate structure according to some other embodiments of the present invention.
FIG. 14 is a simplified schematic diagram illustrating an 10 engineered substrate structure according to some further embodiments of the present invention.
FIG. 15 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to some embodiments of the present invention. 15
FIG. 16 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate according to some embodiments of the present …
FIG. 17 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate 20 according to some other embodiments of the …
FIG. 18 is a simplified flowchart illustrating a method for making a multilayered device on an engineered substrate according to some further embodiments of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An epitaxial semiconductor structure comprising: an engineered substrate having a substrate coefficient of thermal expansion, the engineered substrate compris-ing: a polycrystalline ceramic core; a barrier layer encapsulating the polycrystalline ceramic core; a bonding layer coupled to the barrier layer; and a single crystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the single crystalline silicon layer; a silicon nitride partial layer coupled to the buffer layer; and an epitaxial layer formed on the silicon nitride partial layer, wherein the epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
The epitaxial semiconductor structure of claim 1 wherein the silicon nitride partial layer comprises a partial monolayer of silicon nitride.
The epitaxial semiconductor structure of claim 1 wherein the epitaxial layer comprises gallium nitride (GaN).
An epitaxial semiconductor structure comprising: an engineered substrate characterized by a substrate coef-ficient of thermal expansion and comprising: a polycrystalline ceramic core; a barrier layer encapsulating the polycrystalline ceramic core; a bonding layer coupled to the barrier layer; and a single crystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the single crystalline silicon layer; a silicon nitride partial layer coupled to the buffer layer; and a gallium nitride (GaN) epitaxial layer formed on the silicon nitride partial layer, wherein the GaN epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
The epitaxial semiconductor structure of claim 16 further comprising one or more doped GaN layers coupled to the GaN epitaxial layer, wherein the one or more doped GaN layers are characterized by a doping density greater than 1×1016 cm⁻³.
The epitaxial semiconductor structure of claim 16 wherein the silicon nitride partial layer comprises a partial monolayer of silicon nitride.
The epitaxial semiconductor structure of claim 16 further comprising an additional silicon nitride partial layer coupled to the GaN epitaxial layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
epitaxial semiconductor structure on engineered substrate
Materials described outside the worked examples.
polycrystalline ceramic core
barrier layer (encapsulating ceramic core)
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
breakdown voltage of GaN power device | ≥ 500 V | GaN |
background free carrier density in C-GaN or Fe-GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 19
Related documents with shared materials, methods, properties, or citations.
GaN epitaxial semiconductor structure on engineered substrate
HEMT power device on engineered substrate
single crystalline silicon layer
Si
silicon nitride partial layer
Si₃N₄
buffer layer
AlN buffer layer
AlN
AlGaN buffer layer
AlGaN
gallium nitride epitaxial layer
GaN
carbon-doped GaN
GaN:C
iron-doped GaN
GaN:Fe
InAlN barrier layer
InAlN
Al0.25Ga0.75N buffer layer
Al0.25Ga0.75N
| 1e12 cm⁻³ |
GaN:C |
Thickness | 0.5–2.5 µm | — |
Thickness | 1–100 nm | — |
Thickness | 10–100 nm | — |
— | 1–4 eV | — |
— | 0.2–1.5 eV | — |
Thickness | 0.1–1 µm | — |
Thickness | 0.2–0.3 µm | — |
Thickness | 100–2000 Å | — |
Thickness | 2000–5000 Å | — |
Temperature | 800–1100 °C | — |
Thickness | 2–10 µm | — |
Thickness | 100–1500 µm | — |
Thickness | 4000–5000 Å | — |
— | 1–3 eV | — |
Thickness | 500–5000 Å | — |
Thickness | 0.75–1.5 µm | — |
Thickness | 0–0.5 µm | — |
Thickness | ≤ 0.5 µm | — |
Thickness | ≤ 0.1 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Thickness | ≥ 8 µm | — |
Voltage | ≥ 500 V | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 10 µm | — |
Cited non-patent literature · 5
GaN epitaxial semiconductor structure on engineered substrate
HEMT power device on engineered substrate
single crystalline silicon layer
Si
silicon nitride partial layer
Si₃N₄
buffer layer
AlN buffer layer
AlN
AlGaN buffer layer
AlGaN
gallium nitride epitaxial layer
GaN
carbon-doped GaN
GaN:C
iron-doped GaN
GaN:Fe
InAlN barrier layer
InAlN
Al0.25Ga0.75N buffer layer
Al0.25Ga0.75N
| 1e12 cm⁻³ |
GaN:C |
Thickness | 0.5–2.5 µm | — |
Thickness | 1–100 nm | — |
Thickness | 10–100 nm | — |
— | 1–4 eV | — |
— | 0.2–1.5 eV | — |
Thickness | 0.1–1 µm | — |
Thickness | 0.2–0.3 µm | — |
Thickness | 100–2000 Å | — |
Thickness | 2000–5000 Å | — |
Temperature | 800–1100 °C | — |
Thickness | 2–10 µm | — |
Thickness | 100–1500 µm | — |
Thickness | 4000–5000 Å | — |
— | 1–3 eV | — |
Thickness | 500–5000 Å | — |
Thickness | 0.75–1.5 µm | — |
Thickness | 0–0.5 µm | — |
Thickness | ≤ 0.5 µm | — |
Thickness | ≤ 0.1 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Thickness | ≥ 8 µm | — |
Voltage | ≥ 500 V | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 10 µm | — |
Cited non-patent literature · 5
GaN epitaxial semiconductor structure on engineered substrate
HEMT power device on engineered substrate
single crystalline silicon layer
Si
silicon nitride partial layer
Si₃N₄
buffer layer
AlN buffer layer
AlN
AlGaN buffer layer
AlGaN
gallium nitride epitaxial layer
GaN
carbon-doped GaN
GaN:C
iron-doped GaN
GaN:Fe
InAlN barrier layer
InAlN
Al0.25Ga0.75N buffer layer
Al0.25Ga0.75N
| 1e12 cm⁻³ |
GaN:C |
Thickness | 0.5–2.5 µm | — |
Thickness | 1–100 nm | — |
Thickness | 10–100 nm | — |
— | 1–4 eV | — |
— | 0.2–1.5 eV | — |
Thickness | 0.1–1 µm | — |
Thickness | 0.2–0.3 µm | — |
Thickness | 100–2000 Å | — |
Thickness | 2000–5000 Å | — |
Temperature | 800–1100 °C | — |
Thickness | 2–10 µm | — |
Thickness | 100–1500 µm | — |
Thickness | 4000–5000 Å | — |
— | 1–3 eV | — |
Thickness | 500–5000 Å | — |
Thickness | 0.75–1.5 µm | — |
Thickness | 0–0.5 µm | — |
Thickness | ≤ 0.5 µm | — |
Thickness | ≤ 0.1 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Thickness | ≥ 8 µm | — |
Voltage | ≥ 500 V | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 10 µm | — |
Cited non-patent literature · 5
GaN epitaxial semiconductor structure on engineered substrate
HEMT power device on engineered substrate
single crystalline silicon layer
Si
silicon nitride partial layer
Si₃N₄
buffer layer
AlN buffer layer
AlN
AlGaN buffer layer
AlGaN
gallium nitride epitaxial layer
GaN
carbon-doped GaN
GaN:C
iron-doped GaN
GaN:Fe
InAlN barrier layer
InAlN
Al0.25Ga0.75N buffer layer
Al0.25Ga0.75N
| 1e12 cm⁻³ |
GaN:C |
Thickness | 0.5–2.5 µm | — |
Thickness | 1–100 nm | — |
Thickness | 10–100 nm | — |
— | 1–4 eV | — |
— | 0.2–1.5 eV | — |
Thickness | 0.1–1 µm | — |
Thickness | 0.2–0.3 µm | — |
Thickness | 100–2000 Å | — |
Thickness | 2000–5000 Å | — |
Temperature | 800–1100 °C | — |
Thickness | 2–10 µm | — |
Thickness | 100–1500 µm | — |
Thickness | 4000–5000 Å | — |
— | 1–3 eV | — |
Thickness | 500–5000 Å | — |
Thickness | 0.75–1.5 µm | — |
Thickness | 0–0.5 µm | — |
Thickness | ≤ 0.5 µm | — |
Thickness | ≤ 0.1 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Thickness | ≥ 8 µm | — |
Voltage | ≥ 500 V | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 10 µm | — |
Cited non-patent literature · 5