Patent
US 12,051,742 B1ENHANCEMENT-MODE N-CHANNEL AND P-CHANNEL GAN DEVICE INTEGRATION STRUCTURE
Long Zhang, Weifeng Sun, Siyang Liu, Jie Ma et al.
SOUTHEAST UNIVERSITY, Nanjing (CN)·Jul. 30, 2024·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 12,051,742 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a traditional N-channel and P-channel GaN power device integration structure.
FIG. 2 is a schematic diagram of an embodiment of an enhancement-mode N-channel and P-channel GaN device integration structure according to the invention; 50
FIG. 3 is a data comparison diagram of a P-channel device based on the structure in an embodiment of the invention and a P-channel device based on the …
FIG. 4 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure in an embodiment of the invention and an output …
FIG. 5 is a data comparison diagram of the P-channel device based on the structure without an Al—N insertion layer in an embodiment of the invention and the …
FIG. 6 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure without the Al—N insertion layer in an …
FIG. 7 is a comparison diagram of a transfer characteristic curve of an N-channel device based on the structure in an embodiment of the invention and a …
FIG. 8 is a comparison diagram of an output characteristic curve of the N-channel device based on the structure in an embodiment of the invention and an output …
FIG. 9 is a comparison diagram of an energy band of the gate region and an energy band of a region between the gate region and a drain region of the P-channel …
FIG. 10 is a comparison diagram of an energy band of the gate region and an energy band of a region between the gate region and a drain region of the P-channel …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An enhancement-mode N-channel and P-channel GaN device integration structure, comprising; a substrate, an Al—N nucleating layer being arranged on the substrate, an AlGaN buffer layer being arranged on the Al—N nucleating layer, a GaN channel layer being arranged on the AlGaN buffer layer, and an AlGaN barrier layer being arranged on the GaN channel layer, wherein an isolation layer is arranged in the AlGaN barrier layer and extends into the GaN channel layer, and the isolation layer divides the AlGaN barrier layer and the GaN channel layer into two parts; and a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer arranged on the AlGaN barrier layer on one side of the isolation layer, a first GaN isolation layer is arranged on the first P-GaN layer, a first P+-GaN layer is arranged on the first GaN isolation layer, a first source, first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-type channel device is arranged on the other side of the isolation layer and comprises a second source, a second P-GaN layer and a second drain which are arranged on the AlGaN barrier layer on the other side of the isolation layer, the second source and the second drain are located on two sides of the second P-GaN layer respectively, a second GaN isolation layer is arranged above the second P-GaN layer, a second P+-GaN layer is arranged above the 10 second GaN isolation layer, and a second gate is arranged above the second P+-GaN layer.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the first gate and the gate dielectric layer extend towards the first GaN isolation layer and enters the first GaN isolation layer, an Al—N insertion layer is arranged on a lower surface of the gate dielectric layer and located below the first gate, and the gate dielectric layer further extends and wraps around a side face of the Al—N insertion layer.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the first P-GaN layer and the second P-GaN layer have a thickness of 10-15 nm and a doping concentration of 1.0× 1018/cm3-1.0×1019/cm3; the first GaN isolation layer and the second GaN isolation layer have a thickness of 30-40 nm and a doping concentration of 1.0×1014/cm3-1.0×1016/cm3; and the first P+-GaN layer and the second P+-GaN layer have a thickness of 20-35 nm and a doping concentration of 1.0×1019/cm3-1.0×1020/cm3, and a dopant is Mg or Be.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the gate dielectric layer has a thickness of 5-10 nm and is made from aluminum oxide, silicon oxide, or silicon nitride. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
enhancement-mode N-channel and P-channel GaN device integration structure
Materials described outside the worked examples.
Al-N nucleating layer
AlN
AlGaN buffer layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure in an embodiment of the invention and an output …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
AlGaN barrier layer thickness | 12–25 nm | AlGaN |
P-GaN layer thickness | 10–15 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,051,742 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a traditional N-channel and P-channel GaN power device integration structure.
FIG. 2 is a schematic diagram of an embodiment of an enhancement-mode N-channel and P-channel GaN device integration structure according to the invention; 50
FIG. 3 is a data comparison diagram of a P-channel device based on the structure in an embodiment of the invention and a P-channel device based on the …
FIG. 4 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure in an embodiment of the invention and an output …
FIG. 5 is a data comparison diagram of the P-channel device based on the structure without an Al—N insertion layer in an embodiment of the invention and the …
FIG. 6 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure without the Al—N insertion layer in an …
FIG. 7 is a comparison diagram of a transfer characteristic curve of an N-channel device based on the structure in an embodiment of the invention and a …
FIG. 8 is a comparison diagram of an output characteristic curve of the N-channel device based on the structure in an embodiment of the invention and an output …
FIG. 9 is a comparison diagram of an energy band of the gate region and an energy band of a region between the gate region and a drain region of the P-channel …
FIG. 10 is a comparison diagram of an energy band of the gate region and an energy band of a region between the gate region and a drain region of the P-channel …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An enhancement-mode N-channel and P-channel GaN device integration structure, comprising; a substrate, an Al—N nucleating layer being arranged on the substrate, an AlGaN buffer layer being arranged on the Al—N nucleating layer, a GaN channel layer being arranged on the AlGaN buffer layer, and an AlGaN barrier layer being arranged on the GaN channel layer, wherein an isolation layer is arranged in the AlGaN barrier layer and extends into the GaN channel layer, and the isolation layer divides the AlGaN barrier layer and the GaN channel layer into two parts; and a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer arranged on the AlGaN barrier layer on one side of the isolation layer, a first GaN isolation layer is arranged on the first P-GaN layer, a first P+-GaN layer is arranged on the first GaN isolation layer, a first source, first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-type channel device is arranged on the other side of the isolation layer and comprises a second source, a second P-GaN layer and a second drain which are arranged on the AlGaN barrier layer on the other side of the isolation layer, the second source and the second drain are located on two sides of the second P-GaN layer respectively, a second GaN isolation layer is arranged above the second P-GaN layer, a second P+-GaN layer is arranged above the 10 second GaN isolation layer, and a second gate is arranged above the second P+-GaN layer.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the first gate and the gate dielectric layer extend towards the first GaN isolation layer and enters the first GaN isolation layer, an Al—N insertion layer is arranged on a lower surface of the gate dielectric layer and located below the first gate, and the gate dielectric layer further extends and wraps around a side face of the Al—N insertion layer.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the first P-GaN layer and the second P-GaN layer have a thickness of 10-15 nm and a doping concentration of 1.0× 1018/cm3-1.0×1019/cm3; the first GaN isolation layer and the second GaN isolation layer have a thickness of 30-40 nm and a doping concentration of 1.0×1014/cm3-1.0×1016/cm3; and the first P+-GaN layer and the second P+-GaN layer have a thickness of 20-35 nm and a doping concentration of 1.0×1019/cm3-1.0×1020/cm3, and a dopant is Mg or Be.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the gate dielectric layer has a thickness of 5-10 nm and is made from aluminum oxide, silicon oxide, or silicon nitride. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
enhancement-mode N-channel and P-channel GaN device integration structure
Materials described outside the worked examples.
Al-N nucleating layer
AlN
AlGaN buffer layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure in an embodiment of the invention and an output …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
AlGaN barrier layer thickness | 12–25 nm | AlGaN |
P-GaN layer thickness | 10–15 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,051,742 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a traditional N-channel and P-channel GaN power device integration structure.
FIG. 2 is a schematic diagram of an embodiment of an enhancement-mode N-channel and P-channel GaN device integration structure according to the invention; 50
FIG. 3 is a data comparison diagram of a P-channel device based on the structure in an embodiment of the invention and a P-channel device based on the …
FIG. 4 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure in an embodiment of the invention and an output …
FIG. 5 is a data comparison diagram of the P-channel device based on the structure without an Al—N insertion layer in an embodiment of the invention and the …
FIG. 6 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure without the Al—N insertion layer in an …
FIG. 7 is a comparison diagram of a transfer characteristic curve of an N-channel device based on the structure in an embodiment of the invention and a …
FIG. 8 is a comparison diagram of an output characteristic curve of the N-channel device based on the structure in an embodiment of the invention and an output …
FIG. 9 is a comparison diagram of an energy band of the gate region and an energy band of a region between the gate region and a drain region of the P-channel …
FIG. 10 is a comparison diagram of an energy band of the gate region and an energy band of a region between the gate region and a drain region of the P-channel …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An enhancement-mode N-channel and P-channel GaN device integration structure, comprising; a substrate, an Al—N nucleating layer being arranged on the substrate, an AlGaN buffer layer being arranged on the Al—N nucleating layer, a GaN channel layer being arranged on the AlGaN buffer layer, and an AlGaN barrier layer being arranged on the GaN channel layer, wherein an isolation layer is arranged in the AlGaN barrier layer and extends into the GaN channel layer, and the isolation layer divides the AlGaN barrier layer and the GaN channel layer into two parts; and a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer arranged on the AlGaN barrier layer on one side of the isolation layer, a first GaN isolation layer is arranged on the first P-GaN layer, a first P+-GaN layer is arranged on the first GaN isolation layer, a first source, first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-type channel device is arranged on the other side of the isolation layer and comprises a second source, a second P-GaN layer and a second drain which are arranged on the AlGaN barrier layer on the other side of the isolation layer, the second source and the second drain are located on two sides of the second P-GaN layer respectively, a second GaN isolation layer is arranged above the second P-GaN layer, a second P+-GaN layer is arranged above the 10 second GaN isolation layer, and a second gate is arranged above the second P+-GaN layer.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the first gate and the gate dielectric layer extend towards the first GaN isolation layer and enters the first GaN isolation layer, an Al—N insertion layer is arranged on a lower surface of the gate dielectric layer and located below the first gate, and the gate dielectric layer further extends and wraps around a side face of the Al—N insertion layer.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the first P-GaN layer and the second P-GaN layer have a thickness of 10-15 nm and a doping concentration of 1.0× 1018/cm3-1.0×1019/cm3; the first GaN isolation layer and the second GaN isolation layer have a thickness of 30-40 nm and a doping concentration of 1.0×1014/cm3-1.0×1016/cm3; and the first P+-GaN layer and the second P+-GaN layer have a thickness of 20-35 nm and a doping concentration of 1.0×1019/cm3-1.0×1020/cm3, and a dopant is Mg or Be.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the gate dielectric layer has a thickness of 5-10 nm and is made from aluminum oxide, silicon oxide, or silicon nitride. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
enhancement-mode N-channel and P-channel GaN device integration structure
Materials described outside the worked examples.
Al-N nucleating layer
AlN
AlGaN buffer layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure in an embodiment of the invention and an output …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
AlGaN barrier layer thickness | 12–25 nm | AlGaN |
P-GaN layer thickness | 10–15 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,051,742 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic diagram of a traditional N-channel and P-channel GaN power device integration structure.
FIG. 2 is a schematic diagram of an embodiment of an enhancement-mode N-channel and P-channel GaN device integration structure according to the invention; 50
FIG. 3 is a data comparison diagram of a P-channel device based on the structure in an embodiment of the invention and a P-channel device based on the …
FIG. 4 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure in an embodiment of the invention and an output …
FIG. 5 is a data comparison diagram of the P-channel device based on the structure without an Al—N insertion layer in an embodiment of the invention and the …
FIG. 6 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure without the Al—N insertion layer in an …
FIG. 7 is a comparison diagram of a transfer characteristic curve of an N-channel device based on the structure in an embodiment of the invention and a …
FIG. 8 is a comparison diagram of an output characteristic curve of the N-channel device based on the structure in an embodiment of the invention and an output …
FIG. 9 is a comparison diagram of an energy band of the gate region and an energy band of a region between the gate region and a drain region of the P-channel …
FIG. 10 is a comparison diagram of an energy band of the gate region and an energy band of a region between the gate region and a drain region of the P-channel …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An enhancement-mode N-channel and P-channel GaN device integration structure, comprising; a substrate, an Al—N nucleating layer being arranged on the substrate, an AlGaN buffer layer being arranged on the Al—N nucleating layer, a GaN channel layer being arranged on the AlGaN buffer layer, and an AlGaN barrier layer being arranged on the GaN channel layer, wherein an isolation layer is arranged in the AlGaN barrier layer and extends into the GaN channel layer, and the isolation layer divides the AlGaN barrier layer and the GaN channel layer into two parts; and a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer arranged on the AlGaN barrier layer on one side of the isolation layer, a first GaN isolation layer is arranged on the first P-GaN layer, a first P+-GaN layer is arranged on the first GaN isolation layer, a first source, first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-type channel device is arranged on the other side of the isolation layer and comprises a second source, a second P-GaN layer and a second drain which are arranged on the AlGaN barrier layer on the other side of the isolation layer, the second source and the second drain are located on two sides of the second P-GaN layer respectively, a second GaN isolation layer is arranged above the second P-GaN layer, a second P+-GaN layer is arranged above the 10 second GaN isolation layer, and a second gate is arranged above the second P+-GaN layer.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the first gate and the gate dielectric layer extend towards the first GaN isolation layer and enters the first GaN isolation layer, an Al—N insertion layer is arranged on a lower surface of the gate dielectric layer and located below the first gate, and the gate dielectric layer further extends and wraps around a side face of the Al—N insertion layer.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the first P-GaN layer and the second P-GaN layer have a thickness of 10-15 nm and a doping concentration of 1.0× 1018/cm3-1.0×1019/cm3; the first GaN isolation layer and the second GaN isolation layer have a thickness of 30-40 nm and a doping concentration of 1.0×1014/cm3-1.0×1016/cm3; and the first P+-GaN layer and the second P+-GaN layer have a thickness of 20-35 nm and a doping concentration of 1.0×1019/cm3-1.0×1020/cm3, and a dopant is Mg or Be.
The enhancement-mode N-channel and P-channel GaN device integration structure according to claim 1, wherein the gate dielectric layer has a thickness of 5-10 nm and is made from aluminum oxide, silicon oxide, or silicon nitride. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
enhancement-mode N-channel and P-channel GaN device integration structure
Materials described outside the worked examples.
Al-N nucleating layer
AlN
AlGaN buffer layer
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure in an embodiment of the invention and an output …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
AlGaN barrier layer thickness | 12–25 nm | AlGaN |
P-GaN layer thickness | 10–15 nm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
Related documents with shared materials, methods, properties, or citations.
GaN channel layer
GaN
gate dielectric layer
aluminum oxide gate dielectric
Al₂O₃
silicon oxide gate dielectric
SiO₂
silicon nitride gate dielectric
Si₃N₄
substrate
FIG. 6 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure without the Al—N insertion layer in an …
FIG. 8 is a comparison diagram of an output characteristic curve of the N-channel device based on the structure in an embodiment of the invention and an output …
P-GaN layer doping concentration | 1000000000000000000–10000000000000000000 cm⁻³ | GaN |
GaN isolation layer thickness | 30–40 nm | GaN |
GaN isolation layer doping concentration | 100000000000000–10000000000000000 cm⁻³ | GaN |
P+-GaN layer thickness | 20–35 nm | GaN |
P+-GaN layer doping concentration | 10000000000000000000–100000000000000000000 cm⁻³ | GaN |
gate dielectric layer thickness | 5–10 nm | gate dielectric layer |
Al-N insertion layer thickness | 5–15 nm | AlN |
sum of first GaN isolation layer and first P-GaN layer thickness | 20–50 nm | — |
Thickness | 8–15 nm | — |
N-CHANNEL GALLIUM NITRIDE TRANSISTORS
GaN channel layer
GaN
gate dielectric layer
aluminum oxide gate dielectric
Al₂O₃
silicon oxide gate dielectric
SiO₂
silicon nitride gate dielectric
Si₃N₄
substrate
FIG. 6 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure without the Al—N insertion layer in an …
FIG. 8 is a comparison diagram of an output characteristic curve of the N-channel device based on the structure in an embodiment of the invention and an output …
P-GaN layer doping concentration | 1000000000000000000–10000000000000000000 cm⁻³ | GaN |
GaN isolation layer thickness | 30–40 nm | GaN |
GaN isolation layer doping concentration | 100000000000000–10000000000000000 cm⁻³ | GaN |
P+-GaN layer thickness | 20–35 nm | GaN |
P+-GaN layer doping concentration | 10000000000000000000–100000000000000000000 cm⁻³ | GaN |
gate dielectric layer thickness | 5–10 nm | gate dielectric layer |
Al-N insertion layer thickness | 5–15 nm | AlN |
sum of first GaN isolation layer and first P-GaN layer thickness | 20–50 nm | — |
Thickness | 8–15 nm | — |
N-CHANNEL GALLIUM NITRIDE TRANSISTORS
GaN channel layer
GaN
gate dielectric layer
aluminum oxide gate dielectric
Al₂O₃
silicon oxide gate dielectric
SiO₂
silicon nitride gate dielectric
Si₃N₄
substrate
FIG. 6 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure without the Al—N insertion layer in an …
FIG. 8 is a comparison diagram of an output characteristic curve of the N-channel device based on the structure in an embodiment of the invention and an output …
P-GaN layer doping concentration | 1000000000000000000–10000000000000000000 cm⁻³ | GaN |
GaN isolation layer thickness | 30–40 nm | GaN |
GaN isolation layer doping concentration | 100000000000000–10000000000000000 cm⁻³ | GaN |
P+-GaN layer thickness | 20–35 nm | GaN |
P+-GaN layer doping concentration | 10000000000000000000–100000000000000000000 cm⁻³ | GaN |
gate dielectric layer thickness | 5–10 nm | gate dielectric layer |
Al-N insertion layer thickness | 5–15 nm | AlN |
sum of first GaN isolation layer and first P-GaN layer thickness | 20–50 nm | — |
Thickness | 8–15 nm | — |
N-CHANNEL GALLIUM NITRIDE TRANSISTORS
GaN channel layer
GaN
gate dielectric layer
aluminum oxide gate dielectric
Al₂O₃
silicon oxide gate dielectric
SiO₂
silicon nitride gate dielectric
Si₃N₄
substrate
FIG. 6 is a comparison diagram of an output characteristic curve of the P-channel device based on the structure without the Al—N insertion layer in an …
FIG. 8 is a comparison diagram of an output characteristic curve of the N-channel device based on the structure in an embodiment of the invention and an output …
P-GaN layer doping concentration | 1000000000000000000–10000000000000000000 cm⁻³ | GaN |
GaN isolation layer thickness | 30–40 nm | GaN |
GaN isolation layer doping concentration | 100000000000000–10000000000000000 cm⁻³ | GaN |
P+-GaN layer thickness | 20–35 nm | GaN |
P+-GaN layer doping concentration | 10000000000000000000–100000000000000000000 cm⁻³ | GaN |
gate dielectric layer thickness | 5–10 nm | gate dielectric layer |
Al-N insertion layer thickness | 5–15 nm | AlN |
sum of first GaN isolation layer and first P-GaN layer thickness | 20–50 nm | — |
Thickness | 8–15 nm | — |