Patent
US 8,653,559AlGaN/GaN HYBRID MOS-HFET
Andrea Corrion
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,653,559Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an elevation sectional view of a hybrid MOS-HFET with a layer used as both a gate dielectric and a passivation layer in accordance with the prior …
FIG. 2 shows an elevation sectional view of a hybrid MOS-HFET in accordance with the present disclosure; [0012]
FIG. 3 shows transfer curves comparing characteristics with and without a post deposition anneal (PDA) of the A 120 3 gate dielectric for a hybrid MOS-HFET in …
FIG. 4 shows a 200ns pulsed common-source current voltage measurement of an annealed A 120 3 hybrid MOS-HFET in accordance with the present disclosure; [0014]
FIG. 5 shows a common-source DC current voltage and zero-bias breakdown measurement of an annealed A 120 3 hybrid MOS-HFET in accordance with the present …
FIG. 6 shows a comparison of a prior art normally- off GaN power device with a hybrid MOS-HFET in accordance with the present disclosure; [0016]
FIG. 7 shows a common-source DC current voltage measurement of an annealed hybrid A 120 3 MOS-HFET with a gate periphery of 20mm with the gate biased from + 3V …
FIG. 8 is a flow diagram of a method of fabricating a hybrid MOS-HFET in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET) comprising: a source electrode; a drain electrode; a channel layer; a barrier layer over the channel layer and coupled to the source and drain electrodes; a gate electrode extending through the barrier layer; a passivation layer over the barrier layer for passivati ng the barrier layer between the gate electrode and the source electrode and between the gate electrode and the drain electrode, wherein the gate electrode extends through the passivation layer; a gate eletrode exte nding through the barrier lay er an d the pass iva tio n lay er; and a gate dielectric surrounding the portion of the gate electrode that extends through the barrier layer and the passivation layer; wherein the gate dielectric is annealed to improve an interface between the gate dielectric and the channel layer for reducing electron trap density and increasing channel mobility; wherein the passivation layer is a first material and the gate dielectric is a second material; and wherein the first material is different than the second material.
Preliminary amendment 3 2. The FET of claim 1 wherein: the channel layer is GaN, InN, or InGaN; the barrier layer is AlGaN, AlN, AlInN, a combination of AlN spacer and AlGaN barrier, or a combination of AlN spacer and InAlN barrier; the passivation layer is SiN, Si O2, A₁ 203, Hf 0 2, Ti O2, amorphous A l N, or polycrystalline A lN; the gate dielectric is A 1 203, hafnium oxide (Hf 0 2), titanium oxide (Ti O 2), SiN, Si O 2, amorphous A l N, or polycrystalline A lN.
The FET of claim 1 wherein: the gate dielectric is formed using atomic layer deposition a first pr c.o and the pasivation layer is formed using a second proceo.; where in the first pro cc. and the accond process are diff ere nt.
The FET of claim 1 wherein: the gate dielectric is formed using atomic layer depos iti on; and the passivation layer is formed using plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOV C D), atomic layer deposition (ALD), molecular beam epitaxy (MBE), e-beam evaporation, or sputtering.
The FET of claim 1 wherein the gate dielectric covers the passivation layer.
The FET of claim 1 wherein: Preliminary amendment 4 the barrier layer is annealed etched away to the channel layer in a region of the gate electrode using atomic layer etching (ALE).
The FET of claim 1 wherein: the passivation layer is in the range of 20 to 100 nm thick; and the gate dielectric is in the range of 2-20 nm thick.
The FET of claim 1 wherein the figure of merit Vb₂/Ron,sp is approximately 260 MW/cm2.
The FET of claim 1 wherein the channel layer further comprises a polarization induced 2DEG away from the gate electrode.
The FET of claim 1 wherein the FET is normally- off when the gate electrode is at zero bias.
The FET of claim 1 wherein the FET is a hybrid MOS-HFET.
The FET of claim 1 wherein a periphery of the gate is between 200 1i m to 20mm.
A method of fabricating a field effect transistor comprising: forming a channel layer; forming a barrier layer over the channel layer; forming a passivation layer over the barrier layer; Preliminary amendment 5 etching away a first area of the passivation layer for a source electrode and a second area of the passivation layer for a drain electrode; forming a source electrode and a drain electrode on the barrier layer; etching away a third area of the passivation layer and a fourth area extending through the barrier layer for a gate electrode; forming a gate dielectric on the surface of the third area and the fourth area; annealing the gate dielectric; and forming a gate electrode in the third area and in the fourth area; wherein the passivation layer is a first material and the gate dielectric is a second material; and wherein the first material is different than the second material.
The method of claim 13 wherein: the channel layer is GaN, InN, or InGaN; the barrier layer is AlGaN, AlN, AlInN, a combination of AlN spacer and AlGaN barrier, or a combination of AlN spacer and InAlN barrier; the passivation layer is SiN, Si O2, A₁ 203, Hf 0 2, Ti O2, amorphous A l N, or polycrystalline A lN; the gate dielectric is A 1 203, hafnium oxide (Hf 0 2), titanium oxide (Ti O 2), SiN, Si O 2, amorphous A l N, or polycrystalline A lN.
The method of claim 13 wherein: the gate dielectric is formed using atomic layer deposition a first proccoo; and the pa ss ivation lay e r i s form e d u s ing a se cond proc coo; Preliminary amendment 6 where in the fi rst proes a nd the and pro e are diff oro nt.
The method of claim 13 wherein: the gate dielectric is formed using atomic layer depos iti on; and the passivation layer is formed using plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOV C D), atomic layer deposition (ALD), molecular beam epitaxy (MBE), e-beam evaporation, or sputtering.
The method of claim 13 wherein the gate dielectric covers the passivation layer.
The method of claim 13 wheein further c omp r isi ng etching the barrier layer is annealed to the channel layer in the fourth area using atomic layer etching (ALE).
The method of claim 13 wherein: the passivation layer is in the range of 20 to 100 nm thick; and the gate dielectric is in the range of 2-20 nm thick.
The method of claim 13 wherein the figure of merit Vb₂/Ron is approximately 260 MW/cm2.
The method of claim 13 wherein the channel layer further comprises a polarization induced 2DEG away from the gate electrode.
Preliminary amendment 7 22. The method of claim 13 wherein the FET is normally-off when the gate electrode is at zero bias.
The method of claim 13 wherein the FET is a hybrid MOS-HFET.
The method of claim 13 wherein etching away a third area of the passivation layer and a fourth area extending through the barrier layer for a gate electrode comprises atomic layer etching.
Layer stacks claimed or described, ordered top of device to substrate.
hybrid MOS-HFET (field effect transistor)
Materials described outside the worked examples.
channel layer
barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 shows transfer curves comparing characteristics with and without a post deposition anneal (PDA) of the A 120 3 gate dielectric for a hybrid MOS-HFET in …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Vb2/Ron,sp figure of merit | 260 MW/cm2 | — |
passivation layer thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,653,559Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an elevation sectional view of a hybrid MOS-HFET with a layer used as both a gate dielectric and a passivation layer in accordance with the prior …
FIG. 2 shows an elevation sectional view of a hybrid MOS-HFET in accordance with the present disclosure; [0012]
FIG. 3 shows transfer curves comparing characteristics with and without a post deposition anneal (PDA) of the A 120 3 gate dielectric for a hybrid MOS-HFET in …
FIG. 4 shows a 200ns pulsed common-source current voltage measurement of an annealed A 120 3 hybrid MOS-HFET in accordance with the present disclosure; [0014]
FIG. 5 shows a common-source DC current voltage and zero-bias breakdown measurement of an annealed A 120 3 hybrid MOS-HFET in accordance with the present …
FIG. 6 shows a comparison of a prior art normally- off GaN power device with a hybrid MOS-HFET in accordance with the present disclosure; [0016]
FIG. 7 shows a common-source DC current voltage measurement of an annealed hybrid A 120 3 MOS-HFET with a gate periphery of 20mm with the gate biased from + 3V …
FIG. 8 is a flow diagram of a method of fabricating a hybrid MOS-HFET in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET) comprising: a source electrode; a drain electrode; a channel layer; a barrier layer over the channel layer and coupled to the source and drain electrodes; a gate electrode extending through the barrier layer; a passivation layer over the barrier layer for passivati ng the barrier layer between the gate electrode and the source electrode and between the gate electrode and the drain electrode, wherein the gate electrode extends through the passivation layer; a gate eletrode exte nding through the barrier lay er an d the pass iva tio n lay er; and a gate dielectric surrounding the portion of the gate electrode that extends through the barrier layer and the passivation layer; wherein the gate dielectric is annealed to improve an interface between the gate dielectric and the channel layer for reducing electron trap density and increasing channel mobility; wherein the passivation layer is a first material and the gate dielectric is a second material; and wherein the first material is different than the second material.
Preliminary amendment 3 2. The FET of claim 1 wherein: the channel layer is GaN, InN, or InGaN; the barrier layer is AlGaN, AlN, AlInN, a combination of AlN spacer and AlGaN barrier, or a combination of AlN spacer and InAlN barrier; the passivation layer is SiN, Si O2, A₁ 203, Hf 0 2, Ti O2, amorphous A l N, or polycrystalline A lN; the gate dielectric is A 1 203, hafnium oxide (Hf 0 2), titanium oxide (Ti O 2), SiN, Si O 2, amorphous A l N, or polycrystalline A lN.
The FET of claim 1 wherein: the gate dielectric is formed using atomic layer deposition a first pr c.o and the pasivation layer is formed using a second proceo.; where in the first pro cc. and the accond process are diff ere nt.
The FET of claim 1 wherein: the gate dielectric is formed using atomic layer depos iti on; and the passivation layer is formed using plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOV C D), atomic layer deposition (ALD), molecular beam epitaxy (MBE), e-beam evaporation, or sputtering.
The FET of claim 1 wherein the gate dielectric covers the passivation layer.
The FET of claim 1 wherein: Preliminary amendment 4 the barrier layer is annealed etched away to the channel layer in a region of the gate electrode using atomic layer etching (ALE).
The FET of claim 1 wherein: the passivation layer is in the range of 20 to 100 nm thick; and the gate dielectric is in the range of 2-20 nm thick.
The FET of claim 1 wherein the figure of merit Vb₂/Ron,sp is approximately 260 MW/cm2.
The FET of claim 1 wherein the channel layer further comprises a polarization induced 2DEG away from the gate electrode.
The FET of claim 1 wherein the FET is normally- off when the gate electrode is at zero bias.
The FET of claim 1 wherein the FET is a hybrid MOS-HFET.
The FET of claim 1 wherein a periphery of the gate is between 200 1i m to 20mm.
A method of fabricating a field effect transistor comprising: forming a channel layer; forming a barrier layer over the channel layer; forming a passivation layer over the barrier layer; Preliminary amendment 5 etching away a first area of the passivation layer for a source electrode and a second area of the passivation layer for a drain electrode; forming a source electrode and a drain electrode on the barrier layer; etching away a third area of the passivation layer and a fourth area extending through the barrier layer for a gate electrode; forming a gate dielectric on the surface of the third area and the fourth area; annealing the gate dielectric; and forming a gate electrode in the third area and in the fourth area; wherein the passivation layer is a first material and the gate dielectric is a second material; and wherein the first material is different than the second material.
The method of claim 13 wherein: the channel layer is GaN, InN, or InGaN; the barrier layer is AlGaN, AlN, AlInN, a combination of AlN spacer and AlGaN barrier, or a combination of AlN spacer and InAlN barrier; the passivation layer is SiN, Si O2, A₁ 203, Hf 0 2, Ti O2, amorphous A l N, or polycrystalline A lN; the gate dielectric is A 1 203, hafnium oxide (Hf 0 2), titanium oxide (Ti O 2), SiN, Si O 2, amorphous A l N, or polycrystalline A lN.
The method of claim 13 wherein: the gate dielectric is formed using atomic layer deposition a first proccoo; and the pa ss ivation lay e r i s form e d u s ing a se cond proc coo; Preliminary amendment 6 where in the fi rst proes a nd the and pro e are diff oro nt.
The method of claim 13 wherein: the gate dielectric is formed using atomic layer depos iti on; and the passivation layer is formed using plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOV C D), atomic layer deposition (ALD), molecular beam epitaxy (MBE), e-beam evaporation, or sputtering.
The method of claim 13 wherein the gate dielectric covers the passivation layer.
The method of claim 13 wheein further c omp r isi ng etching the barrier layer is annealed to the channel layer in the fourth area using atomic layer etching (ALE).
The method of claim 13 wherein: the passivation layer is in the range of 20 to 100 nm thick; and the gate dielectric is in the range of 2-20 nm thick.
The method of claim 13 wherein the figure of merit Vb₂/Ron is approximately 260 MW/cm2.
The method of claim 13 wherein the channel layer further comprises a polarization induced 2DEG away from the gate electrode.
Preliminary amendment 7 22. The method of claim 13 wherein the FET is normally-off when the gate electrode is at zero bias.
The method of claim 13 wherein the FET is a hybrid MOS-HFET.
The method of claim 13 wherein etching away a third area of the passivation layer and a fourth area extending through the barrier layer for a gate electrode comprises atomic layer etching.
Layer stacks claimed or described, ordered top of device to substrate.
hybrid MOS-HFET (field effect transistor)
Materials described outside the worked examples.
channel layer
barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 shows transfer curves comparing characteristics with and without a post deposition anneal (PDA) of the A 120 3 gate dielectric for a hybrid MOS-HFET in …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Vb2/Ron,sp figure of merit | 260 MW/cm2 | — |
passivation layer thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,653,559Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an elevation sectional view of a hybrid MOS-HFET with a layer used as both a gate dielectric and a passivation layer in accordance with the prior …
FIG. 2 shows an elevation sectional view of a hybrid MOS-HFET in accordance with the present disclosure; [0012]
FIG. 3 shows transfer curves comparing characteristics with and without a post deposition anneal (PDA) of the A 120 3 gate dielectric for a hybrid MOS-HFET in …
FIG. 4 shows a 200ns pulsed common-source current voltage measurement of an annealed A 120 3 hybrid MOS-HFET in accordance with the present disclosure; [0014]
FIG. 5 shows a common-source DC current voltage and zero-bias breakdown measurement of an annealed A 120 3 hybrid MOS-HFET in accordance with the present …
FIG. 6 shows a comparison of a prior art normally- off GaN power device with a hybrid MOS-HFET in accordance with the present disclosure; [0016]
FIG. 7 shows a common-source DC current voltage measurement of an annealed hybrid A 120 3 MOS-HFET with a gate periphery of 20mm with the gate biased from + 3V …
FIG. 8 is a flow diagram of a method of fabricating a hybrid MOS-HFET in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET) comprising: a source electrode; a drain electrode; a channel layer; a barrier layer over the channel layer and coupled to the source and drain electrodes; a gate electrode extending through the barrier layer; a passivation layer over the barrier layer for passivati ng the barrier layer between the gate electrode and the source electrode and between the gate electrode and the drain electrode, wherein the gate electrode extends through the passivation layer; a gate eletrode exte nding through the barrier lay er an d the pass iva tio n lay er; and a gate dielectric surrounding the portion of the gate electrode that extends through the barrier layer and the passivation layer; wherein the gate dielectric is annealed to improve an interface between the gate dielectric and the channel layer for reducing electron trap density and increasing channel mobility; wherein the passivation layer is a first material and the gate dielectric is a second material; and wherein the first material is different than the second material.
Preliminary amendment 3 2. The FET of claim 1 wherein: the channel layer is GaN, InN, or InGaN; the barrier layer is AlGaN, AlN, AlInN, a combination of AlN spacer and AlGaN barrier, or a combination of AlN spacer and InAlN barrier; the passivation layer is SiN, Si O2, A₁ 203, Hf 0 2, Ti O2, amorphous A l N, or polycrystalline A lN; the gate dielectric is A 1 203, hafnium oxide (Hf 0 2), titanium oxide (Ti O 2), SiN, Si O 2, amorphous A l N, or polycrystalline A lN.
The FET of claim 1 wherein: the gate dielectric is formed using atomic layer deposition a first pr c.o and the pasivation layer is formed using a second proceo.; where in the first pro cc. and the accond process are diff ere nt.
The FET of claim 1 wherein: the gate dielectric is formed using atomic layer depos iti on; and the passivation layer is formed using plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOV C D), atomic layer deposition (ALD), molecular beam epitaxy (MBE), e-beam evaporation, or sputtering.
The FET of claim 1 wherein the gate dielectric covers the passivation layer.
The FET of claim 1 wherein: Preliminary amendment 4 the barrier layer is annealed etched away to the channel layer in a region of the gate electrode using atomic layer etching (ALE).
The FET of claim 1 wherein: the passivation layer is in the range of 20 to 100 nm thick; and the gate dielectric is in the range of 2-20 nm thick.
The FET of claim 1 wherein the figure of merit Vb₂/Ron,sp is approximately 260 MW/cm2.
The FET of claim 1 wherein the channel layer further comprises a polarization induced 2DEG away from the gate electrode.
The FET of claim 1 wherein the FET is normally- off when the gate electrode is at zero bias.
The FET of claim 1 wherein the FET is a hybrid MOS-HFET.
The FET of claim 1 wherein a periphery of the gate is between 200 1i m to 20mm.
A method of fabricating a field effect transistor comprising: forming a channel layer; forming a barrier layer over the channel layer; forming a passivation layer over the barrier layer; Preliminary amendment 5 etching away a first area of the passivation layer for a source electrode and a second area of the passivation layer for a drain electrode; forming a source electrode and a drain electrode on the barrier layer; etching away a third area of the passivation layer and a fourth area extending through the barrier layer for a gate electrode; forming a gate dielectric on the surface of the third area and the fourth area; annealing the gate dielectric; and forming a gate electrode in the third area and in the fourth area; wherein the passivation layer is a first material and the gate dielectric is a second material; and wherein the first material is different than the second material.
The method of claim 13 wherein: the channel layer is GaN, InN, or InGaN; the barrier layer is AlGaN, AlN, AlInN, a combination of AlN spacer and AlGaN barrier, or a combination of AlN spacer and InAlN barrier; the passivation layer is SiN, Si O2, A₁ 203, Hf 0 2, Ti O2, amorphous A l N, or polycrystalline A lN; the gate dielectric is A 1 203, hafnium oxide (Hf 0 2), titanium oxide (Ti O 2), SiN, Si O 2, amorphous A l N, or polycrystalline A lN.
The method of claim 13 wherein: the gate dielectric is formed using atomic layer deposition a first proccoo; and the pa ss ivation lay e r i s form e d u s ing a se cond proc coo; Preliminary amendment 6 where in the fi rst proes a nd the and pro e are diff oro nt.
The method of claim 13 wherein: the gate dielectric is formed using atomic layer depos iti on; and the passivation layer is formed using plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOV C D), atomic layer deposition (ALD), molecular beam epitaxy (MBE), e-beam evaporation, or sputtering.
The method of claim 13 wherein the gate dielectric covers the passivation layer.
The method of claim 13 wheein further c omp r isi ng etching the barrier layer is annealed to the channel layer in the fourth area using atomic layer etching (ALE).
The method of claim 13 wherein: the passivation layer is in the range of 20 to 100 nm thick; and the gate dielectric is in the range of 2-20 nm thick.
The method of claim 13 wherein the figure of merit Vb₂/Ron is approximately 260 MW/cm2.
The method of claim 13 wherein the channel layer further comprises a polarization induced 2DEG away from the gate electrode.
Preliminary amendment 7 22. The method of claim 13 wherein the FET is normally-off when the gate electrode is at zero bias.
The method of claim 13 wherein the FET is a hybrid MOS-HFET.
The method of claim 13 wherein etching away a third area of the passivation layer and a fourth area extending through the barrier layer for a gate electrode comprises atomic layer etching.
Layer stacks claimed or described, ordered top of device to substrate.
hybrid MOS-HFET (field effect transistor)
Materials described outside the worked examples.
channel layer
barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 shows transfer curves comparing characteristics with and without a post deposition anneal (PDA) of the A 120 3 gate dielectric for a hybrid MOS-HFET in …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Vb2/Ron,sp figure of merit | 260 MW/cm2 | — |
passivation layer thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,653,559Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an elevation sectional view of a hybrid MOS-HFET with a layer used as both a gate dielectric and a passivation layer in accordance with the prior …
FIG. 2 shows an elevation sectional view of a hybrid MOS-HFET in accordance with the present disclosure; [0012]
FIG. 3 shows transfer curves comparing characteristics with and without a post deposition anneal (PDA) of the A 120 3 gate dielectric for a hybrid MOS-HFET in …
FIG. 4 shows a 200ns pulsed common-source current voltage measurement of an annealed A 120 3 hybrid MOS-HFET in accordance with the present disclosure; [0014]
FIG. 5 shows a common-source DC current voltage and zero-bias breakdown measurement of an annealed A 120 3 hybrid MOS-HFET in accordance with the present …
FIG. 6 shows a comparison of a prior art normally- off GaN power device with a hybrid MOS-HFET in accordance with the present disclosure; [0016]
FIG. 7 shows a common-source DC current voltage measurement of an annealed hybrid A 120 3 MOS-HFET with a gate periphery of 20mm with the gate biased from + 3V …
FIG. 8 is a flow diagram of a method of fabricating a hybrid MOS-HFET in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET) comprising: a source electrode; a drain electrode; a channel layer; a barrier layer over the channel layer and coupled to the source and drain electrodes; a gate electrode extending through the barrier layer; a passivation layer over the barrier layer for passivati ng the barrier layer between the gate electrode and the source electrode and between the gate electrode and the drain electrode, wherein the gate electrode extends through the passivation layer; a gate eletrode exte nding through the barrier lay er an d the pass iva tio n lay er; and a gate dielectric surrounding the portion of the gate electrode that extends through the barrier layer and the passivation layer; wherein the gate dielectric is annealed to improve an interface between the gate dielectric and the channel layer for reducing electron trap density and increasing channel mobility; wherein the passivation layer is a first material and the gate dielectric is a second material; and wherein the first material is different than the second material.
Preliminary amendment 3 2. The FET of claim 1 wherein: the channel layer is GaN, InN, or InGaN; the barrier layer is AlGaN, AlN, AlInN, a combination of AlN spacer and AlGaN barrier, or a combination of AlN spacer and InAlN barrier; the passivation layer is SiN, Si O2, A₁ 203, Hf 0 2, Ti O2, amorphous A l N, or polycrystalline A lN; the gate dielectric is A 1 203, hafnium oxide (Hf 0 2), titanium oxide (Ti O 2), SiN, Si O 2, amorphous A l N, or polycrystalline A lN.
The FET of claim 1 wherein: the gate dielectric is formed using atomic layer deposition a first pr c.o and the pasivation layer is formed using a second proceo.; where in the first pro cc. and the accond process are diff ere nt.
The FET of claim 1 wherein: the gate dielectric is formed using atomic layer depos iti on; and the passivation layer is formed using plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOV C D), atomic layer deposition (ALD), molecular beam epitaxy (MBE), e-beam evaporation, or sputtering.
The FET of claim 1 wherein the gate dielectric covers the passivation layer.
The FET of claim 1 wherein: Preliminary amendment 4 the barrier layer is annealed etched away to the channel layer in a region of the gate electrode using atomic layer etching (ALE).
The FET of claim 1 wherein: the passivation layer is in the range of 20 to 100 nm thick; and the gate dielectric is in the range of 2-20 nm thick.
The FET of claim 1 wherein the figure of merit Vb₂/Ron,sp is approximately 260 MW/cm2.
The FET of claim 1 wherein the channel layer further comprises a polarization induced 2DEG away from the gate electrode.
The FET of claim 1 wherein the FET is normally- off when the gate electrode is at zero bias.
The FET of claim 1 wherein the FET is a hybrid MOS-HFET.
The FET of claim 1 wherein a periphery of the gate is between 200 1i m to 20mm.
A method of fabricating a field effect transistor comprising: forming a channel layer; forming a barrier layer over the channel layer; forming a passivation layer over the barrier layer; Preliminary amendment 5 etching away a first area of the passivation layer for a source electrode and a second area of the passivation layer for a drain electrode; forming a source electrode and a drain electrode on the barrier layer; etching away a third area of the passivation layer and a fourth area extending through the barrier layer for a gate electrode; forming a gate dielectric on the surface of the third area and the fourth area; annealing the gate dielectric; and forming a gate electrode in the third area and in the fourth area; wherein the passivation layer is a first material and the gate dielectric is a second material; and wherein the first material is different than the second material.
The method of claim 13 wherein: the channel layer is GaN, InN, or InGaN; the barrier layer is AlGaN, AlN, AlInN, a combination of AlN spacer and AlGaN barrier, or a combination of AlN spacer and InAlN barrier; the passivation layer is SiN, Si O2, A₁ 203, Hf 0 2, Ti O2, amorphous A l N, or polycrystalline A lN; the gate dielectric is A 1 203, hafnium oxide (Hf 0 2), titanium oxide (Ti O 2), SiN, Si O 2, amorphous A l N, or polycrystalline A lN.
The method of claim 13 wherein: the gate dielectric is formed using atomic layer deposition a first proccoo; and the pa ss ivation lay e r i s form e d u s ing a se cond proc coo; Preliminary amendment 6 where in the fi rst proes a nd the and pro e are diff oro nt.
The method of claim 13 wherein: the gate dielectric is formed using atomic layer depos iti on; and the passivation layer is formed using plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOV C D), atomic layer deposition (ALD), molecular beam epitaxy (MBE), e-beam evaporation, or sputtering.
The method of claim 13 wherein the gate dielectric covers the passivation layer.
The method of claim 13 wheein further c omp r isi ng etching the barrier layer is annealed to the channel layer in the fourth area using atomic layer etching (ALE).
The method of claim 13 wherein: the passivation layer is in the range of 20 to 100 nm thick; and the gate dielectric is in the range of 2-20 nm thick.
The method of claim 13 wherein the figure of merit Vb₂/Ron is approximately 260 MW/cm2.
The method of claim 13 wherein the channel layer further comprises a polarization induced 2DEG away from the gate electrode.
Preliminary amendment 7 22. The method of claim 13 wherein the FET is normally-off when the gate electrode is at zero bias.
The method of claim 13 wherein the FET is a hybrid MOS-HFET.
The method of claim 13 wherein etching away a third area of the passivation layer and a fourth area extending through the barrier layer for a gate electrode comprises atomic layer etching.
Layer stacks claimed or described, ordered top of device to substrate.
hybrid MOS-HFET (field effect transistor)
Materials described outside the worked examples.
channel layer
barrier layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 shows transfer curves comparing characteristics with and without a post deposition anneal (PDA) of the A 120 3 gate dielectric for a hybrid MOS-HFET in …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Vb2/Ron,sp figure of merit | 260 MW/cm2 | — |
passivation layer thickness |
Related documents with shared materials, methods, properties, or citations.
passivation layer (first material)
gate dielectric (second material)
gate electrode
GaN
InN
InGaN
AlGaN
AlN
AlInN
AlN spacer and AlGaN barrier combination
AlN spacer and InAlN barrier combination
SiN
SiO₂
Al₂O₃
HfO₂
TiO₂
FIG. 7 shows a common-source DC current voltage measurement of an annealed hybrid A 120 3 MOS-HFET with a gate periphery of 20mm with the gate biased from + 3V …
| — |
passivation layer (first material) |
gate dielectric thickness | — | gate dielectric (second material) |
dielectric constant of Al2O3 | — | Al₂O₃ |
dielectric constant of SiO2 | — | SiO₂ |
bandgap of Al2O3 | 7 eV | Al₂O₃ |
bandgap of SiO2 | 5 eV | SiO₂ |
Thickness | 20–100 nm | — |
Thickness | 30–50 nm | — |
Thickness | 2–20 nm | — |
Thickness | ≤ 20 nm | — |
Thickness | ≥ 20 nm | — |
passivation layer (first material)
gate dielectric (second material)
gate electrode
GaN
InN
InGaN
AlGaN
AlN
AlInN
AlN spacer and AlGaN barrier combination
AlN spacer and InAlN barrier combination
SiN
SiO₂
Al₂O₃
HfO₂
TiO₂
FIG. 7 shows a common-source DC current voltage measurement of an annealed hybrid A 120 3 MOS-HFET with a gate periphery of 20mm with the gate biased from + 3V …
| — |
passivation layer (first material) |
gate dielectric thickness | — | gate dielectric (second material) |
dielectric constant of Al2O3 | — | Al₂O₃ |
dielectric constant of SiO2 | — | SiO₂ |
bandgap of Al2O3 | 7 eV | Al₂O₃ |
bandgap of SiO2 | 5 eV | SiO₂ |
Thickness | 20–100 nm | — |
Thickness | 30–50 nm | — |
Thickness | 2–20 nm | — |
Thickness | ≤ 20 nm | — |
Thickness | ≥ 20 nm | — |
passivation layer (first material)
gate dielectric (second material)
gate electrode
GaN
InN
InGaN
AlGaN
AlN
AlInN
AlN spacer and AlGaN barrier combination
AlN spacer and InAlN barrier combination
SiN
SiO₂
Al₂O₃
HfO₂
TiO₂
FIG. 7 shows a common-source DC current voltage measurement of an annealed hybrid A 120 3 MOS-HFET with a gate periphery of 20mm with the gate biased from + 3V …
| — |
passivation layer (first material) |
gate dielectric thickness | — | gate dielectric (second material) |
dielectric constant of Al2O3 | — | Al₂O₃ |
dielectric constant of SiO2 | — | SiO₂ |
bandgap of Al2O3 | 7 eV | Al₂O₃ |
bandgap of SiO2 | 5 eV | SiO₂ |
Thickness | 20–100 nm | — |
Thickness | 30–50 nm | — |
Thickness | 2–20 nm | — |
Thickness | ≤ 20 nm | — |
Thickness | ≥ 20 nm | — |
passivation layer (first material)
gate dielectric (second material)
gate electrode
GaN
InN
InGaN
AlGaN
AlN
AlInN
AlN spacer and AlGaN barrier combination
AlN spacer and InAlN barrier combination
SiN
SiO₂
Al₂O₃
HfO₂
TiO₂
FIG. 7 shows a common-source DC current voltage measurement of an annealed hybrid A 120 3 MOS-HFET with a gate periphery of 20mm with the gate biased from + 3V …
| — |
passivation layer (first material) |
gate dielectric thickness | — | gate dielectric (second material) |
dielectric constant of Al2O3 | — | Al₂O₃ |
dielectric constant of SiO2 | — | SiO₂ |
bandgap of Al2O3 | 7 eV | Al₂O₃ |
bandgap of SiO2 | 5 eV | SiO₂ |
Thickness | 20–100 nm | — |
Thickness | 30–50 nm | — |
Thickness | 2–20 nm | — |
Thickness | ≤ 20 nm | — |
Thickness | ≥ 20 nm | — |