Patent
US 9,214,539GaN MISFETS WITH HYBRID Al₂O₃ AS GATE DIELECTRIC
Han-Chin Chiu
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,214,539Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The semiconductor device of claim 1, wherein the first hydrogen to hydroxide ratio is higher than the second hydrogen to hydroxide ratio.
The semiconductor device of claim 2, wherein the first dielectric layer has a thickness in a range of about 1 nm to about 2 0 nm and the second dielectric layer has a thickness in a range of about 1 0 nm to about 5 0 nm.
The semiconductor device of claim 1, further comprising: a hybrid passivation layer which is disposed directly above the crystalline or poly crystalline I ll -N layer, in regions between the source, drain and gate.
The semiconductor device of claim 4, wherein the hybrid passivation layer comprises a first passivation layer and a second passivation layer, wherein the first passivation layer has higher H/OH content than the second passivation layer, and wherein the second passivation layer, which comprises one or more than one kinds of oxide stacks oxides stacked on top of the first passivation and has lower H/OH content, resides on top of the first passivation layer.
The semiconductor device of claim 1, wherein the hybrid gate dielectric layer comprises Ga₂ O 3, SiO2, A 120 3, MgO, Ga₂ O 3, La₂ O3, HfO 2, ZrO2, Y₂ 0 3, Gd₂ O 3, Ce₂₀ 3, Ta₂ O 3 or Ta₂
A I II -nitride (I II -N) high electron mobility transistor (HEMT) device comprising: an aluminum nitride (AIN) buffer layer disposed on a substrate; a first aluminum gallium nitride (AIGaN) layer disposed on the AIN buffer layer; a gallium nitride (GaN) layer disposed on the first AIGaN layer; P₂₀₁₃₀₅₀₃ US00 App. No. 14/016,328 Page 5 a second aluminum gallium nitride (AIGaN) layer disposed on the GaN layer; a source region located at a first location in or on the second AIGaN layer; a drain region located at a second location in or on the second AIGaN layer, wherein the second location is laterally disposed and separated from the source region; a gate region located at a third location on the second AIGaN layer or the GaN layer, wherein the third location is laterally disposed between the source region and the drain region; and a hybrid gate dielectric layer disposed directly above the GaN or second AIGaN layer in the gate region and having first and second portions, wherein the first and second portions have first and second hydrogen to hydroxide ratios, respectively, the first and second hydrogen to hydroxide ratios differing from one another.
The HEMT device of claim 8, further comprising: a hybrid passivation layer disposed directly above the second AIGaN layer between the source, drain and gate regions; a cap layer disposed above the hybrid passivation layer, the source region and the drain region; and a gate electrode disposed directly above the hybrid gate dielectric layer in the gate region.
The HEMT device of claim 8, wherein the hybrid gate dielectric layer has a larger band gap than the second AIGaN layer or the GaN layer underneath.
The HEMT device of claim 8, wherein the hybrid gate dielectric layer comprises: a first dielectric layer comprising a H₂₀-based atomic layer deposited (ALD) oxide; and a second dielectric layer comprising an 03/02 plasma-based ALD oxide, wherein the second dielectric layer resides on top of the first dielectric layer.
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A I II -N (tri nitride) semiconductor device, comprising: a heterojunction structure disposed over a semiconductor substrate and including a first I ll -N layer abutting a second I II -N layer, wherein the second I II -N layer is disposed over the first I II -N layer and differs from the first I II -N layer in its chemical composition; a source region and a drain region which are disposed over an upper region of the second I ll -N layer and which are spaced apart from one another; a gate electrode disposed over the heterojunction structure in a gate region, wherein the gate region is laterally disposed between the source and drain regions; a hybrid passivation layer disposed directly over the upper region of the second Ill -N layer on either side of the source, drain regions except in the gate region, wherein the hybrid passivation layer comprises first and second passivation layers having first and second hydrogen to hydroxide ratios, respectively, wherein the first and second hydrogen to hydroxide ratios differ from one another; and a hybrid gate dielectric layer disposed directly over the upper region of the second III -N layer, in the gate region.
The Ill -N semiconductor device of claim 21, wherein the hybrid gate dielectric layer comprises a first dielectric layer and a second P₂₀₁₃₀₅₀₃ US00 App. No. 14/016,328 Page 7 dielectric layer, wherein the first dielectric layer has a higher hydrogen to hydroxide ratio than the second dielectric layer, and wherein the second dielectric layer resides on top of the first dielectric layer.
The Ill -N semiconductor device of claim 21, wherein the first hydrogen to hydroxide ratio is higher than the second hydrogen to hydroxide ratio, and wherein the second passivation layer resides on top of the first passivation layer.
The l1l -N semiconductor device of claim 21, further comprising a cap layer disposed above the hybrid passivation layer, the source region and the drain region.
The Ill -N semiconductor device of claim 21, wherein the hybrid gate dielectric layer has a larger band gap than the first or second Ill-N layer.
Layer stacks claimed or described, ordered top of device to substrate.
III-N semiconductor device with hybrid gate dielectric (claim 1 family)
III-N HEMT device with AlN buffer, AlGaN/GaN/AlGaN stack and hybrid gate dielectric (claim 8 family)
Materials described outside the worked examples.
aluminum nitride buffer layer
AlN
aluminum gallium nitride (first layer)
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,214,539Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The semiconductor device of claim 1, wherein the first hydrogen to hydroxide ratio is higher than the second hydrogen to hydroxide ratio.
The semiconductor device of claim 2, wherein the first dielectric layer has a thickness in a range of about 1 nm to about 2 0 nm and the second dielectric layer has a thickness in a range of about 1 0 nm to about 5 0 nm.
The semiconductor device of claim 1, further comprising: a hybrid passivation layer which is disposed directly above the crystalline or poly crystalline I ll -N layer, in regions between the source, drain and gate.
The semiconductor device of claim 4, wherein the hybrid passivation layer comprises a first passivation layer and a second passivation layer, wherein the first passivation layer has higher H/OH content than the second passivation layer, and wherein the second passivation layer, which comprises one or more than one kinds of oxide stacks oxides stacked on top of the first passivation and has lower H/OH content, resides on top of the first passivation layer.
The semiconductor device of claim 1, wherein the hybrid gate dielectric layer comprises Ga₂ O 3, SiO2, A 120 3, MgO, Ga₂ O 3, La₂ O3, HfO 2, ZrO2, Y₂ 0 3, Gd₂ O 3, Ce₂₀ 3, Ta₂ O 3 or Ta₂
A I II -nitride (I II -N) high electron mobility transistor (HEMT) device comprising: an aluminum nitride (AIN) buffer layer disposed on a substrate; a first aluminum gallium nitride (AIGaN) layer disposed on the AIN buffer layer; a gallium nitride (GaN) layer disposed on the first AIGaN layer; P₂₀₁₃₀₅₀₃ US00 App. No. 14/016,328 Page 5 a second aluminum gallium nitride (AIGaN) layer disposed on the GaN layer; a source region located at a first location in or on the second AIGaN layer; a drain region located at a second location in or on the second AIGaN layer, wherein the second location is laterally disposed and separated from the source region; a gate region located at a third location on the second AIGaN layer or the GaN layer, wherein the third location is laterally disposed between the source region and the drain region; and a hybrid gate dielectric layer disposed directly above the GaN or second AIGaN layer in the gate region and having first and second portions, wherein the first and second portions have first and second hydrogen to hydroxide ratios, respectively, the first and second hydrogen to hydroxide ratios differing from one another.
The HEMT device of claim 8, further comprising: a hybrid passivation layer disposed directly above the second AIGaN layer between the source, drain and gate regions; a cap layer disposed above the hybrid passivation layer, the source region and the drain region; and a gate electrode disposed directly above the hybrid gate dielectric layer in the gate region.
The HEMT device of claim 8, wherein the hybrid gate dielectric layer has a larger band gap than the second AIGaN layer or the GaN layer underneath.
The HEMT device of claim 8, wherein the hybrid gate dielectric layer comprises: a first dielectric layer comprising a H₂₀-based atomic layer deposited (ALD) oxide; and a second dielectric layer comprising an 03/02 plasma-based ALD oxide, wherein the second dielectric layer resides on top of the first dielectric layer.
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A I II -N (tri nitride) semiconductor device, comprising: a heterojunction structure disposed over a semiconductor substrate and including a first I ll -N layer abutting a second I II -N layer, wherein the second I II -N layer is disposed over the first I II -N layer and differs from the first I II -N layer in its chemical composition; a source region and a drain region which are disposed over an upper region of the second I ll -N layer and which are spaced apart from one another; a gate electrode disposed over the heterojunction structure in a gate region, wherein the gate region is laterally disposed between the source and drain regions; a hybrid passivation layer disposed directly over the upper region of the second Ill -N layer on either side of the source, drain regions except in the gate region, wherein the hybrid passivation layer comprises first and second passivation layers having first and second hydrogen to hydroxide ratios, respectively, wherein the first and second hydrogen to hydroxide ratios differ from one another; and a hybrid gate dielectric layer disposed directly over the upper region of the second III -N layer, in the gate region.
The Ill -N semiconductor device of claim 21, wherein the hybrid gate dielectric layer comprises a first dielectric layer and a second P₂₀₁₃₀₅₀₃ US00 App. No. 14/016,328 Page 7 dielectric layer, wherein the first dielectric layer has a higher hydrogen to hydroxide ratio than the second dielectric layer, and wherein the second dielectric layer resides on top of the first dielectric layer.
The Ill -N semiconductor device of claim 21, wherein the first hydrogen to hydroxide ratio is higher than the second hydrogen to hydroxide ratio, and wherein the second passivation layer resides on top of the first passivation layer.
The l1l -N semiconductor device of claim 21, further comprising a cap layer disposed above the hybrid passivation layer, the source region and the drain region.
The Ill -N semiconductor device of claim 21, wherein the hybrid gate dielectric layer has a larger band gap than the first or second Ill-N layer.
Layer stacks claimed or described, ordered top of device to substrate.
III-N semiconductor device with hybrid gate dielectric (claim 1 family)
III-N HEMT device with AlN buffer, AlGaN/GaN/AlGaN stack and hybrid gate dielectric (claim 8 family)
Materials described outside the worked examples.
aluminum nitride buffer layer
AlN
aluminum gallium nitride (first layer)
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,214,539Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The semiconductor device of claim 1, wherein the first hydrogen to hydroxide ratio is higher than the second hydrogen to hydroxide ratio.
The semiconductor device of claim 2, wherein the first dielectric layer has a thickness in a range of about 1 nm to about 2 0 nm and the second dielectric layer has a thickness in a range of about 1 0 nm to about 5 0 nm.
The semiconductor device of claim 1, further comprising: a hybrid passivation layer which is disposed directly above the crystalline or poly crystalline I ll -N layer, in regions between the source, drain and gate.
The semiconductor device of claim 4, wherein the hybrid passivation layer comprises a first passivation layer and a second passivation layer, wherein the first passivation layer has higher H/OH content than the second passivation layer, and wherein the second passivation layer, which comprises one or more than one kinds of oxide stacks oxides stacked on top of the first passivation and has lower H/OH content, resides on top of the first passivation layer.
The semiconductor device of claim 1, wherein the hybrid gate dielectric layer comprises Ga₂ O 3, SiO2, A 120 3, MgO, Ga₂ O 3, La₂ O3, HfO 2, ZrO2, Y₂ 0 3, Gd₂ O 3, Ce₂₀ 3, Ta₂ O 3 or Ta₂
A I II -nitride (I II -N) high electron mobility transistor (HEMT) device comprising: an aluminum nitride (AIN) buffer layer disposed on a substrate; a first aluminum gallium nitride (AIGaN) layer disposed on the AIN buffer layer; a gallium nitride (GaN) layer disposed on the first AIGaN layer; P₂₀₁₃₀₅₀₃ US00 App. No. 14/016,328 Page 5 a second aluminum gallium nitride (AIGaN) layer disposed on the GaN layer; a source region located at a first location in or on the second AIGaN layer; a drain region located at a second location in or on the second AIGaN layer, wherein the second location is laterally disposed and separated from the source region; a gate region located at a third location on the second AIGaN layer or the GaN layer, wherein the third location is laterally disposed between the source region and the drain region; and a hybrid gate dielectric layer disposed directly above the GaN or second AIGaN layer in the gate region and having first and second portions, wherein the first and second portions have first and second hydrogen to hydroxide ratios, respectively, the first and second hydrogen to hydroxide ratios differing from one another.
The HEMT device of claim 8, further comprising: a hybrid passivation layer disposed directly above the second AIGaN layer between the source, drain and gate regions; a cap layer disposed above the hybrid passivation layer, the source region and the drain region; and a gate electrode disposed directly above the hybrid gate dielectric layer in the gate region.
The HEMT device of claim 8, wherein the hybrid gate dielectric layer has a larger band gap than the second AIGaN layer or the GaN layer underneath.
The HEMT device of claim 8, wherein the hybrid gate dielectric layer comprises: a first dielectric layer comprising a H₂₀-based atomic layer deposited (ALD) oxide; and a second dielectric layer comprising an 03/02 plasma-based ALD oxide, wherein the second dielectric layer resides on top of the first dielectric layer.
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A I II -N (tri nitride) semiconductor device, comprising: a heterojunction structure disposed over a semiconductor substrate and including a first I ll -N layer abutting a second I II -N layer, wherein the second I II -N layer is disposed over the first I II -N layer and differs from the first I II -N layer in its chemical composition; a source region and a drain region which are disposed over an upper region of the second I ll -N layer and which are spaced apart from one another; a gate electrode disposed over the heterojunction structure in a gate region, wherein the gate region is laterally disposed between the source and drain regions; a hybrid passivation layer disposed directly over the upper region of the second Ill -N layer on either side of the source, drain regions except in the gate region, wherein the hybrid passivation layer comprises first and second passivation layers having first and second hydrogen to hydroxide ratios, respectively, wherein the first and second hydrogen to hydroxide ratios differ from one another; and a hybrid gate dielectric layer disposed directly over the upper region of the second III -N layer, in the gate region.
The Ill -N semiconductor device of claim 21, wherein the hybrid gate dielectric layer comprises a first dielectric layer and a second P₂₀₁₃₀₅₀₃ US00 App. No. 14/016,328 Page 7 dielectric layer, wherein the first dielectric layer has a higher hydrogen to hydroxide ratio than the second dielectric layer, and wherein the second dielectric layer resides on top of the first dielectric layer.
The Ill -N semiconductor device of claim 21, wherein the first hydrogen to hydroxide ratio is higher than the second hydrogen to hydroxide ratio, and wherein the second passivation layer resides on top of the first passivation layer.
The l1l -N semiconductor device of claim 21, further comprising a cap layer disposed above the hybrid passivation layer, the source region and the drain region.
The Ill -N semiconductor device of claim 21, wherein the hybrid gate dielectric layer has a larger band gap than the first or second Ill-N layer.
Layer stacks claimed or described, ordered top of device to substrate.
III-N semiconductor device with hybrid gate dielectric (claim 1 family)
III-N HEMT device with AlN buffer, AlGaN/GaN/AlGaN stack and hybrid gate dielectric (claim 8 family)
Materials described outside the worked examples.
aluminum nitride buffer layer
AlN
aluminum gallium nitride (first layer)
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,214,539Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The semiconductor device of claim 1, wherein the first hydrogen to hydroxide ratio is higher than the second hydrogen to hydroxide ratio.
The semiconductor device of claim 2, wherein the first dielectric layer has a thickness in a range of about 1 nm to about 2 0 nm and the second dielectric layer has a thickness in a range of about 1 0 nm to about 5 0 nm.
The semiconductor device of claim 1, further comprising: a hybrid passivation layer which is disposed directly above the crystalline or poly crystalline I ll -N layer, in regions between the source, drain and gate.
The semiconductor device of claim 4, wherein the hybrid passivation layer comprises a first passivation layer and a second passivation layer, wherein the first passivation layer has higher H/OH content than the second passivation layer, and wherein the second passivation layer, which comprises one or more than one kinds of oxide stacks oxides stacked on top of the first passivation and has lower H/OH content, resides on top of the first passivation layer.
The semiconductor device of claim 1, wherein the hybrid gate dielectric layer comprises Ga₂ O 3, SiO2, A 120 3, MgO, Ga₂ O 3, La₂ O3, HfO 2, ZrO2, Y₂ 0 3, Gd₂ O 3, Ce₂₀ 3, Ta₂ O 3 or Ta₂
A I II -nitride (I II -N) high electron mobility transistor (HEMT) device comprising: an aluminum nitride (AIN) buffer layer disposed on a substrate; a first aluminum gallium nitride (AIGaN) layer disposed on the AIN buffer layer; a gallium nitride (GaN) layer disposed on the first AIGaN layer; P₂₀₁₃₀₅₀₃ US00 App. No. 14/016,328 Page 5 a second aluminum gallium nitride (AIGaN) layer disposed on the GaN layer; a source region located at a first location in or on the second AIGaN layer; a drain region located at a second location in or on the second AIGaN layer, wherein the second location is laterally disposed and separated from the source region; a gate region located at a third location on the second AIGaN layer or the GaN layer, wherein the third location is laterally disposed between the source region and the drain region; and a hybrid gate dielectric layer disposed directly above the GaN or second AIGaN layer in the gate region and having first and second portions, wherein the first and second portions have first and second hydrogen to hydroxide ratios, respectively, the first and second hydrogen to hydroxide ratios differing from one another.
The HEMT device of claim 8, further comprising: a hybrid passivation layer disposed directly above the second AIGaN layer between the source, drain and gate regions; a cap layer disposed above the hybrid passivation layer, the source region and the drain region; and a gate electrode disposed directly above the hybrid gate dielectric layer in the gate region.
The HEMT device of claim 8, wherein the hybrid gate dielectric layer has a larger band gap than the second AIGaN layer or the GaN layer underneath.
The HEMT device of claim 8, wherein the hybrid gate dielectric layer comprises: a first dielectric layer comprising a H₂₀-based atomic layer deposited (ALD) oxide; and a second dielectric layer comprising an 03/02 plasma-based ALD oxide, wherein the second dielectric layer resides on top of the first dielectric layer.
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A I II -N (tri nitride) semiconductor device, comprising: a heterojunction structure disposed over a semiconductor substrate and including a first I ll -N layer abutting a second I II -N layer, wherein the second I II -N layer is disposed over the first I II -N layer and differs from the first I II -N layer in its chemical composition; a source region and a drain region which are disposed over an upper region of the second I ll -N layer and which are spaced apart from one another; a gate electrode disposed over the heterojunction structure in a gate region, wherein the gate region is laterally disposed between the source and drain regions; a hybrid passivation layer disposed directly over the upper region of the second Ill -N layer on either side of the source, drain regions except in the gate region, wherein the hybrid passivation layer comprises first and second passivation layers having first and second hydrogen to hydroxide ratios, respectively, wherein the first and second hydrogen to hydroxide ratios differ from one another; and a hybrid gate dielectric layer disposed directly over the upper region of the second III -N layer, in the gate region.
The Ill -N semiconductor device of claim 21, wherein the hybrid gate dielectric layer comprises a first dielectric layer and a second P₂₀₁₃₀₅₀₃ US00 App. No. 14/016,328 Page 7 dielectric layer, wherein the first dielectric layer has a higher hydrogen to hydroxide ratio than the second dielectric layer, and wherein the second dielectric layer resides on top of the first dielectric layer.
The Ill -N semiconductor device of claim 21, wherein the first hydrogen to hydroxide ratio is higher than the second hydrogen to hydroxide ratio, and wherein the second passivation layer resides on top of the first passivation layer.
The l1l -N semiconductor device of claim 21, further comprising a cap layer disposed above the hybrid passivation layer, the source region and the drain region.
The Ill -N semiconductor device of claim 21, wherein the hybrid gate dielectric layer has a larger band gap than the first or second Ill-N layer.
Layer stacks claimed or described, ordered top of device to substrate.
III-N semiconductor device with hybrid gate dielectric (claim 1 family)
III-N HEMT device with AlN buffer, AlGaN/GaN/AlGaN stack and hybrid gate dielectric (claim 8 family)
Materials described outside the worked examples.
aluminum nitride buffer layer
AlN
aluminum gallium nitride (first layer)
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1–20 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
III-N semiconductor device with heterojunction, hybrid passivation and hybrid gate dielectric (claim 21 family)
III-N HEMT device 100 with hybrid gate dielectric and hybrid passivation layer (described embodiment)
gallium nitride channel layer
GaN
first passivation layer (H₂O-based ALD oxide)
second passivation layer (O₃/O₂-based ALD oxide)
hybrid gate dielectric oxide options
H₂O-based ALD oxide (first dielectric layer)
O₃/O₂ plasma-based ALD oxide (second dielectric layer)
Al₂O₃ (H₂O-based ALD, first dielectric layer)
Al₂O₃
cap layer
| — |
Thickness | 5–100 nm | — |
Thickness | 0–50 nm | — |
Thickness | 150–300 nm | — |
Thickness | 150–1200 nm | — |
III-N semiconductor device with heterojunction, hybrid passivation and hybrid gate dielectric (claim 21 family)
III-N HEMT device 100 with hybrid gate dielectric and hybrid passivation layer (described embodiment)
gallium nitride channel layer
GaN
first passivation layer (H₂O-based ALD oxide)
second passivation layer (O₃/O₂-based ALD oxide)
hybrid gate dielectric oxide options
H₂O-based ALD oxide (first dielectric layer)
O₃/O₂ plasma-based ALD oxide (second dielectric layer)
Al₂O₃ (H₂O-based ALD, first dielectric layer)
Al₂O₃
cap layer
| — |
Thickness | 5–100 nm | — |
Thickness | 0–50 nm | — |
Thickness | 150–300 nm | — |
Thickness | 150–1200 nm | — |
III-N semiconductor device with heterojunction, hybrid passivation and hybrid gate dielectric (claim 21 family)
III-N HEMT device 100 with hybrid gate dielectric and hybrid passivation layer (described embodiment)
gallium nitride channel layer
GaN
first passivation layer (H₂O-based ALD oxide)
second passivation layer (O₃/O₂-based ALD oxide)
hybrid gate dielectric oxide options
H₂O-based ALD oxide (first dielectric layer)
O₃/O₂ plasma-based ALD oxide (second dielectric layer)
Al₂O₃ (H₂O-based ALD, first dielectric layer)
Al₂O₃
cap layer
| — |
Thickness | 5–100 nm | — |
Thickness | 0–50 nm | — |
Thickness | 150–300 nm | — |
Thickness | 150–1200 nm | — |
III-N semiconductor device with heterojunction, hybrid passivation and hybrid gate dielectric (claim 21 family)
III-N HEMT device 100 with hybrid gate dielectric and hybrid passivation layer (described embodiment)
gallium nitride channel layer
GaN
first passivation layer (H₂O-based ALD oxide)
second passivation layer (O₃/O₂-based ALD oxide)
hybrid gate dielectric oxide options
H₂O-based ALD oxide (first dielectric layer)
O₃/O₂ plasma-based ALD oxide (second dielectric layer)
Al₂O₃ (H₂O-based ALD, first dielectric layer)
Al₂O₃
cap layer
| — |
Thickness | 5–100 nm | — |
Thickness | 0–50 nm | — |
Thickness | 150–300 nm | — |
Thickness | 150–1200 nm | — |