Patent
US 11,335,798ENHANCEMENT MODE MISHEMT WITH GAN CHANNEL REGROWTH UNDER A GATE AREA
Peter MOENS
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,335,798Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section of an E-mode MISHEMT with GaN channel regrowth under a gate area, according to some example implementations. [0008]
FIG. 2 illustrates a more detailed example device structure of the E-mode MISHEMT with GaN channel regrowth under a gate area of
FIG. 3 illustrates bandgaps and bandgap offsets of example dielectric materials that may be used in the example devices of
FIG. 4 illustrates a first example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate area …
FIG. 5 illustrates a second example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 6 illustrates a third example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 7 illustrates a fourth example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 8 illustrates a fifth example device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate area of
FIG. 9 is a flowchart illustrating an example process for forming an implementation of the E-mode MISHEMT with GaN channel regrowth of under a gate area
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a High Electron Mobility Transistor (H EMT) having: a substrate; a channel layer adjacent to the substrate; a barrier layer adjacent to the channel layer and extending at least partially between a source and a drain of the HEMT, the barrier layer providing a heterojunction with the channel layer, the heterojunction causing a two-dimensional electron gas (2DEG) to occur within the channel layer between the source and the drain; a channel-material layer extending through a recess in the barrier layer and into the channel layer, the channel-material layer inc l udin g a channel-material portion that is within the channel layer and between the barrier layer and the s ubstrate; at least one passivation layer adjacent to the channel-material layer within the recess; at least one dielectric layer adjacent to the at least one passivation layer within the recess; and a gate adjacent to the at least one dielectric layer. wherein the channel-material portion disrupts the 2DEG when the gate is not biased and defines a disruption region between the channel-material portion and the substrate. and current flows between the source and the drain through the disruption region when a bias is applied to the gate. Currently amended
The semiconductor device of claim 1, wherein the channel-material layer formed within the recess in the barrier layer extends along a surface of the barr ier layer in a direction of a source contact of the HEMT and in a direction of a drain contact of the HEMT. Previously presented
The semiconductor device of claim 1, wherein the channel-material layer is p-doped. Original
The semiconductor device of claim 1, wherein less than 10 nm. New
The semiconductor device of claim 1, wherein layer include the same channel material. New
. Canceled
. Canceled
(Cu rr ently Amended) A High Electron Mobility Transistor (HEMT) device, comprising: a substrate; a channel layer adjacent to the substrate; a barrier layer adjacent to the channel layer and forming a heterojunction therewith, the heterojunction causing a two-dimensional electron gas (2DEG) to occur within the channel layer; a channel-material layer formed at least partially within a recess in the ba rr ier layer and including a portion that extends into the channel layer; at least one passivation layer adjacent to the channel-material layer within the recess; at least one dielectric layer adjacent to the at least one passivation layer within the recess; a gate adjacent to the at least one dielectric layer; and a source and a drain formed at opposing ends of the 2DEG to define a current channel between the source and the drain that extends through the channel layer, the cu rr ent channel including a region of the channel layer adjacent to the portion of the channel-material layer, wherein the channel-material layer, the at least one passivation layer, and the at least one dielectric layer extend in a direction of the source and in a direction of the drain s wherein the portion of the channel-material layer disrupts the 2DEG when the gate is not biased and defines a disruption region between the portion of the channel-material layer and the substrate, and current flows between the source and the drain through the disruption region when a bias is applied to the gate. Currently amended
The HEMT of claim 10, wherein the channel-material layer extends along sidewalls of the recess. Previously presented
The HEMT of claim 10, wherein the at least one dielectric layer includes an oxide having a bandgap offset relative to both a conduction band and a valence band of the channel layer and the channel-material layer. Previously presented
(Cu rr ently Amended) The HEMT of claim 10, wherein the substrate includes a Sapphire substrate. Currently amended
The HEMT of claim 10, wherein the channel-material layer is p-doped. Original
. Canceled
A method of making a High Electron Mobility Transistor (HEMT), comprising: forming a layer stack that includes at least a channel layer and a ba rr ier layer adjacent to the channel layer and forming a heterojunction at which a current channel is defined in the channel layer; forming a recess in the ba rr ier layer that extends into the channel layer; SVG 16734649.12-03-2021.KWQUHEWHLDFLYX9.CLM.1.svg 0.16 3.38 Black and white forming at least one dielectric layer adjacent to the channel-material layer; forming a gate adjacent to the at least one dielectric layer; and forming a source and drain at opposing ends of the current channel. Withdrawn
The method of claim 17, wherein forming the recess comprises a first etching process to etch through the barrier layer to an etch stop layer in the layer stack between the channel layer and the barrier layer, and further wherein forming the channel- material layer includes a second etch process to etch into the channel layer. Withdrawn
The method of claim 17, wherein forming the at least one dielectric layer comprises: forming the at least one dielectric layer in-situ with the channel-material layer. Withdrawn
The method of claim 17, wherein forming the at least one dielectric layer comprises: SVG 16734649.12-03-2021.KWQUHEWHLDFLYX9.CLM.2.svg insulating layer with a bandgap offset relative to the channel layer and the channel-material layer.
Layer stacks claimed or described, ordered top of device to substrate.
Enhancement Mode MIS-HEMT (EMISHEMT) with GaN channel regrowth
Materials described outside the worked examples.
GaN (channel layer)
GaN
Silicon Nitride
Si₃N₄
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 illustrates bandgaps and bandgap offsets of example dielectric materials that may be used in the example devices of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.002–0.05 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,335,798Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section of an E-mode MISHEMT with GaN channel regrowth under a gate area, according to some example implementations. [0008]
FIG. 2 illustrates a more detailed example device structure of the E-mode MISHEMT with GaN channel regrowth under a gate area of
FIG. 3 illustrates bandgaps and bandgap offsets of example dielectric materials that may be used in the example devices of
FIG. 4 illustrates a first example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate area …
FIG. 5 illustrates a second example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 6 illustrates a third example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 7 illustrates a fourth example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 8 illustrates a fifth example device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate area of
FIG. 9 is a flowchart illustrating an example process for forming an implementation of the E-mode MISHEMT with GaN channel regrowth of under a gate area
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a High Electron Mobility Transistor (H EMT) having: a substrate; a channel layer adjacent to the substrate; a barrier layer adjacent to the channel layer and extending at least partially between a source and a drain of the HEMT, the barrier layer providing a heterojunction with the channel layer, the heterojunction causing a two-dimensional electron gas (2DEG) to occur within the channel layer between the source and the drain; a channel-material layer extending through a recess in the barrier layer and into the channel layer, the channel-material layer inc l udin g a channel-material portion that is within the channel layer and between the barrier layer and the s ubstrate; at least one passivation layer adjacent to the channel-material layer within the recess; at least one dielectric layer adjacent to the at least one passivation layer within the recess; and a gate adjacent to the at least one dielectric layer. wherein the channel-material portion disrupts the 2DEG when the gate is not biased and defines a disruption region between the channel-material portion and the substrate. and current flows between the source and the drain through the disruption region when a bias is applied to the gate. Currently amended
The semiconductor device of claim 1, wherein the channel-material layer formed within the recess in the barrier layer extends along a surface of the barr ier layer in a direction of a source contact of the HEMT and in a direction of a drain contact of the HEMT. Previously presented
The semiconductor device of claim 1, wherein the channel-material layer is p-doped. Original
The semiconductor device of claim 1, wherein less than 10 nm. New
The semiconductor device of claim 1, wherein layer include the same channel material. New
. Canceled
. Canceled
(Cu rr ently Amended) A High Electron Mobility Transistor (HEMT) device, comprising: a substrate; a channel layer adjacent to the substrate; a barrier layer adjacent to the channel layer and forming a heterojunction therewith, the heterojunction causing a two-dimensional electron gas (2DEG) to occur within the channel layer; a channel-material layer formed at least partially within a recess in the ba rr ier layer and including a portion that extends into the channel layer; at least one passivation layer adjacent to the channel-material layer within the recess; at least one dielectric layer adjacent to the at least one passivation layer within the recess; a gate adjacent to the at least one dielectric layer; and a source and a drain formed at opposing ends of the 2DEG to define a current channel between the source and the drain that extends through the channel layer, the cu rr ent channel including a region of the channel layer adjacent to the portion of the channel-material layer, wherein the channel-material layer, the at least one passivation layer, and the at least one dielectric layer extend in a direction of the source and in a direction of the drain s wherein the portion of the channel-material layer disrupts the 2DEG when the gate is not biased and defines a disruption region between the portion of the channel-material layer and the substrate, and current flows between the source and the drain through the disruption region when a bias is applied to the gate. Currently amended
The HEMT of claim 10, wherein the channel-material layer extends along sidewalls of the recess. Previously presented
The HEMT of claim 10, wherein the at least one dielectric layer includes an oxide having a bandgap offset relative to both a conduction band and a valence band of the channel layer and the channel-material layer. Previously presented
(Cu rr ently Amended) The HEMT of claim 10, wherein the substrate includes a Sapphire substrate. Currently amended
The HEMT of claim 10, wherein the channel-material layer is p-doped. Original
. Canceled
A method of making a High Electron Mobility Transistor (HEMT), comprising: forming a layer stack that includes at least a channel layer and a ba rr ier layer adjacent to the channel layer and forming a heterojunction at which a current channel is defined in the channel layer; forming a recess in the ba rr ier layer that extends into the channel layer; SVG 16734649.12-03-2021.KWQUHEWHLDFLYX9.CLM.1.svg 0.16 3.38 Black and white forming at least one dielectric layer adjacent to the channel-material layer; forming a gate adjacent to the at least one dielectric layer; and forming a source and drain at opposing ends of the current channel. Withdrawn
The method of claim 17, wherein forming the recess comprises a first etching process to etch through the barrier layer to an etch stop layer in the layer stack between the channel layer and the barrier layer, and further wherein forming the channel- material layer includes a second etch process to etch into the channel layer. Withdrawn
The method of claim 17, wherein forming the at least one dielectric layer comprises: forming the at least one dielectric layer in-situ with the channel-material layer. Withdrawn
The method of claim 17, wherein forming the at least one dielectric layer comprises: SVG 16734649.12-03-2021.KWQUHEWHLDFLYX9.CLM.2.svg insulating layer with a bandgap offset relative to the channel layer and the channel-material layer.
Layer stacks claimed or described, ordered top of device to substrate.
Enhancement Mode MIS-HEMT (EMISHEMT) with GaN channel regrowth
Materials described outside the worked examples.
GaN (channel layer)
GaN
Silicon Nitride
Si₃N₄
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 illustrates bandgaps and bandgap offsets of example dielectric materials that may be used in the example devices of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.002–0.05 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,335,798Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section of an E-mode MISHEMT with GaN channel regrowth under a gate area, according to some example implementations. [0008]
FIG. 2 illustrates a more detailed example device structure of the E-mode MISHEMT with GaN channel regrowth under a gate area of
FIG. 3 illustrates bandgaps and bandgap offsets of example dielectric materials that may be used in the example devices of
FIG. 4 illustrates a first example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate area …
FIG. 5 illustrates a second example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 6 illustrates a third example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 7 illustrates a fourth example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 8 illustrates a fifth example device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate area of
FIG. 9 is a flowchart illustrating an example process for forming an implementation of the E-mode MISHEMT with GaN channel regrowth of under a gate area
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a High Electron Mobility Transistor (H EMT) having: a substrate; a channel layer adjacent to the substrate; a barrier layer adjacent to the channel layer and extending at least partially between a source and a drain of the HEMT, the barrier layer providing a heterojunction with the channel layer, the heterojunction causing a two-dimensional electron gas (2DEG) to occur within the channel layer between the source and the drain; a channel-material layer extending through a recess in the barrier layer and into the channel layer, the channel-material layer inc l udin g a channel-material portion that is within the channel layer and between the barrier layer and the s ubstrate; at least one passivation layer adjacent to the channel-material layer within the recess; at least one dielectric layer adjacent to the at least one passivation layer within the recess; and a gate adjacent to the at least one dielectric layer. wherein the channel-material portion disrupts the 2DEG when the gate is not biased and defines a disruption region between the channel-material portion and the substrate. and current flows between the source and the drain through the disruption region when a bias is applied to the gate. Currently amended
The semiconductor device of claim 1, wherein the channel-material layer formed within the recess in the barrier layer extends along a surface of the barr ier layer in a direction of a source contact of the HEMT and in a direction of a drain contact of the HEMT. Previously presented
The semiconductor device of claim 1, wherein the channel-material layer is p-doped. Original
The semiconductor device of claim 1, wherein less than 10 nm. New
The semiconductor device of claim 1, wherein layer include the same channel material. New
. Canceled
. Canceled
(Cu rr ently Amended) A High Electron Mobility Transistor (HEMT) device, comprising: a substrate; a channel layer adjacent to the substrate; a barrier layer adjacent to the channel layer and forming a heterojunction therewith, the heterojunction causing a two-dimensional electron gas (2DEG) to occur within the channel layer; a channel-material layer formed at least partially within a recess in the ba rr ier layer and including a portion that extends into the channel layer; at least one passivation layer adjacent to the channel-material layer within the recess; at least one dielectric layer adjacent to the at least one passivation layer within the recess; a gate adjacent to the at least one dielectric layer; and a source and a drain formed at opposing ends of the 2DEG to define a current channel between the source and the drain that extends through the channel layer, the cu rr ent channel including a region of the channel layer adjacent to the portion of the channel-material layer, wherein the channel-material layer, the at least one passivation layer, and the at least one dielectric layer extend in a direction of the source and in a direction of the drain s wherein the portion of the channel-material layer disrupts the 2DEG when the gate is not biased and defines a disruption region between the portion of the channel-material layer and the substrate, and current flows between the source and the drain through the disruption region when a bias is applied to the gate. Currently amended
The HEMT of claim 10, wherein the channel-material layer extends along sidewalls of the recess. Previously presented
The HEMT of claim 10, wherein the at least one dielectric layer includes an oxide having a bandgap offset relative to both a conduction band and a valence band of the channel layer and the channel-material layer. Previously presented
(Cu rr ently Amended) The HEMT of claim 10, wherein the substrate includes a Sapphire substrate. Currently amended
The HEMT of claim 10, wherein the channel-material layer is p-doped. Original
. Canceled
A method of making a High Electron Mobility Transistor (HEMT), comprising: forming a layer stack that includes at least a channel layer and a ba rr ier layer adjacent to the channel layer and forming a heterojunction at which a current channel is defined in the channel layer; forming a recess in the ba rr ier layer that extends into the channel layer; SVG 16734649.12-03-2021.KWQUHEWHLDFLYX9.CLM.1.svg 0.16 3.38 Black and white forming at least one dielectric layer adjacent to the channel-material layer; forming a gate adjacent to the at least one dielectric layer; and forming a source and drain at opposing ends of the current channel. Withdrawn
The method of claim 17, wherein forming the recess comprises a first etching process to etch through the barrier layer to an etch stop layer in the layer stack between the channel layer and the barrier layer, and further wherein forming the channel- material layer includes a second etch process to etch into the channel layer. Withdrawn
The method of claim 17, wherein forming the at least one dielectric layer comprises: forming the at least one dielectric layer in-situ with the channel-material layer. Withdrawn
The method of claim 17, wherein forming the at least one dielectric layer comprises: SVG 16734649.12-03-2021.KWQUHEWHLDFLYX9.CLM.2.svg insulating layer with a bandgap offset relative to the channel layer and the channel-material layer.
Layer stacks claimed or described, ordered top of device to substrate.
Enhancement Mode MIS-HEMT (EMISHEMT) with GaN channel regrowth
Materials described outside the worked examples.
GaN (channel layer)
GaN
Silicon Nitride
Si₃N₄
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 illustrates bandgaps and bandgap offsets of example dielectric materials that may be used in the example devices of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.002–0.05 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,335,798Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section of an E-mode MISHEMT with GaN channel regrowth under a gate area, according to some example implementations. [0008]
FIG. 2 illustrates a more detailed example device structure of the E-mode MISHEMT with GaN channel regrowth under a gate area of
FIG. 3 illustrates bandgaps and bandgap offsets of example dielectric materials that may be used in the example devices of
FIG. 4 illustrates a first example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate area …
FIG. 5 illustrates a second example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 6 illustrates a third example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 7 illustrates a fourth example intermediate device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate …
FIG. 8 illustrates a fifth example device structure for forming an implementation of the E-mode MISHEMT with GaN channel regrowth under a gate area of
FIG. 9 is a flowchart illustrating an example process for forming an implementation of the E-mode MISHEMT with GaN channel regrowth of under a gate area
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a High Electron Mobility Transistor (H EMT) having: a substrate; a channel layer adjacent to the substrate; a barrier layer adjacent to the channel layer and extending at least partially between a source and a drain of the HEMT, the barrier layer providing a heterojunction with the channel layer, the heterojunction causing a two-dimensional electron gas (2DEG) to occur within the channel layer between the source and the drain; a channel-material layer extending through a recess in the barrier layer and into the channel layer, the channel-material layer inc l udin g a channel-material portion that is within the channel layer and between the barrier layer and the s ubstrate; at least one passivation layer adjacent to the channel-material layer within the recess; at least one dielectric layer adjacent to the at least one passivation layer within the recess; and a gate adjacent to the at least one dielectric layer. wherein the channel-material portion disrupts the 2DEG when the gate is not biased and defines a disruption region between the channel-material portion and the substrate. and current flows between the source and the drain through the disruption region when a bias is applied to the gate. Currently amended
The semiconductor device of claim 1, wherein the channel-material layer formed within the recess in the barrier layer extends along a surface of the barr ier layer in a direction of a source contact of the HEMT and in a direction of a drain contact of the HEMT. Previously presented
The semiconductor device of claim 1, wherein the channel-material layer is p-doped. Original
The semiconductor device of claim 1, wherein less than 10 nm. New
The semiconductor device of claim 1, wherein layer include the same channel material. New
. Canceled
. Canceled
(Cu rr ently Amended) A High Electron Mobility Transistor (HEMT) device, comprising: a substrate; a channel layer adjacent to the substrate; a barrier layer adjacent to the channel layer and forming a heterojunction therewith, the heterojunction causing a two-dimensional electron gas (2DEG) to occur within the channel layer; a channel-material layer formed at least partially within a recess in the ba rr ier layer and including a portion that extends into the channel layer; at least one passivation layer adjacent to the channel-material layer within the recess; at least one dielectric layer adjacent to the at least one passivation layer within the recess; a gate adjacent to the at least one dielectric layer; and a source and a drain formed at opposing ends of the 2DEG to define a current channel between the source and the drain that extends through the channel layer, the cu rr ent channel including a region of the channel layer adjacent to the portion of the channel-material layer, wherein the channel-material layer, the at least one passivation layer, and the at least one dielectric layer extend in a direction of the source and in a direction of the drain s wherein the portion of the channel-material layer disrupts the 2DEG when the gate is not biased and defines a disruption region between the portion of the channel-material layer and the substrate, and current flows between the source and the drain through the disruption region when a bias is applied to the gate. Currently amended
The HEMT of claim 10, wherein the channel-material layer extends along sidewalls of the recess. Previously presented
The HEMT of claim 10, wherein the at least one dielectric layer includes an oxide having a bandgap offset relative to both a conduction band and a valence band of the channel layer and the channel-material layer. Previously presented
(Cu rr ently Amended) The HEMT of claim 10, wherein the substrate includes a Sapphire substrate. Currently amended
The HEMT of claim 10, wherein the channel-material layer is p-doped. Original
. Canceled
A method of making a High Electron Mobility Transistor (HEMT), comprising: forming a layer stack that includes at least a channel layer and a ba rr ier layer adjacent to the channel layer and forming a heterojunction at which a current channel is defined in the channel layer; forming a recess in the ba rr ier layer that extends into the channel layer; SVG 16734649.12-03-2021.KWQUHEWHLDFLYX9.CLM.1.svg 0.16 3.38 Black and white forming at least one dielectric layer adjacent to the channel-material layer; forming a gate adjacent to the at least one dielectric layer; and forming a source and drain at opposing ends of the current channel. Withdrawn
The method of claim 17, wherein forming the recess comprises a first etching process to etch through the barrier layer to an etch stop layer in the layer stack between the channel layer and the barrier layer, and further wherein forming the channel- material layer includes a second etch process to etch into the channel layer. Withdrawn
The method of claim 17, wherein forming the at least one dielectric layer comprises: forming the at least one dielectric layer in-situ with the channel-material layer. Withdrawn
The method of claim 17, wherein forming the at least one dielectric layer comprises: SVG 16734649.12-03-2021.KWQUHEWHLDFLYX9.CLM.2.svg insulating layer with a bandgap offset relative to the channel layer and the channel-material layer.
Layer stacks claimed or described, ordered top of device to substrate.
Enhancement Mode MIS-HEMT (EMISHEMT) with GaN channel regrowth
Materials described outside the worked examples.
GaN (channel layer)
GaN
Silicon Nitride
Si₃N₄
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 illustrates bandgaps and bandgap offsets of example dielectric materials that may be used in the example devices of
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.002–0.05 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
oxide dielectric (e.g., SiO₂ or alumina)
Sapphire substrate
Al₂O₃
AlGaN (barrier layer)
AlGaN
carbon-doped GaN (HV blocking layer)
GaN:C
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
| 35–50 nm |
| — |
Thickness | ≤ 10 nm | — |
oxide dielectric (e.g., SiO₂ or alumina)
Sapphire substrate
Al₂O₃
AlGaN (barrier layer)
AlGaN
carbon-doped GaN (HV blocking layer)
GaN:C
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
| 35–50 nm |
| — |
Thickness | ≤ 10 nm | — |
oxide dielectric (e.g., SiO₂ or alumina)
Sapphire substrate
Al₂O₃
AlGaN (barrier layer)
AlGaN
carbon-doped GaN (HV blocking layer)
GaN:C
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
| 35–50 nm |
| — |
Thickness | ≤ 10 nm | — |
oxide dielectric (e.g., SiO₂ or alumina)
Sapphire substrate
Al₂O₃
AlGaN (barrier layer)
AlGaN
carbon-doped GaN (HV blocking layer)
GaN:C
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
FIG. 10 is a graph illustrating a drain current as a function of gate potential for example embodiments.
| 35–50 nm |
| — |
Thickness | ≤ 10 nm | — |