Patent
US 11,527,610CMOS COMPATIBLE ISOLATION LEAKAGE IMPROVEMENTS IN GALLIUM NITRIDE TRANSISTORS
Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Han Wui THEN
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,527,610Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 2A and 2B are cross-sectional illustrations of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the first embodiment.
Figure 3 is a graph illustrating leakage improvement between a structure comprising a trench filled with standard materials.
Figure 4 is a cross-sectional illustration of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the second embodiment.
Figures 5A-5G are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors having a shallow trench isolation structure in accordance with the first embodiment.
Figures 6A-6F are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors separated by an isolation structure comprising at least two gaps in the I II -N substrate and the dielectric material separating the two transistors in accordance with the second …
Figures 7A and 7B are top views of a wafer and dies that include one or more III- N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more I -N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 9 illustrates a computing device in accordance with one implementation of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
The integrated circuit structure of claim 4-10, wherein the first I II-N transistor and the second I II -N transistor comprise gallium nitride (GaN) transistors. Currently amended
Canceled
The integrated circuit structure of claim 4-10, wherein the shallow trench is filled with a bilayer stack comprising a high-K dielectric liner formed on the sidewalls and a bottom of the shallow trench, and the oxide, nitride or low-K dielectric formed on the high- K dielectric and filling a remainder of the shallow trench. Currently amended
The integrated circuit structure of claim 4, wherein the high-K dielectric liner comprises one of aluminum oxide and hafnium oxide. Original
The integrated circuit structure of claim 4, wherein the high-K dielectric liner is approximately 2 nm in thickness. Original
The integrated circuit structure of claim 4-10, wherein the shallow trench extends into the I II-N substrate to a depth of approximately 200 nm to 500 nm. Currently amended
The integrated circuit structure of claim 4-10, wherein sides of the respective source and drain regions of the first I II -N transistor and the second I II -N transistor form sidewalls of the shallow trench. Currently amended
The integrated circuit structure of claim 4-10, wherein a width of the shallow trench is approximately 300 nm to several microns. Currently amended
The integrated circuit structure of claim 4-10, wherein the first I II-N transistor comprises source and drain regions, a polarization layer on the I II -N substrate between the source and drain regions, and a gate electrode over the polarization layer. Currently amended
The integrated circuit structure of claim 4-10, wherein the second III -N transistor comprises source and drain regions, a polarization layer on the I II -N substrate between the source and drain regions, and a gate electrode over the polarization layer. Currently amended
An integrated circuit structure, comprising: a silicon substrate; a I II -nitride (I II -N) substrate over the silicon substrate; a first I II -N transistor and a second I II -N transistor on the I II -N substrate; and an insulator structure formed in the I II -N substrate between the first I II -N transistor and the second I II -N transistor, wherein the insulator structure comprises one of. a shallow trench filled with an oxide, nitride or low-K dielectric, wherein the oxide, nitride or low-K dielectric is coplanar with a top of metal contacts on the respective source and drain regions of the first I II -N transistor and the second I II-N transistor; or a first gap adjacent to the first I II -N transistor and a second gap adjacent to the second I II -N transistor, wherein the first gap is in contact with a source and drain region of the first I II -N transistor and the second gap is in contact with a source drain region of the second I II -N transistor, where the first gap and the second gap are separated by a dielectric material. Previously presented
The integrated circuit structure of claim 10, wherein the first gap and the second gap are filled with at least one of air, a gas, a dielectric, and a liquid. Original
The integrated circuit structure of claim 10, wherein the first gap and the second gap have respective top portions and bottom portions, wherein the top portions are located in an interlayer dielectric (ILD) at approximately 1 2 a height of the respective source and drain regions of the first I II -N transistor and the second I II -N transistor, and the bottom portions are located in the I II -N substrate at approximately one half a depth of the I II -N substrate such that the bottom portions do not contact the silicon substrate. Original
The integrated circuit structure of claim 10, wherein the first gap and the second gap and are formed as an opening with borders defined by an interlayer dielectric (ILD) along a top portion and along a first side bordered by the I II -N substrate along bottom portions; and bordered by both the source and drain regions and the I II -N substrate along a second side. Original
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Canceled
Layer stacks claimed or described, ordered top of device to substrate.
III-N transistor (GaN transistor)
shallow trench isolation structure (bilayer)
Materials described outside the worked examples.
gallium nitride
GaN
oxide, nitride or low-K dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figures 2A and 2B are cross-sectional illustrations of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the first embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–500 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,527,610Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 2A and 2B are cross-sectional illustrations of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the first embodiment.
Figure 3 is a graph illustrating leakage improvement between a structure comprising a trench filled with standard materials.
Figure 4 is a cross-sectional illustration of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the second embodiment.
Figures 5A-5G are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors having a shallow trench isolation structure in accordance with the first embodiment.
Figures 6A-6F are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors separated by an isolation structure comprising at least two gaps in the I II -N substrate and the dielectric material separating the two transistors in accordance with the second …
Figures 7A and 7B are top views of a wafer and dies that include one or more III- N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more I -N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 9 illustrates a computing device in accordance with one implementation of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
The integrated circuit structure of claim 4-10, wherein the first I II-N transistor and the second I II -N transistor comprise gallium nitride (GaN) transistors. Currently amended
Canceled
The integrated circuit structure of claim 4-10, wherein the shallow trench is filled with a bilayer stack comprising a high-K dielectric liner formed on the sidewalls and a bottom of the shallow trench, and the oxide, nitride or low-K dielectric formed on the high- K dielectric and filling a remainder of the shallow trench. Currently amended
The integrated circuit structure of claim 4, wherein the high-K dielectric liner comprises one of aluminum oxide and hafnium oxide. Original
The integrated circuit structure of claim 4, wherein the high-K dielectric liner is approximately 2 nm in thickness. Original
The integrated circuit structure of claim 4-10, wherein the shallow trench extends into the I II-N substrate to a depth of approximately 200 nm to 500 nm. Currently amended
The integrated circuit structure of claim 4-10, wherein sides of the respective source and drain regions of the first I II -N transistor and the second I II -N transistor form sidewalls of the shallow trench. Currently amended
The integrated circuit structure of claim 4-10, wherein a width of the shallow trench is approximately 300 nm to several microns. Currently amended
The integrated circuit structure of claim 4-10, wherein the first I II-N transistor comprises source and drain regions, a polarization layer on the I II -N substrate between the source and drain regions, and a gate electrode over the polarization layer. Currently amended
The integrated circuit structure of claim 4-10, wherein the second III -N transistor comprises source and drain regions, a polarization layer on the I II -N substrate between the source and drain regions, and a gate electrode over the polarization layer. Currently amended
An integrated circuit structure, comprising: a silicon substrate; a I II -nitride (I II -N) substrate over the silicon substrate; a first I II -N transistor and a second I II -N transistor on the I II -N substrate; and an insulator structure formed in the I II -N substrate between the first I II -N transistor and the second I II -N transistor, wherein the insulator structure comprises one of. a shallow trench filled with an oxide, nitride or low-K dielectric, wherein the oxide, nitride or low-K dielectric is coplanar with a top of metal contacts on the respective source and drain regions of the first I II -N transistor and the second I II-N transistor; or a first gap adjacent to the first I II -N transistor and a second gap adjacent to the second I II -N transistor, wherein the first gap is in contact with a source and drain region of the first I II -N transistor and the second gap is in contact with a source drain region of the second I II -N transistor, where the first gap and the second gap are separated by a dielectric material. Previously presented
The integrated circuit structure of claim 10, wherein the first gap and the second gap are filled with at least one of air, a gas, a dielectric, and a liquid. Original
The integrated circuit structure of claim 10, wherein the first gap and the second gap have respective top portions and bottom portions, wherein the top portions are located in an interlayer dielectric (ILD) at approximately 1 2 a height of the respective source and drain regions of the first I II -N transistor and the second I II -N transistor, and the bottom portions are located in the I II -N substrate at approximately one half a depth of the I II -N substrate such that the bottom portions do not contact the silicon substrate. Original
The integrated circuit structure of claim 10, wherein the first gap and the second gap and are formed as an opening with borders defined by an interlayer dielectric (ILD) along a top portion and along a first side bordered by the I II -N substrate along bottom portions; and bordered by both the source and drain regions and the I II -N substrate along a second side. Original
Canceled
Canceled
Canceled
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
III-N transistor (GaN transistor)
shallow trench isolation structure (bilayer)
Materials described outside the worked examples.
gallium nitride
GaN
oxide, nitride or low-K dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figures 2A and 2B are cross-sectional illustrations of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the first embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–500 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,527,610Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 2A and 2B are cross-sectional illustrations of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the first embodiment.
Figure 3 is a graph illustrating leakage improvement between a structure comprising a trench filled with standard materials.
Figure 4 is a cross-sectional illustration of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the second embodiment.
Figures 5A-5G are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors having a shallow trench isolation structure in accordance with the first embodiment.
Figures 6A-6F are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors separated by an isolation structure comprising at least two gaps in the I II -N substrate and the dielectric material separating the two transistors in accordance with the second …
Figures 7A and 7B are top views of a wafer and dies that include one or more III- N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more I -N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 9 illustrates a computing device in accordance with one implementation of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
The integrated circuit structure of claim 4-10, wherein the first I II-N transistor and the second I II -N transistor comprise gallium nitride (GaN) transistors. Currently amended
Canceled
The integrated circuit structure of claim 4-10, wherein the shallow trench is filled with a bilayer stack comprising a high-K dielectric liner formed on the sidewalls and a bottom of the shallow trench, and the oxide, nitride or low-K dielectric formed on the high- K dielectric and filling a remainder of the shallow trench. Currently amended
The integrated circuit structure of claim 4, wherein the high-K dielectric liner comprises one of aluminum oxide and hafnium oxide. Original
The integrated circuit structure of claim 4, wherein the high-K dielectric liner is approximately 2 nm in thickness. Original
The integrated circuit structure of claim 4-10, wherein the shallow trench extends into the I II-N substrate to a depth of approximately 200 nm to 500 nm. Currently amended
The integrated circuit structure of claim 4-10, wherein sides of the respective source and drain regions of the first I II -N transistor and the second I II -N transistor form sidewalls of the shallow trench. Currently amended
The integrated circuit structure of claim 4-10, wherein a width of the shallow trench is approximately 300 nm to several microns. Currently amended
The integrated circuit structure of claim 4-10, wherein the first I II-N transistor comprises source and drain regions, a polarization layer on the I II -N substrate between the source and drain regions, and a gate electrode over the polarization layer. Currently amended
The integrated circuit structure of claim 4-10, wherein the second III -N transistor comprises source and drain regions, a polarization layer on the I II -N substrate between the source and drain regions, and a gate electrode over the polarization layer. Currently amended
An integrated circuit structure, comprising: a silicon substrate; a I II -nitride (I II -N) substrate over the silicon substrate; a first I II -N transistor and a second I II -N transistor on the I II -N substrate; and an insulator structure formed in the I II -N substrate between the first I II -N transistor and the second I II -N transistor, wherein the insulator structure comprises one of. a shallow trench filled with an oxide, nitride or low-K dielectric, wherein the oxide, nitride or low-K dielectric is coplanar with a top of metal contacts on the respective source and drain regions of the first I II -N transistor and the second I II-N transistor; or a first gap adjacent to the first I II -N transistor and a second gap adjacent to the second I II -N transistor, wherein the first gap is in contact with a source and drain region of the first I II -N transistor and the second gap is in contact with a source drain region of the second I II -N transistor, where the first gap and the second gap are separated by a dielectric material. Previously presented
The integrated circuit structure of claim 10, wherein the first gap and the second gap are filled with at least one of air, a gas, a dielectric, and a liquid. Original
The integrated circuit structure of claim 10, wherein the first gap and the second gap have respective top portions and bottom portions, wherein the top portions are located in an interlayer dielectric (ILD) at approximately 1 2 a height of the respective source and drain regions of the first I II -N transistor and the second I II -N transistor, and the bottom portions are located in the I II -N substrate at approximately one half a depth of the I II -N substrate such that the bottom portions do not contact the silicon substrate. Original
The integrated circuit structure of claim 10, wherein the first gap and the second gap and are formed as an opening with borders defined by an interlayer dielectric (ILD) along a top portion and along a first side bordered by the I II -N substrate along bottom portions; and bordered by both the source and drain regions and the I II -N substrate along a second side. Original
Canceled
Canceled
Canceled
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
III-N transistor (GaN transistor)
shallow trench isolation structure (bilayer)
Materials described outside the worked examples.
gallium nitride
GaN
oxide, nitride or low-K dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figures 2A and 2B are cross-sectional illustrations of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the first embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–500 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,527,610Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 2A and 2B are cross-sectional illustrations of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the first embodiment.
Figure 3 is a graph illustrating leakage improvement between a structure comprising a trench filled with standard materials.
Figure 4 is a cross-sectional illustration of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the second embodiment.
Figures 5A-5G are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors having a shallow trench isolation structure in accordance with the first embodiment.
Figures 6A-6F are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors separated by an isolation structure comprising at least two gaps in the I II -N substrate and the dielectric material separating the two transistors in accordance with the second …
Figures 7A and 7B are top views of a wafer and dies that include one or more III- N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more I -N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 9 illustrates a computing device in accordance with one implementation of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
The integrated circuit structure of claim 4-10, wherein the first I II-N transistor and the second I II -N transistor comprise gallium nitride (GaN) transistors. Currently amended
Canceled
The integrated circuit structure of claim 4-10, wherein the shallow trench is filled with a bilayer stack comprising a high-K dielectric liner formed on the sidewalls and a bottom of the shallow trench, and the oxide, nitride or low-K dielectric formed on the high- K dielectric and filling a remainder of the shallow trench. Currently amended
The integrated circuit structure of claim 4, wherein the high-K dielectric liner comprises one of aluminum oxide and hafnium oxide. Original
The integrated circuit structure of claim 4, wherein the high-K dielectric liner is approximately 2 nm in thickness. Original
The integrated circuit structure of claim 4-10, wherein the shallow trench extends into the I II-N substrate to a depth of approximately 200 nm to 500 nm. Currently amended
The integrated circuit structure of claim 4-10, wherein sides of the respective source and drain regions of the first I II -N transistor and the second I II -N transistor form sidewalls of the shallow trench. Currently amended
The integrated circuit structure of claim 4-10, wherein a width of the shallow trench is approximately 300 nm to several microns. Currently amended
The integrated circuit structure of claim 4-10, wherein the first I II-N transistor comprises source and drain regions, a polarization layer on the I II -N substrate between the source and drain regions, and a gate electrode over the polarization layer. Currently amended
The integrated circuit structure of claim 4-10, wherein the second III -N transistor comprises source and drain regions, a polarization layer on the I II -N substrate between the source and drain regions, and a gate electrode over the polarization layer. Currently amended
An integrated circuit structure, comprising: a silicon substrate; a I II -nitride (I II -N) substrate over the silicon substrate; a first I II -N transistor and a second I II -N transistor on the I II -N substrate; and an insulator structure formed in the I II -N substrate between the first I II -N transistor and the second I II -N transistor, wherein the insulator structure comprises one of. a shallow trench filled with an oxide, nitride or low-K dielectric, wherein the oxide, nitride or low-K dielectric is coplanar with a top of metal contacts on the respective source and drain regions of the first I II -N transistor and the second I II-N transistor; or a first gap adjacent to the first I II -N transistor and a second gap adjacent to the second I II -N transistor, wherein the first gap is in contact with a source and drain region of the first I II -N transistor and the second gap is in contact with a source drain region of the second I II -N transistor, where the first gap and the second gap are separated by a dielectric material. Previously presented
The integrated circuit structure of claim 10, wherein the first gap and the second gap are filled with at least one of air, a gas, a dielectric, and a liquid. Original
The integrated circuit structure of claim 10, wherein the first gap and the second gap have respective top portions and bottom portions, wherein the top portions are located in an interlayer dielectric (ILD) at approximately 1 2 a height of the respective source and drain regions of the first I II -N transistor and the second I II -N transistor, and the bottom portions are located in the I II -N substrate at approximately one half a depth of the I II -N substrate such that the bottom portions do not contact the silicon substrate. Original
The integrated circuit structure of claim 10, wherein the first gap and the second gap and are formed as an opening with borders defined by an interlayer dielectric (ILD) along a top portion and along a first side bordered by the I II -N substrate along bottom portions; and bordered by both the source and drain regions and the I II -N substrate along a second side. Original
Canceled
Canceled
Canceled
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
III-N transistor (GaN transistor)
shallow trench isolation structure (bilayer)
Materials described outside the worked examples.
gallium nitride
GaN
oxide, nitride or low-K dielectric
Measurements and analyses referenced in the patent, with their drawing references.
Figures 2A and 2B are cross-sectional illustrations of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the first embodiment.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–500 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
air-gap isolation structure
high-K dielectric liner
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
III-nitride substrate
indium nitride
InN
aluminum nitride
AlN
C-doped SiOx
silicon nitride
SiN
Figure 3 is a graph illustrating leakage improvement between a structure comprising a trench filled with standard materials.
Figure 4 is a cross-sectional illustration of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the second embodiment.
Figures 5A-5G are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors having a shallow trench isolation structure in accordance with the first embodiment.
Figures 6A-6F are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors separated by an isolation structure comprising at least two gaps in the I II -N substrate and the dielectric material separating the two transistors in accordance with the second …
Figures 7A and 7B are top views of a wafer and dies that include one or more III- N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more I -N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
| — |
air-gap isolation structure
high-K dielectric liner
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
III-nitride substrate
indium nitride
InN
aluminum nitride
AlN
C-doped SiOx
silicon nitride
SiN
Figure 3 is a graph illustrating leakage improvement between a structure comprising a trench filled with standard materials.
Figure 4 is a cross-sectional illustration of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the second embodiment.
Figures 5A-5G are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors having a shallow trench isolation structure in accordance with the first embodiment.
Figures 6A-6F are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors separated by an isolation structure comprising at least two gaps in the I II -N substrate and the dielectric material separating the two transistors in accordance with the second …
Figures 7A and 7B are top views of a wafer and dies that include one or more III- N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more I -N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
| — |
air-gap isolation structure
high-K dielectric liner
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
III-nitride substrate
indium nitride
InN
aluminum nitride
AlN
C-doped SiOx
silicon nitride
SiN
Figure 3 is a graph illustrating leakage improvement between a structure comprising a trench filled with standard materials.
Figure 4 is a cross-sectional illustration of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the second embodiment.
Figures 5A-5G are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors having a shallow trench isolation structure in accordance with the first embodiment.
Figures 6A-6F are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors separated by an isolation structure comprising at least two gaps in the I II -N substrate and the dielectric material separating the two transistors in accordance with the second …
Figures 7A and 7B are top views of a wafer and dies that include one or more III- N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more I -N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
| — |
air-gap isolation structure
high-K dielectric liner
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
III-nitride substrate
indium nitride
InN
aluminum nitride
AlN
C-doped SiOx
silicon nitride
SiN
Figure 3 is a graph illustrating leakage improvement between a structure comprising a trench filled with standard materials.
Figure 4 is a cross-sectional illustration of an integrated circuit structure comprising a pair of adjacent I II -N transistors with an improved insulator structure in accordance with the second embodiment.
Figures 5A-5G are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors having a shallow trench isolation structure in accordance with the first embodiment.
Figures 6A-6F are diagrams illustrating cross-sectional views showing the fabrication of a pair of I II -N transistors separated by an isolation structure comprising at least two gaps in the I II -N substrate and the dielectric material separating the two transistors in accordance with the second …
Figures 7A and 7B are top views of a wafer and dies that include one or more III- N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
Figure 8 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more I -N transistors having CMOS compatible isolation structures, in accordance with one or more of the embodiments disclosed herein.
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