Patent
Atlas literature
Patent
US 12,300,746 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows the schematic diagram of the structure of the enhanced gallium nitride-based high-electron-mobility tran- sistor in the prior art. 40
FIG. 2 shows the structural stereogram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to …
FIG. 3 shows the schematic diagram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to release …
FIGS. 4A, 4B, 4C, and 4D show the process schematic diagrams for producing the asymmetric multi-integrated gate structure GaN HEMT transistor with the ability …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN HEMT transistor with impact energy release capability, comprising a substrate layer, a gallium nitride layer, a barrier layer, and a gate structure, arranged from bottom to top; two opposite outer sides of the barrier layer are provided with a source and a drain respectively, the source, the drain, and the barrier layer are arranged together on a top surface of the gallium nitride layer; wherein the gate structure is set near the source and comprises a p-type gallium nitride layer, dielectric layers, Ohmic metal pillars, and a Schottky metal layer; the Ohmic metal pillars comprise a main pillar partially buried inside the barrier layer, first auxiliary pillars provided on a left side of the main pillar, and second auxiliary pillars provided on a right side of the main pillar; a buried end of the main pillar contacts the top surface of the gallium nitride layer, while the other end contacts a bottom surface of the Schottky metal layer; the first auxiliary pillars have a shallower maximum burial depth inside the barrier layer compared to the 30 second auxiliary pillars, to form an asymmetric gate structure; the p-type gallium nitride layer comprises first p-type gallium nitride layers and second p-type gallium nitride layers arranged at intervals; the dielectric layers are arranged at intervals along the width direction of the B₂ gate structure on top surfaces of the first p-type gallium nitride layers, the barrier layer, and the second p-type gallium nitride layers; the dielectric layers and the Ohmic metal pillars are arranged at intervals; the top surfaces of the first p-type gallium nitride layers, the second p-type gallium nitride layers, the dielectric layers and the Ohmic metal pillars are all covered by the Schottky metal layer and in contact with the Schottky metal layer, forming multiple integrated gate structures.
The GaN HEMT transistor of claim 1, wherein burial depths of the second auxiliary pillars decrease successively in the width direction closer to the drain, one of the second auxiliary pillars closest to the drain is a shallowest second auxiliary pillar, and burial depths of the first auxiliary pillars are consistent with a burial depth of the shallowest second auxiliary pillar.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT transistor with asymmetric multi-integrated gate structure
Materials described outside the worked examples.
gallium nitride
GaN
p-type gallium nitride
p-GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows the schematic diagram of the structure of the enhanced gallium nitride-based high-electron-mobility tran- sistor in the prior art. 40
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.3–0.8 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,300,746 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows the schematic diagram of the structure of the enhanced gallium nitride-based high-electron-mobility tran- sistor in the prior art. 40
FIG. 2 shows the structural stereogram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to …
FIG. 3 shows the schematic diagram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to release …
FIGS. 4A, 4B, 4C, and 4D show the process schematic diagrams for producing the asymmetric multi-integrated gate structure GaN HEMT transistor with the ability …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN HEMT transistor with impact energy release capability, comprising a substrate layer, a gallium nitride layer, a barrier layer, and a gate structure, arranged from bottom to top; two opposite outer sides of the barrier layer are provided with a source and a drain respectively, the source, the drain, and the barrier layer are arranged together on a top surface of the gallium nitride layer; wherein the gate structure is set near the source and comprises a p-type gallium nitride layer, dielectric layers, Ohmic metal pillars, and a Schottky metal layer; the Ohmic metal pillars comprise a main pillar partially buried inside the barrier layer, first auxiliary pillars provided on a left side of the main pillar, and second auxiliary pillars provided on a right side of the main pillar; a buried end of the main pillar contacts the top surface of the gallium nitride layer, while the other end contacts a bottom surface of the Schottky metal layer; the first auxiliary pillars have a shallower maximum burial depth inside the barrier layer compared to the 30 second auxiliary pillars, to form an asymmetric gate structure; the p-type gallium nitride layer comprises first p-type gallium nitride layers and second p-type gallium nitride layers arranged at intervals; the dielectric layers are arranged at intervals along the width direction of the B₂ gate structure on top surfaces of the first p-type gallium nitride layers, the barrier layer, and the second p-type gallium nitride layers; the dielectric layers and the Ohmic metal pillars are arranged at intervals; the top surfaces of the first p-type gallium nitride layers, the second p-type gallium nitride layers, the dielectric layers and the Ohmic metal pillars are all covered by the Schottky metal layer and in contact with the Schottky metal layer, forming multiple integrated gate structures.
The GaN HEMT transistor of claim 1, wherein burial depths of the second auxiliary pillars decrease successively in the width direction closer to the drain, one of the second auxiliary pillars closest to the drain is a shallowest second auxiliary pillar, and burial depths of the first auxiliary pillars are consistent with a burial depth of the shallowest second auxiliary pillar.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT transistor with asymmetric multi-integrated gate structure
Materials described outside the worked examples.
gallium nitride
GaN
p-type gallium nitride
p-GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows the schematic diagram of the structure of the enhanced gallium nitride-based high-electron-mobility tran- sistor in the prior art. 40
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.3–0.8 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,300,746 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows the schematic diagram of the structure of the enhanced gallium nitride-based high-electron-mobility tran- sistor in the prior art. 40
FIG. 2 shows the structural stereogram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to …
FIG. 3 shows the schematic diagram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to release …
FIGS. 4A, 4B, 4C, and 4D show the process schematic diagrams for producing the asymmetric multi-integrated gate structure GaN HEMT transistor with the ability …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN HEMT transistor with impact energy release capability, comprising a substrate layer, a gallium nitride layer, a barrier layer, and a gate structure, arranged from bottom to top; two opposite outer sides of the barrier layer are provided with a source and a drain respectively, the source, the drain, and the barrier layer are arranged together on a top surface of the gallium nitride layer; wherein the gate structure is set near the source and comprises a p-type gallium nitride layer, dielectric layers, Ohmic metal pillars, and a Schottky metal layer; the Ohmic metal pillars comprise a main pillar partially buried inside the barrier layer, first auxiliary pillars provided on a left side of the main pillar, and second auxiliary pillars provided on a right side of the main pillar; a buried end of the main pillar contacts the top surface of the gallium nitride layer, while the other end contacts a bottom surface of the Schottky metal layer; the first auxiliary pillars have a shallower maximum burial depth inside the barrier layer compared to the 30 second auxiliary pillars, to form an asymmetric gate structure; the p-type gallium nitride layer comprises first p-type gallium nitride layers and second p-type gallium nitride layers arranged at intervals; the dielectric layers are arranged at intervals along the width direction of the B₂ gate structure on top surfaces of the first p-type gallium nitride layers, the barrier layer, and the second p-type gallium nitride layers; the dielectric layers and the Ohmic metal pillars are arranged at intervals; the top surfaces of the first p-type gallium nitride layers, the second p-type gallium nitride layers, the dielectric layers and the Ohmic metal pillars are all covered by the Schottky metal layer and in contact with the Schottky metal layer, forming multiple integrated gate structures.
The GaN HEMT transistor of claim 1, wherein burial depths of the second auxiliary pillars decrease successively in the width direction closer to the drain, one of the second auxiliary pillars closest to the drain is a shallowest second auxiliary pillar, and burial depths of the first auxiliary pillars are consistent with a burial depth of the shallowest second auxiliary pillar.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT transistor with asymmetric multi-integrated gate structure
Materials described outside the worked examples.
gallium nitride
GaN
p-type gallium nitride
p-GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows the schematic diagram of the structure of the enhanced gallium nitride-based high-electron-mobility tran- sistor in the prior art. 40
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.3–0.8 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,300,746 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows the schematic diagram of the structure of the enhanced gallium nitride-based high-electron-mobility tran- sistor in the prior art. 40
FIG. 2 shows the structural stereogram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to …
FIG. 3 shows the schematic diagram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to release …
FIGS. 4A, 4B, 4C, and 4D show the process schematic diagrams for producing the asymmetric multi-integrated gate structure GaN HEMT transistor with the ability …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN HEMT transistor with impact energy release capability, comprising a substrate layer, a gallium nitride layer, a barrier layer, and a gate structure, arranged from bottom to top; two opposite outer sides of the barrier layer are provided with a source and a drain respectively, the source, the drain, and the barrier layer are arranged together on a top surface of the gallium nitride layer; wherein the gate structure is set near the source and comprises a p-type gallium nitride layer, dielectric layers, Ohmic metal pillars, and a Schottky metal layer; the Ohmic metal pillars comprise a main pillar partially buried inside the barrier layer, first auxiliary pillars provided on a left side of the main pillar, and second auxiliary pillars provided on a right side of the main pillar; a buried end of the main pillar contacts the top surface of the gallium nitride layer, while the other end contacts a bottom surface of the Schottky metal layer; the first auxiliary pillars have a shallower maximum burial depth inside the barrier layer compared to the 30 second auxiliary pillars, to form an asymmetric gate structure; the p-type gallium nitride layer comprises first p-type gallium nitride layers and second p-type gallium nitride layers arranged at intervals; the dielectric layers are arranged at intervals along the width direction of the B₂ gate structure on top surfaces of the first p-type gallium nitride layers, the barrier layer, and the second p-type gallium nitride layers; the dielectric layers and the Ohmic metal pillars are arranged at intervals; the top surfaces of the first p-type gallium nitride layers, the second p-type gallium nitride layers, the dielectric layers and the Ohmic metal pillars are all covered by the Schottky metal layer and in contact with the Schottky metal layer, forming multiple integrated gate structures.
The GaN HEMT transistor of claim 1, wherein burial depths of the second auxiliary pillars decrease successively in the width direction closer to the drain, one of the second auxiliary pillars closest to the drain is a shallowest second auxiliary pillar, and burial depths of the first auxiliary pillars are consistent with a burial depth of the shallowest second auxiliary pillar.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT transistor with asymmetric multi-integrated gate structure
Materials described outside the worked examples.
gallium nitride
GaN
p-type gallium nitride
p-GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows the schematic diagram of the structure of the enhanced gallium nitride-based high-electron-mobility tran- sistor in the prior art. 40
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.3–0.8 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
barrier layer
dielectric layer
Schottky metal layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
AlGaN/GaN heterojunction
Ohmic metal
tetramethyl amine hydroxide solution
FIG. 2 shows the structural stereogram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to …
FIG. 3 shows the schematic diagram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to release …
FIGS. 4A, 4B, 4C, and 4D show the process schematic diagrams for producing the asymmetric multi-integrated gate structure GaN HEMT transistor with the ability …
| — |
Thickness | 20–100 nm | — |
Thickness | 50–100 nm | — |
Pressure | 0.6–1.2 Pa | — |
Thickness | 0.05–0.1 µm | — |
— | 200–300 W | — |
Temperature | 800–900 °C | — |
Temperature | 300–400 °C | — |
Duration | 60–200 sec | — |
Thickness | 1000–4000 nm | — |
Thickness | 1000–5000 nm | — |
Cited non-patent literature · 2
ALGaN/GaN HYBRID MOS-HFET
barrier layer
dielectric layer
Schottky metal layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
AlGaN/GaN heterojunction
Ohmic metal
tetramethyl amine hydroxide solution
FIG. 2 shows the structural stereogram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to …
FIG. 3 shows the schematic diagram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to release …
FIGS. 4A, 4B, 4C, and 4D show the process schematic diagrams for producing the asymmetric multi-integrated gate structure GaN HEMT transistor with the ability …
| — |
Thickness | 20–100 nm | — |
Thickness | 50–100 nm | — |
Pressure | 0.6–1.2 Pa | — |
Thickness | 0.05–0.1 µm | — |
— | 200–300 W | — |
Temperature | 800–900 °C | — |
Temperature | 300–400 °C | — |
Duration | 60–200 sec | — |
Thickness | 1000–4000 nm | — |
Thickness | 1000–5000 nm | — |
Cited non-patent literature · 2
ALGaN/GaN HYBRID MOS-HFET
barrier layer
dielectric layer
Schottky metal layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
AlGaN/GaN heterojunction
Ohmic metal
tetramethyl amine hydroxide solution
FIG. 2 shows the structural stereogram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to …
FIG. 3 shows the schematic diagram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to release …
FIGS. 4A, 4B, 4C, and 4D show the process schematic diagrams for producing the asymmetric multi-integrated gate structure GaN HEMT transistor with the ability …
| — |
Thickness | 20–100 nm | — |
Thickness | 50–100 nm | — |
Pressure | 0.6–1.2 Pa | — |
Thickness | 0.05–0.1 µm | — |
— | 200–300 W | — |
Temperature | 800–900 °C | — |
Temperature | 300–400 °C | — |
Duration | 60–200 sec | — |
Thickness | 1000–4000 nm | — |
Thickness | 1000–5000 nm | — |
Cited non-patent literature · 2
ALGaN/GaN HYBRID MOS-HFET
barrier layer
dielectric layer
Schottky metal layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
AlGaN/GaN heterojunction
Ohmic metal
tetramethyl amine hydroxide solution
FIG. 2 shows the structural stereogram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to …
FIG. 3 shows the schematic diagram of the asymmetric multi-integrated gate structure GaN HEMT transistor of the present invention with the ability to release …
FIGS. 4A, 4B, 4C, and 4D show the process schematic diagrams for producing the asymmetric multi-integrated gate structure GaN HEMT transistor with the ability …
| — |
Thickness | 20–100 nm | — |
Thickness | 50–100 nm | — |
Pressure | 0.6–1.2 Pa | — |
Thickness | 0.05–0.1 µm | — |
— | 200–300 W | — |
Temperature | 800–900 °C | — |
Temperature | 300–400 °C | — |
Duration | 60–200 sec | — |
Thickness | 1000–4000 nm | — |
Thickness | 1000–5000 nm | — |
Cited non-patent literature · 2
