Patent
US 8,530,978HIGH CURRENT HIGH VOLTAGE GaN FIELD EFFECT TRANSISTORS AND METHOD OF FABRICATING SAME
Rongming Chu
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,530,978Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an elevation sectional view of a FET with a source connected slant field plate in accordance with the present disclosure; [0012] FIG s. 2A-2D show …
FIG. 2B. The gray scale mask 44 has the effect of tapering the illumination intensity between the gate 24 and the drain 26 to create a sloped sidewall 47 on the …
FIG. 3 shows a slanted trench formed using methods in accordance with the present disclosure; [0014]
FIG. 4B shows a simulation of the electric-field for a source connected slant field- plate structure in accordance with the present disclosure; and 4 [0015]
FIG. 5 is a flow diagram of a method of fabricating a source connected slant field plate in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET) having a source contact to a channel layer, a drain contact to the channel layer, and a gate contact on a barrier layer over the channel layer, the FET comprising: a dielectric layer on the barrier layer between the source contact and the drain contact and over the gate contact; and a field plate on the dielectric layer, the field plate connected to the source contact and extending over a space between the gate contact and the drain contact and the field plate comprising a sloped sidewall in the space between the gate contact and the drain contact.
The field effect transistor (FET) of claim 1 wherein a lateral dimension of the sloped sidewall between the gate contact and the drain contact is at least 1 micrometer.
The field effect transistor (FET) of claim 1 wherein the sloped sidewall is sloped such that near the gate contact the sloped sidewall is closer to the barrier layer than the sloped sidewall is farther away from the gate contact.
The field effect transistor (FET) of claim 1 wherein an angle of the sloped sidewall is approximately 30 degrees relative to a plane of the barrier layer.
The field effect transistor (FET) of claim 1 wherein the sloped sidewall is curved.
6. The field effect transistor (FET) of claim 1 wherein the sloped sidewall shapes the electric field between the gate contact and the drain contact.
The method of claim 10 wherein the third sloped sidewall is sloped such that the third sloped sidewall near the gate contact is closer to the barrier layer than the third sloped sidewall further away from gate contact.
The method of claim 10 wherein an angle of the third sloped sidewall is approximately degrees relative to a plane of the barrier layer.
The method of claim 10 wherein the third sloped sidewall is curved.
The method of claim 10 wherein the third sloped sidewall shapes the electric field between the gate contact and the drain contact.
The method of claim 10 wherein the source contact, the gate contact, the drain contact, and the field plate are metal.
The method of claim 10 wherein the mask comprises a gray scale mask.
The method of claim 10 wherein the mask comprises a portion that masks the illumination intensity to vary linearly between the gate contact and the drain contact.
The method of claim 10 wherein the field plate is insulated from the gate contact and the drain contact by the dielectric.
Layer stacks claimed or described, ordered top of device to substrate.
GaN field effect transistor with source-connected slant field plate
Materials described outside the worked examples.
dielectric layer
channel layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows an elevation sectional view of a FET with a source connected slant field plate in accordance with the present disclosure; [0012] FIG s. 2A-2D show …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 1 µm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,530,978Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an elevation sectional view of a FET with a source connected slant field plate in accordance with the present disclosure; [0012] FIG s. 2A-2D show …
FIG. 2B. The gray scale mask 44 has the effect of tapering the illumination intensity between the gate 24 and the drain 26 to create a sloped sidewall 47 on the …
FIG. 3 shows a slanted trench formed using methods in accordance with the present disclosure; [0014]
FIG. 4B shows a simulation of the electric-field for a source connected slant field- plate structure in accordance with the present disclosure; and 4 [0015]
FIG. 5 is a flow diagram of a method of fabricating a source connected slant field plate in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET) having a source contact to a channel layer, a drain contact to the channel layer, and a gate contact on a barrier layer over the channel layer, the FET comprising: a dielectric layer on the barrier layer between the source contact and the drain contact and over the gate contact; and a field plate on the dielectric layer, the field plate connected to the source contact and extending over a space between the gate contact and the drain contact and the field plate comprising a sloped sidewall in the space between the gate contact and the drain contact.
The field effect transistor (FET) of claim 1 wherein a lateral dimension of the sloped sidewall between the gate contact and the drain contact is at least 1 micrometer.
The field effect transistor (FET) of claim 1 wherein the sloped sidewall is sloped such that near the gate contact the sloped sidewall is closer to the barrier layer than the sloped sidewall is farther away from the gate contact.
The field effect transistor (FET) of claim 1 wherein an angle of the sloped sidewall is approximately 30 degrees relative to a plane of the barrier layer.
The field effect transistor (FET) of claim 1 wherein the sloped sidewall is curved.
6. The field effect transistor (FET) of claim 1 wherein the sloped sidewall shapes the electric field between the gate contact and the drain contact.
The method of claim 10 wherein the third sloped sidewall is sloped such that the third sloped sidewall near the gate contact is closer to the barrier layer than the third sloped sidewall further away from gate contact.
The method of claim 10 wherein an angle of the third sloped sidewall is approximately degrees relative to a plane of the barrier layer.
The method of claim 10 wherein the third sloped sidewall is curved.
The method of claim 10 wherein the third sloped sidewall shapes the electric field between the gate contact and the drain contact.
The method of claim 10 wherein the source contact, the gate contact, the drain contact, and the field plate are metal.
The method of claim 10 wherein the mask comprises a gray scale mask.
The method of claim 10 wherein the mask comprises a portion that masks the illumination intensity to vary linearly between the gate contact and the drain contact.
The method of claim 10 wherein the field plate is insulated from the gate contact and the drain contact by the dielectric.
Layer stacks claimed or described, ordered top of device to substrate.
GaN field effect transistor with source-connected slant field plate
Materials described outside the worked examples.
dielectric layer
channel layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows an elevation sectional view of a FET with a source connected slant field plate in accordance with the present disclosure; [0012] FIG s. 2A-2D show …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 1 µm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,530,978Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an elevation sectional view of a FET with a source connected slant field plate in accordance with the present disclosure; [0012] FIG s. 2A-2D show …
FIG. 2B. The gray scale mask 44 has the effect of tapering the illumination intensity between the gate 24 and the drain 26 to create a sloped sidewall 47 on the …
FIG. 3 shows a slanted trench formed using methods in accordance with the present disclosure; [0014]
FIG. 4B shows a simulation of the electric-field for a source connected slant field- plate structure in accordance with the present disclosure; and 4 [0015]
FIG. 5 is a flow diagram of a method of fabricating a source connected slant field plate in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET) having a source contact to a channel layer, a drain contact to the channel layer, and a gate contact on a barrier layer over the channel layer, the FET comprising: a dielectric layer on the barrier layer between the source contact and the drain contact and over the gate contact; and a field plate on the dielectric layer, the field plate connected to the source contact and extending over a space between the gate contact and the drain contact and the field plate comprising a sloped sidewall in the space between the gate contact and the drain contact.
The field effect transistor (FET) of claim 1 wherein a lateral dimension of the sloped sidewall between the gate contact and the drain contact is at least 1 micrometer.
The field effect transistor (FET) of claim 1 wherein the sloped sidewall is sloped such that near the gate contact the sloped sidewall is closer to the barrier layer than the sloped sidewall is farther away from the gate contact.
The field effect transistor (FET) of claim 1 wherein an angle of the sloped sidewall is approximately 30 degrees relative to a plane of the barrier layer.
The field effect transistor (FET) of claim 1 wherein the sloped sidewall is curved.
6. The field effect transistor (FET) of claim 1 wherein the sloped sidewall shapes the electric field between the gate contact and the drain contact.
The method of claim 10 wherein the third sloped sidewall is sloped such that the third sloped sidewall near the gate contact is closer to the barrier layer than the third sloped sidewall further away from gate contact.
The method of claim 10 wherein an angle of the third sloped sidewall is approximately degrees relative to a plane of the barrier layer.
The method of claim 10 wherein the third sloped sidewall is curved.
The method of claim 10 wherein the third sloped sidewall shapes the electric field between the gate contact and the drain contact.
The method of claim 10 wherein the source contact, the gate contact, the drain contact, and the field plate are metal.
The method of claim 10 wherein the mask comprises a gray scale mask.
The method of claim 10 wherein the mask comprises a portion that masks the illumination intensity to vary linearly between the gate contact and the drain contact.
The method of claim 10 wherein the field plate is insulated from the gate contact and the drain contact by the dielectric.
Layer stacks claimed or described, ordered top of device to substrate.
GaN field effect transistor with source-connected slant field plate
Materials described outside the worked examples.
dielectric layer
channel layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows an elevation sectional view of a FET with a source connected slant field plate in accordance with the present disclosure; [0012] FIG s. 2A-2D show …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 1 µm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,530,978Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an elevation sectional view of a FET with a source connected slant field plate in accordance with the present disclosure; [0012] FIG s. 2A-2D show …
FIG. 2B. The gray scale mask 44 has the effect of tapering the illumination intensity between the gate 24 and the drain 26 to create a sloped sidewall 47 on the …
FIG. 3 shows a slanted trench formed using methods in accordance with the present disclosure; [0014]
FIG. 4B shows a simulation of the electric-field for a source connected slant field- plate structure in accordance with the present disclosure; and 4 [0015]
FIG. 5 is a flow diagram of a method of fabricating a source connected slant field plate in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A field effect transistor (FET) having a source contact to a channel layer, a drain contact to the channel layer, and a gate contact on a barrier layer over the channel layer, the FET comprising: a dielectric layer on the barrier layer between the source contact and the drain contact and over the gate contact; and a field plate on the dielectric layer, the field plate connected to the source contact and extending over a space between the gate contact and the drain contact and the field plate comprising a sloped sidewall in the space between the gate contact and the drain contact.
The field effect transistor (FET) of claim 1 wherein a lateral dimension of the sloped sidewall between the gate contact and the drain contact is at least 1 micrometer.
The field effect transistor (FET) of claim 1 wherein the sloped sidewall is sloped such that near the gate contact the sloped sidewall is closer to the barrier layer than the sloped sidewall is farther away from the gate contact.
The field effect transistor (FET) of claim 1 wherein an angle of the sloped sidewall is approximately 30 degrees relative to a plane of the barrier layer.
The field effect transistor (FET) of claim 1 wherein the sloped sidewall is curved.
6. The field effect transistor (FET) of claim 1 wherein the sloped sidewall shapes the electric field between the gate contact and the drain contact.
The method of claim 10 wherein the third sloped sidewall is sloped such that the third sloped sidewall near the gate contact is closer to the barrier layer than the third sloped sidewall further away from gate contact.
The method of claim 10 wherein an angle of the third sloped sidewall is approximately degrees relative to a plane of the barrier layer.
The method of claim 10 wherein the third sloped sidewall is curved.
The method of claim 10 wherein the third sloped sidewall shapes the electric field between the gate contact and the drain contact.
The method of claim 10 wherein the source contact, the gate contact, the drain contact, and the field plate are metal.
The method of claim 10 wherein the mask comprises a gray scale mask.
The method of claim 10 wherein the mask comprises a portion that masks the illumination intensity to vary linearly between the gate contact and the drain contact.
The method of claim 10 wherein the field plate is insulated from the gate contact and the drain contact by the dielectric.
Layer stacks claimed or described, ordered top of device to substrate.
GaN field effect transistor with source-connected slant field plate
Materials described outside the worked examples.
dielectric layer
channel layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows an elevation sectional view of a FET with a source connected slant field plate in accordance with the present disclosure; [0012] FIG s. 2A-2D show …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 1 µm | — |
Related documents with shared materials, methods, properties, or citations.
barrier layer
field plate
metal
GaN
InN
InGaN
AlGaN
AlN
AlInN
SiN
Al₂O₃
hafnium oxide
HfO₂
titanium oxide
TiO₂
SiO₂
gold
Au
copper
Cu
aluminum
Al
FIG. 2B. The gray scale mask 44 has the effect of tapering the illumination intensity between the gate 24 and the drain 26 to create a sloped sidewall 47 on the …
GaN-BASED BIDIRECTIONAL SWITCH DEVICE
barrier layer
field plate
metal
GaN
InN
InGaN
AlGaN
AlN
AlInN
SiN
Al₂O₃
hafnium oxide
HfO₂
titanium oxide
TiO₂
SiO₂
gold
Au
copper
Cu
aluminum
Al
FIG. 2B. The gray scale mask 44 has the effect of tapering the illumination intensity between the gate 24 and the drain 26 to create a sloped sidewall 47 on the …
GaN-BASED BIDIRECTIONAL SWITCH DEVICE
barrier layer
field plate
metal
GaN
InN
InGaN
AlGaN
AlN
AlInN
SiN
Al₂O₃
hafnium oxide
HfO₂
titanium oxide
TiO₂
SiO₂
gold
Au
copper
Cu
aluminum
Al
FIG. 2B. The gray scale mask 44 has the effect of tapering the illumination intensity between the gate 24 and the drain 26 to create a sloped sidewall 47 on the …
GaN-BASED BIDIRECTIONAL SWITCH DEVICE
barrier layer
field plate
metal
GaN
InN
InGaN
AlGaN
AlN
AlInN
SiN
Al₂O₃
hafnium oxide
HfO₂
titanium oxide
TiO₂
SiO₂
gold
Au
copper
Cu
aluminum
Al
FIG. 2B. The gray scale mask 44 has the effect of tapering the illumination intensity between the gate 24 and the drain 26 to create a sloped sidewall 47 on the …