Patent
US 9,502,524COMPOUND SEMICONDUCTOR DEVICE HAVING GALLIUM NITRIDE GATE STRUCTURES
Chih-Wen HSIUNG
US
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Patent
Atlas literature
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US 9,502,524Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 2 -9 are sectional views of semiconductor structures according to various embodiments. 1 DM₂ \ 5657496 1 Attorney Docket: P₂₀₁₂₀₇₉₃US01/N1085.01488
Figures 10 through 12 are sectional views of a compound semiconductor structure having a high threshold voltage E-mode HEMT, a low threshold voltage E- mode H E MT, and a D-mode H E MT.
Figures 13 through 15 are sectional views of a compound semiconductor 5 structure having a high threshold voltage E -mode MISFET, a low threshold voltage E- mode MISFET, and a D-mode MISFET. Detailed Description [0008] It is understood that the following disclosure provides many different …
Figures 1 a through l d and the embodiments illustrated in
Figure 3, unprotected or unmasked parts of the semiconductor structure 100 are etched down to the A lXGaI N 115 layer to form access regions 135 and one or more gate stacks 120a-c. The photoresist can also be appropriately stripped. Suitable etching techniques include sputter etching, reactive gas …
Figure 4, a first layer of silicon nitride 136 is deposited onto the semiconductor structure 100. Exemplary silicon nitrides (SiN) include amorphous SiN, t r isilicon tetranitride, disilicon mononitride, and silicon mononitride. The first silicon nitride layer 136 can be deposited using a low …
Figure 5, ohmic contacts 150 are fabricated for the semiconductor structure 100 by defining one or more ohmic regions in the first silicon nitride layer 136 and depositing a suitable ohmic material in the defined ohmic regions. In one embodiment, to form an appropriate ohmic region, the first silicon …
Figure 6, a second layer of silicon nitride 138 is deposited over the ohmic contacts 150, gate structures 120a-c, and exposed portions of the first silicon nitride layer 136. In one embodiment, the second layer of silicon nitride 138 is 10 deposited using a suitable vapor deposition processes (e.g., …
Figure 7, an exemplary gate stack 120a for a high threshold voltage E -mode device is formed by selectively etching photoresist material 5 139, the second silicon nitride layer 138, and sacrificial or dummy layer 127 of dielectric material. Suitable etching techniques include exposing the …
Figure 8, an exemplary gate stack 120b for a low threshold voltage E -mode device is formed by selectively etching photoresist material 139, the second silicon nitride layer 138, sacrificial or dummy layer 127 of dielectric material, and n-GaN layer 126 using a suitable etching technique and second …
Figure 9, an exemplary gate stack 120 c for a D-mode device is formed by selectively etching photoresist material 139, the second silicon nitride layer 138, sacrificial or dummy layer 127 of dielectric material, n-GaN layer 126, Al N layer 124, and p-GaN layer 122 using a suitable etching technique …
Figure 11, a layer of suitable gate metal 162 is deposited onto the exposed surfaces of the structure 15 100 using sputter deposition, evaporation or chemical vapor deposition processes, and a layer of photoresist material 139 formed over portions of the gate metal layer 162. In a non-limiting …
Figure 12, in embodiments having layers of electrical conductors or semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be used …
Figure 14, a layer of suitable gate metal 162 is deposited onto the exposed surfaces of the structure 100 using sputter deposition, evaporation, or chemical vapor deposition processes, and a layer of photoresist material 139 formed over 15 portions of the gate metal layer 162. In a non-limiting …
Figure 15, in embodiments having layers of electrical conductors or 20 semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor structure comprising the steps of: forming an aluminum gallium nitride layer (A l GaN) on a GaN layer; and forming a first gate stack on the AlGaN layer, the first gate stack including: a I II -V compound p-type doped layer adjacent the AlGaN layer, an aluminum nitride (AIN) layer disposed on the I II -V compound p-type doped layer, a I II -V compound n-type doped layer disposed on the A I N layer, a metal layer disposed on the I II -V compound n-type doped layer; and forming a second gate stack disposed on the A l GaN layer, the second gate stack being different from the first gate stack.
The method of claim 1, wherein the second gate stack comprises a metal layer.
The method of Claim 1, further comprising the step of forming a dielectric layer underlying the metal layer of the first gate stack.
The method of Claim 1, wherein the III -V compound p-type doped layer is a p-doped GaN layer and the I II -V compound n-type doped layer is a n-doped GaN layer.
The method of Claim 1, wherein the I II -V compound p-type doped layer is doped with an impurity selected from the group consisting of magnesium, calcium, zin c, beryllium, carbon, and combinations thereof.
The method of Claim 1, wherein the I II -V compound n-type doped layer is doped with an impurity selected from the group consisting of silicon and oxygen. 3 DM2\6613959.1 DOCKET NO.: P₂₀₁₂₀₇₉₃US01 (N₁₀₈₅-01488) App l. No. 144/724,876 Reply to Office action of
A method of fo rm ing a semiconductor structure comprising the steps of: providing a substrate having an aluminum gallium nitride layer (A l GaN) on a GaN layer; and forming a first gate stack on the AlGaN layer, the first gate stack including: a III -V compound p-type doped layer adjacent the AlGaN layer, an aluminum nitride (A i N) layer disposed on the I II -V compound p-type doped layer, and a I II -V compound n-type doped layer disposed on the A l N layer, and forming a second gate stack disposed on the A l GaN layer and isolated from the first gate stack, the second gate stack having a metal layer on an A l N layer.
The method of claim 11, wherein the step of forming the first gate stack further comprises forming a metal layer disposed on the I II -V compound n-type doped layer.
The method of claim 11, wherein step of forming the second gate stack further comprises forming a III -V compound p-type doped layer adjacent the AlGaN layer, the A I N layer of the second gate stack disposed on the I II -V compound p-type doped layer of the second gate stack.
The method of claim 11, further comprising forming a dielectric layer on the I II -V compound n-type doped layer, and forming a metal layer on the I II-V compound n-type doped layer.
A method of forming a semiconductor structure comprising the steps of: forming an aluminum gallium nitride layer (AlGaN) on a GaN layer; and forming a first gate stack on the A l GaN layer, the first gate stack including: a III-V compound p-type doped layer on the AlGaN layer, SVG 14724876.04-13-2016.IMZ₅T₁ARPXXIFW3.CLM.4.11.612.1187.2160.1238.svg 0.17 5.16 Chemistry Black and white layer; and a III=V compound-n-type doped layer disposed above the-AlGaN-layer, and a metal layer disposed on the I₄₁-ompoundn-type doped= Al N layer; and forming a second gate stack disposed on the AlGaN layer and isolated from the first gate stack, the second gate stack being different from the first gate stack includinga metal4ayer adjacent4he AGan-layer:
The method of claim 16, wherein the-step of forming the first further comprising forning a third gate stack -ec o mprises comprising: forming a I II -V compound p-type doped layer adjacent the AlGaN layer, 5 DM2\6613959 1 DOCKET NO.: P₂₀₁₂₀₇₉₃US 01 (N₁₀₈₅-01488) App l. No. 144/724,876 Reply to Office action of forming an aluminum nitride (A I N) layer on the III -V compound p-type doped layer, wherein the forming a I II -V compound n-type doped layer of the first gate stack is formed o n the A I N layer of the first third gate stack: and formin g a metal layer on the III-V compound n-type doped layer of the third g ate stack.
The method of claim 16, further comprising forming a third gate stack on the AlGaN layer and isolated from the first and second gate stacks, the third gate stack including a dielectric layer above the A l GaN layer and a metal layer above
The method of claim 16, wherein the second AlGan layer. 6 DM2\6613959.1 the dielectric layer. gate stack includes a metal layer adjacent the
. canceled
The method of claim- ? 16, wherein- further comprising the step of forming SVG 14724876.04-13-2016.IMZ₅T₁ARPXXIFW3.CLM.4.20.658.2235.877.2282.svg 0.157 0.73 Chemistry Black and white gate stack eompr-ises- comprising forming a I II -V compound p- type doped layer adjacent the AlGaN layer, and forming the- an A l N layer is dispo s ed- on the I II -V compound p-type doped layer of the third gate stack.
Layer stacks claimed or described, ordered top of device to substrate.
first gate stack on AlGaN/GaN HEMT structure
Materials described outside the worked examples.
aluminum gallium nitride
AlGaN
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 12, in embodiments having layers of electrical conductors or semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be used …
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US 9,502,524Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 2 -9 are sectional views of semiconductor structures according to various embodiments. 1 DM₂ \ 5657496 1 Attorney Docket: P₂₀₁₂₀₇₉₃US01/N1085.01488
Figures 10 through 12 are sectional views of a compound semiconductor structure having a high threshold voltage E-mode HEMT, a low threshold voltage E- mode H E MT, and a D-mode H E MT.
Figures 13 through 15 are sectional views of a compound semiconductor 5 structure having a high threshold voltage E -mode MISFET, a low threshold voltage E- mode MISFET, and a D-mode MISFET. Detailed Description [0008] It is understood that the following disclosure provides many different …
Figures 1 a through l d and the embodiments illustrated in
Figure 3, unprotected or unmasked parts of the semiconductor structure 100 are etched down to the A lXGaI N 115 layer to form access regions 135 and one or more gate stacks 120a-c. The photoresist can also be appropriately stripped. Suitable etching techniques include sputter etching, reactive gas …
Figure 4, a first layer of silicon nitride 136 is deposited onto the semiconductor structure 100. Exemplary silicon nitrides (SiN) include amorphous SiN, t r isilicon tetranitride, disilicon mononitride, and silicon mononitride. The first silicon nitride layer 136 can be deposited using a low …
Figure 5, ohmic contacts 150 are fabricated for the semiconductor structure 100 by defining one or more ohmic regions in the first silicon nitride layer 136 and depositing a suitable ohmic material in the defined ohmic regions. In one embodiment, to form an appropriate ohmic region, the first silicon …
Figure 6, a second layer of silicon nitride 138 is deposited over the ohmic contacts 150, gate structures 120a-c, and exposed portions of the first silicon nitride layer 136. In one embodiment, the second layer of silicon nitride 138 is 10 deposited using a suitable vapor deposition processes (e.g., …
Figure 7, an exemplary gate stack 120a for a high threshold voltage E -mode device is formed by selectively etching photoresist material 5 139, the second silicon nitride layer 138, and sacrificial or dummy layer 127 of dielectric material. Suitable etching techniques include exposing the …
Figure 8, an exemplary gate stack 120b for a low threshold voltage E -mode device is formed by selectively etching photoresist material 139, the second silicon nitride layer 138, sacrificial or dummy layer 127 of dielectric material, and n-GaN layer 126 using a suitable etching technique and second …
Figure 9, an exemplary gate stack 120 c for a D-mode device is formed by selectively etching photoresist material 139, the second silicon nitride layer 138, sacrificial or dummy layer 127 of dielectric material, n-GaN layer 126, Al N layer 124, and p-GaN layer 122 using a suitable etching technique …
Figure 11, a layer of suitable gate metal 162 is deposited onto the exposed surfaces of the structure 15 100 using sputter deposition, evaporation or chemical vapor deposition processes, and a layer of photoresist material 139 formed over portions of the gate metal layer 162. In a non-limiting …
Figure 12, in embodiments having layers of electrical conductors or semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be used …
Figure 14, a layer of suitable gate metal 162 is deposited onto the exposed surfaces of the structure 100 using sputter deposition, evaporation, or chemical vapor deposition processes, and a layer of photoresist material 139 formed over 15 portions of the gate metal layer 162. In a non-limiting …
Figure 15, in embodiments having layers of electrical conductors or 20 semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor structure comprising the steps of: forming an aluminum gallium nitride layer (A l GaN) on a GaN layer; and forming a first gate stack on the AlGaN layer, the first gate stack including: a I II -V compound p-type doped layer adjacent the AlGaN layer, an aluminum nitride (AIN) layer disposed on the I II -V compound p-type doped layer, a I II -V compound n-type doped layer disposed on the A I N layer, a metal layer disposed on the I II -V compound n-type doped layer; and forming a second gate stack disposed on the A l GaN layer, the second gate stack being different from the first gate stack.
The method of claim 1, wherein the second gate stack comprises a metal layer.
The method of Claim 1, further comprising the step of forming a dielectric layer underlying the metal layer of the first gate stack.
The method of Claim 1, wherein the III -V compound p-type doped layer is a p-doped GaN layer and the I II -V compound n-type doped layer is a n-doped GaN layer.
The method of Claim 1, wherein the I II -V compound p-type doped layer is doped with an impurity selected from the group consisting of magnesium, calcium, zin c, beryllium, carbon, and combinations thereof.
The method of Claim 1, wherein the I II -V compound n-type doped layer is doped with an impurity selected from the group consisting of silicon and oxygen. 3 DM2\6613959.1 DOCKET NO.: P₂₀₁₂₀₇₉₃US01 (N₁₀₈₅-01488) App l. No. 144/724,876 Reply to Office action of
A method of fo rm ing a semiconductor structure comprising the steps of: providing a substrate having an aluminum gallium nitride layer (A l GaN) on a GaN layer; and forming a first gate stack on the AlGaN layer, the first gate stack including: a III -V compound p-type doped layer adjacent the AlGaN layer, an aluminum nitride (A i N) layer disposed on the I II -V compound p-type doped layer, and a I II -V compound n-type doped layer disposed on the A l N layer, and forming a second gate stack disposed on the A l GaN layer and isolated from the first gate stack, the second gate stack having a metal layer on an A l N layer.
The method of claim 11, wherein the step of forming the first gate stack further comprises forming a metal layer disposed on the I II -V compound n-type doped layer.
The method of claim 11, wherein step of forming the second gate stack further comprises forming a III -V compound p-type doped layer adjacent the AlGaN layer, the A I N layer of the second gate stack disposed on the I II -V compound p-type doped layer of the second gate stack.
The method of claim 11, further comprising forming a dielectric layer on the I II -V compound n-type doped layer, and forming a metal layer on the I II-V compound n-type doped layer.
A method of forming a semiconductor structure comprising the steps of: forming an aluminum gallium nitride layer (AlGaN) on a GaN layer; and forming a first gate stack on the A l GaN layer, the first gate stack including: a III-V compound p-type doped layer on the AlGaN layer, SVG 14724876.04-13-2016.IMZ₅T₁ARPXXIFW3.CLM.4.11.612.1187.2160.1238.svg 0.17 5.16 Chemistry Black and white layer; and a III=V compound-n-type doped layer disposed above the-AlGaN-layer, and a metal layer disposed on the I₄₁-ompoundn-type doped= Al N layer; and forming a second gate stack disposed on the AlGaN layer and isolated from the first gate stack, the second gate stack being different from the first gate stack includinga metal4ayer adjacent4he AGan-layer:
The method of claim 16, wherein the-step of forming the first further comprising forning a third gate stack -ec o mprises comprising: forming a I II -V compound p-type doped layer adjacent the AlGaN layer, 5 DM2\6613959 1 DOCKET NO.: P₂₀₁₂₀₇₉₃US 01 (N₁₀₈₅-01488) App l. No. 144/724,876 Reply to Office action of forming an aluminum nitride (A I N) layer on the III -V compound p-type doped layer, wherein the forming a I II -V compound n-type doped layer of the first gate stack is formed o n the A I N layer of the first third gate stack: and formin g a metal layer on the III-V compound n-type doped layer of the third g ate stack.
The method of claim 16, further comprising forming a third gate stack on the AlGaN layer and isolated from the first and second gate stacks, the third gate stack including a dielectric layer above the A l GaN layer and a metal layer above
The method of claim 16, wherein the second AlGan layer. 6 DM2\6613959.1 the dielectric layer. gate stack includes a metal layer adjacent the
. canceled
The method of claim- ? 16, wherein- further comprising the step of forming SVG 14724876.04-13-2016.IMZ₅T₁ARPXXIFW3.CLM.4.20.658.2235.877.2282.svg 0.157 0.73 Chemistry Black and white gate stack eompr-ises- comprising forming a I II -V compound p- type doped layer adjacent the AlGaN layer, and forming the- an A l N layer is dispo s ed- on the I II -V compound p-type doped layer of the third gate stack.
Layer stacks claimed or described, ordered top of device to substrate.
first gate stack on AlGaN/GaN HEMT structure
Materials described outside the worked examples.
aluminum gallium nitride
AlGaN
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 12, in embodiments having layers of electrical conductors or semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be used …
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US 9,502,524Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 2 -9 are sectional views of semiconductor structures according to various embodiments. 1 DM₂ \ 5657496 1 Attorney Docket: P₂₀₁₂₀₇₉₃US01/N1085.01488
Figures 10 through 12 are sectional views of a compound semiconductor structure having a high threshold voltage E-mode HEMT, a low threshold voltage E- mode H E MT, and a D-mode H E MT.
Figures 13 through 15 are sectional views of a compound semiconductor 5 structure having a high threshold voltage E -mode MISFET, a low threshold voltage E- mode MISFET, and a D-mode MISFET. Detailed Description [0008] It is understood that the following disclosure provides many different …
Figures 1 a through l d and the embodiments illustrated in
Figure 3, unprotected or unmasked parts of the semiconductor structure 100 are etched down to the A lXGaI N 115 layer to form access regions 135 and one or more gate stacks 120a-c. The photoresist can also be appropriately stripped. Suitable etching techniques include sputter etching, reactive gas …
Figure 4, a first layer of silicon nitride 136 is deposited onto the semiconductor structure 100. Exemplary silicon nitrides (SiN) include amorphous SiN, t r isilicon tetranitride, disilicon mononitride, and silicon mononitride. The first silicon nitride layer 136 can be deposited using a low …
Figure 5, ohmic contacts 150 are fabricated for the semiconductor structure 100 by defining one or more ohmic regions in the first silicon nitride layer 136 and depositing a suitable ohmic material in the defined ohmic regions. In one embodiment, to form an appropriate ohmic region, the first silicon …
Figure 6, a second layer of silicon nitride 138 is deposited over the ohmic contacts 150, gate structures 120a-c, and exposed portions of the first silicon nitride layer 136. In one embodiment, the second layer of silicon nitride 138 is 10 deposited using a suitable vapor deposition processes (e.g., …
Figure 7, an exemplary gate stack 120a for a high threshold voltage E -mode device is formed by selectively etching photoresist material 5 139, the second silicon nitride layer 138, and sacrificial or dummy layer 127 of dielectric material. Suitable etching techniques include exposing the …
Figure 8, an exemplary gate stack 120b for a low threshold voltage E -mode device is formed by selectively etching photoresist material 139, the second silicon nitride layer 138, sacrificial or dummy layer 127 of dielectric material, and n-GaN layer 126 using a suitable etching technique and second …
Figure 9, an exemplary gate stack 120 c for a D-mode device is formed by selectively etching photoresist material 139, the second silicon nitride layer 138, sacrificial or dummy layer 127 of dielectric material, n-GaN layer 126, Al N layer 124, and p-GaN layer 122 using a suitable etching technique …
Figure 11, a layer of suitable gate metal 162 is deposited onto the exposed surfaces of the structure 15 100 using sputter deposition, evaporation or chemical vapor deposition processes, and a layer of photoresist material 139 formed over portions of the gate metal layer 162. In a non-limiting …
Figure 12, in embodiments having layers of electrical conductors or semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be used …
Figure 14, a layer of suitable gate metal 162 is deposited onto the exposed surfaces of the structure 100 using sputter deposition, evaporation, or chemical vapor deposition processes, and a layer of photoresist material 139 formed over 15 portions of the gate metal layer 162. In a non-limiting …
Figure 15, in embodiments having layers of electrical conductors or 20 semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor structure comprising the steps of: forming an aluminum gallium nitride layer (A l GaN) on a GaN layer; and forming a first gate stack on the AlGaN layer, the first gate stack including: a I II -V compound p-type doped layer adjacent the AlGaN layer, an aluminum nitride (AIN) layer disposed on the I II -V compound p-type doped layer, a I II -V compound n-type doped layer disposed on the A I N layer, a metal layer disposed on the I II -V compound n-type doped layer; and forming a second gate stack disposed on the A l GaN layer, the second gate stack being different from the first gate stack.
The method of claim 1, wherein the second gate stack comprises a metal layer.
The method of Claim 1, further comprising the step of forming a dielectric layer underlying the metal layer of the first gate stack.
The method of Claim 1, wherein the III -V compound p-type doped layer is a p-doped GaN layer and the I II -V compound n-type doped layer is a n-doped GaN layer.
The method of Claim 1, wherein the I II -V compound p-type doped layer is doped with an impurity selected from the group consisting of magnesium, calcium, zin c, beryllium, carbon, and combinations thereof.
The method of Claim 1, wherein the I II -V compound n-type doped layer is doped with an impurity selected from the group consisting of silicon and oxygen. 3 DM2\6613959.1 DOCKET NO.: P₂₀₁₂₀₇₉₃US01 (N₁₀₈₅-01488) App l. No. 144/724,876 Reply to Office action of
A method of fo rm ing a semiconductor structure comprising the steps of: providing a substrate having an aluminum gallium nitride layer (A l GaN) on a GaN layer; and forming a first gate stack on the AlGaN layer, the first gate stack including: a III -V compound p-type doped layer adjacent the AlGaN layer, an aluminum nitride (A i N) layer disposed on the I II -V compound p-type doped layer, and a I II -V compound n-type doped layer disposed on the A l N layer, and forming a second gate stack disposed on the A l GaN layer and isolated from the first gate stack, the second gate stack having a metal layer on an A l N layer.
The method of claim 11, wherein the step of forming the first gate stack further comprises forming a metal layer disposed on the I II -V compound n-type doped layer.
The method of claim 11, wherein step of forming the second gate stack further comprises forming a III -V compound p-type doped layer adjacent the AlGaN layer, the A I N layer of the second gate stack disposed on the I II -V compound p-type doped layer of the second gate stack.
The method of claim 11, further comprising forming a dielectric layer on the I II -V compound n-type doped layer, and forming a metal layer on the I II-V compound n-type doped layer.
A method of forming a semiconductor structure comprising the steps of: forming an aluminum gallium nitride layer (AlGaN) on a GaN layer; and forming a first gate stack on the A l GaN layer, the first gate stack including: a III-V compound p-type doped layer on the AlGaN layer, SVG 14724876.04-13-2016.IMZ₅T₁ARPXXIFW3.CLM.4.11.612.1187.2160.1238.svg 0.17 5.16 Chemistry Black and white layer; and a III=V compound-n-type doped layer disposed above the-AlGaN-layer, and a metal layer disposed on the I₄₁-ompoundn-type doped= Al N layer; and forming a second gate stack disposed on the AlGaN layer and isolated from the first gate stack, the second gate stack being different from the first gate stack includinga metal4ayer adjacent4he AGan-layer:
The method of claim 16, wherein the-step of forming the first further comprising forning a third gate stack -ec o mprises comprising: forming a I II -V compound p-type doped layer adjacent the AlGaN layer, 5 DM2\6613959 1 DOCKET NO.: P₂₀₁₂₀₇₉₃US 01 (N₁₀₈₅-01488) App l. No. 144/724,876 Reply to Office action of forming an aluminum nitride (A I N) layer on the III -V compound p-type doped layer, wherein the forming a I II -V compound n-type doped layer of the first gate stack is formed o n the A I N layer of the first third gate stack: and formin g a metal layer on the III-V compound n-type doped layer of the third g ate stack.
The method of claim 16, further comprising forming a third gate stack on the AlGaN layer and isolated from the first and second gate stacks, the third gate stack including a dielectric layer above the A l GaN layer and a metal layer above
The method of claim 16, wherein the second AlGan layer. 6 DM2\6613959.1 the dielectric layer. gate stack includes a metal layer adjacent the
. canceled
The method of claim- ? 16, wherein- further comprising the step of forming SVG 14724876.04-13-2016.IMZ₅T₁ARPXXIFW3.CLM.4.20.658.2235.877.2282.svg 0.157 0.73 Chemistry Black and white gate stack eompr-ises- comprising forming a I II -V compound p- type doped layer adjacent the AlGaN layer, and forming the- an A l N layer is dispo s ed- on the I II -V compound p-type doped layer of the third gate stack.
Layer stacks claimed or described, ordered top of device to substrate.
first gate stack on AlGaN/GaN HEMT structure
Materials described outside the worked examples.
aluminum gallium nitride
AlGaN
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 12, in embodiments having layers of electrical conductors or semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be used …
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US 9,502,524Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 2 -9 are sectional views of semiconductor structures according to various embodiments. 1 DM₂ \ 5657496 1 Attorney Docket: P₂₀₁₂₀₇₉₃US01/N1085.01488
Figures 10 through 12 are sectional views of a compound semiconductor structure having a high threshold voltage E-mode HEMT, a low threshold voltage E- mode H E MT, and a D-mode H E MT.
Figures 13 through 15 are sectional views of a compound semiconductor 5 structure having a high threshold voltage E -mode MISFET, a low threshold voltage E- mode MISFET, and a D-mode MISFET. Detailed Description [0008] It is understood that the following disclosure provides many different …
Figures 1 a through l d and the embodiments illustrated in
Figure 3, unprotected or unmasked parts of the semiconductor structure 100 are etched down to the A lXGaI N 115 layer to form access regions 135 and one or more gate stacks 120a-c. The photoresist can also be appropriately stripped. Suitable etching techniques include sputter etching, reactive gas …
Figure 4, a first layer of silicon nitride 136 is deposited onto the semiconductor structure 100. Exemplary silicon nitrides (SiN) include amorphous SiN, t r isilicon tetranitride, disilicon mononitride, and silicon mononitride. The first silicon nitride layer 136 can be deposited using a low …
Figure 5, ohmic contacts 150 are fabricated for the semiconductor structure 100 by defining one or more ohmic regions in the first silicon nitride layer 136 and depositing a suitable ohmic material in the defined ohmic regions. In one embodiment, to form an appropriate ohmic region, the first silicon …
Figure 6, a second layer of silicon nitride 138 is deposited over the ohmic contacts 150, gate structures 120a-c, and exposed portions of the first silicon nitride layer 136. In one embodiment, the second layer of silicon nitride 138 is 10 deposited using a suitable vapor deposition processes (e.g., …
Figure 7, an exemplary gate stack 120a for a high threshold voltage E -mode device is formed by selectively etching photoresist material 5 139, the second silicon nitride layer 138, and sacrificial or dummy layer 127 of dielectric material. Suitable etching techniques include exposing the …
Figure 8, an exemplary gate stack 120b for a low threshold voltage E -mode device is formed by selectively etching photoresist material 139, the second silicon nitride layer 138, sacrificial or dummy layer 127 of dielectric material, and n-GaN layer 126 using a suitable etching technique and second …
Figure 9, an exemplary gate stack 120 c for a D-mode device is formed by selectively etching photoresist material 139, the second silicon nitride layer 138, sacrificial or dummy layer 127 of dielectric material, n-GaN layer 126, Al N layer 124, and p-GaN layer 122 using a suitable etching technique …
Figure 11, a layer of suitable gate metal 162 is deposited onto the exposed surfaces of the structure 15 100 using sputter deposition, evaporation or chemical vapor deposition processes, and a layer of photoresist material 139 formed over portions of the gate metal layer 162. In a non-limiting …
Figure 12, in embodiments having layers of electrical conductors or semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be used …
Figure 14, a layer of suitable gate metal 162 is deposited onto the exposed surfaces of the structure 100 using sputter deposition, evaporation, or chemical vapor deposition processes, and a layer of photoresist material 139 formed over 15 portions of the gate metal layer 162. In a non-limiting …
Figure 15, in embodiments having layers of electrical conductors or 20 semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a semiconductor structure comprising the steps of: forming an aluminum gallium nitride layer (A l GaN) on a GaN layer; and forming a first gate stack on the AlGaN layer, the first gate stack including: a I II -V compound p-type doped layer adjacent the AlGaN layer, an aluminum nitride (AIN) layer disposed on the I II -V compound p-type doped layer, a I II -V compound n-type doped layer disposed on the A I N layer, a metal layer disposed on the I II -V compound n-type doped layer; and forming a second gate stack disposed on the A l GaN layer, the second gate stack being different from the first gate stack.
The method of claim 1, wherein the second gate stack comprises a metal layer.
The method of Claim 1, further comprising the step of forming a dielectric layer underlying the metal layer of the first gate stack.
The method of Claim 1, wherein the III -V compound p-type doped layer is a p-doped GaN layer and the I II -V compound n-type doped layer is a n-doped GaN layer.
The method of Claim 1, wherein the I II -V compound p-type doped layer is doped with an impurity selected from the group consisting of magnesium, calcium, zin c, beryllium, carbon, and combinations thereof.
The method of Claim 1, wherein the I II -V compound n-type doped layer is doped with an impurity selected from the group consisting of silicon and oxygen. 3 DM2\6613959.1 DOCKET NO.: P₂₀₁₂₀₇₉₃US01 (N₁₀₈₅-01488) App l. No. 144/724,876 Reply to Office action of
A method of fo rm ing a semiconductor structure comprising the steps of: providing a substrate having an aluminum gallium nitride layer (A l GaN) on a GaN layer; and forming a first gate stack on the AlGaN layer, the first gate stack including: a III -V compound p-type doped layer adjacent the AlGaN layer, an aluminum nitride (A i N) layer disposed on the I II -V compound p-type doped layer, and a I II -V compound n-type doped layer disposed on the A l N layer, and forming a second gate stack disposed on the A l GaN layer and isolated from the first gate stack, the second gate stack having a metal layer on an A l N layer.
The method of claim 11, wherein the step of forming the first gate stack further comprises forming a metal layer disposed on the I II -V compound n-type doped layer.
The method of claim 11, wherein step of forming the second gate stack further comprises forming a III -V compound p-type doped layer adjacent the AlGaN layer, the A I N layer of the second gate stack disposed on the I II -V compound p-type doped layer of the second gate stack.
The method of claim 11, further comprising forming a dielectric layer on the I II -V compound n-type doped layer, and forming a metal layer on the I II-V compound n-type doped layer.
A method of forming a semiconductor structure comprising the steps of: forming an aluminum gallium nitride layer (AlGaN) on a GaN layer; and forming a first gate stack on the A l GaN layer, the first gate stack including: a III-V compound p-type doped layer on the AlGaN layer, SVG 14724876.04-13-2016.IMZ₅T₁ARPXXIFW3.CLM.4.11.612.1187.2160.1238.svg 0.17 5.16 Chemistry Black and white layer; and a III=V compound-n-type doped layer disposed above the-AlGaN-layer, and a metal layer disposed on the I₄₁-ompoundn-type doped= Al N layer; and forming a second gate stack disposed on the AlGaN layer and isolated from the first gate stack, the second gate stack being different from the first gate stack includinga metal4ayer adjacent4he AGan-layer:
The method of claim 16, wherein the-step of forming the first further comprising forning a third gate stack -ec o mprises comprising: forming a I II -V compound p-type doped layer adjacent the AlGaN layer, 5 DM2\6613959 1 DOCKET NO.: P₂₀₁₂₀₇₉₃US 01 (N₁₀₈₅-01488) App l. No. 144/724,876 Reply to Office action of forming an aluminum nitride (A I N) layer on the III -V compound p-type doped layer, wherein the forming a I II -V compound n-type doped layer of the first gate stack is formed o n the A I N layer of the first third gate stack: and formin g a metal layer on the III-V compound n-type doped layer of the third g ate stack.
The method of claim 16, further comprising forming a third gate stack on the AlGaN layer and isolated from the first and second gate stacks, the third gate stack including a dielectric layer above the A l GaN layer and a metal layer above
The method of claim 16, wherein the second AlGan layer. 6 DM2\6613959.1 the dielectric layer. gate stack includes a metal layer adjacent the
. canceled
The method of claim- ? 16, wherein- further comprising the step of forming SVG 14724876.04-13-2016.IMZ₅T₁ARPXXIFW3.CLM.4.20.658.2235.877.2282.svg 0.157 0.73 Chemistry Black and white gate stack eompr-ises- comprising forming a I II -V compound p- type doped layer adjacent the AlGaN layer, and forming the- an A l N layer is dispo s ed- on the I II -V compound p-type doped layer of the third gate stack.
Layer stacks claimed or described, ordered top of device to substrate.
first gate stack on AlGaN/GaN HEMT structure
Materials described outside the worked examples.
aluminum gallium nitride
AlGaN
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 12, in embodiments having layers of electrical conductors or semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be used …
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second gate stack on AlGaN/GaN HEMT structure
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III-V compound p-type doped layer
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Figure 15, in embodiments having layers of electrical conductors or 20 semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be …
second gate stack on AlGaN/GaN HEMT structure
third gate stack on AlGaN/GaN HEMT structure
III-V compound p-type doped layer
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p-doped GaN
GaN:p
n-doped GaN
GaN:n
aluminum nitride
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silicon dioxide
SiO₂
silicon nitride
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aluminum oxide
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tantalum oxide
Ta₂O₅
titanium oxide
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zinc oxide
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hafnium oxide
HfO₂
Figure 15, in embodiments having layers of electrical conductors or 20 semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be …
second gate stack on AlGaN/GaN HEMT structure
third gate stack on AlGaN/GaN HEMT structure
III-V compound p-type doped layer
III-V compound n-type doped layer
metal layer
dielectric layer
p-doped GaN
GaN:p
n-doped GaN
GaN:n
aluminum nitride
AlN
buffer layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
tantalum oxide
Ta₂O₅
titanium oxide
TiO₂
zinc oxide
ZnO₂
hafnium oxide
HfO₂
Figure 15, in embodiments having layers of electrical conductors or 20 semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be …
second gate stack on AlGaN/GaN HEMT structure
third gate stack on AlGaN/GaN HEMT structure
III-V compound p-type doped layer
III-V compound n-type doped layer
metal layer
dielectric layer
p-doped GaN
GaN:p
n-doped GaN
GaN:n
aluminum nitride
AlN
buffer layer
silicon dioxide
SiO₂
silicon nitride
Si₃N₄
aluminum oxide
Al₂O₃
tantalum oxide
Ta₂O₅
titanium oxide
TiO₂
zinc oxide
ZnO₂
hafnium oxide
HfO₂
Figure 15, in embodiments having layers of electrical conductors or 20 semiconductors, a layer of electrically insulating material 164 can be deposited on the semiconductor structure 100. In one embodiment, the layer 164 is a dielectric material. Any suitable interlayer dielectric material can be …