A method of forming a semiconductor field-effect transistor, the method comprising: forming a multilayer stack on the substrate, wherein the multilayer stack comprises a group III nitride epilayer, a back barrier layer, and a spacer layer; 5 forming a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; forming a dielectric, discontinuous thin film layer comprising SiO 2 on portions of the ultrathin barrier layer while leaving other portions exposed; forming a plurality of source electrodes and drain electrodes on the exposed areas of the 10 ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; and forming gate electrodes on the dielectric, discontinuous thin film layer.

The method of claim 5, wherein the source electrodes and the drain electrodes have an interlaced source-gate drain electrode structure. 22 Attorney Docket No.: USC-410-DIV (1093)

A method of forming a semiconductor field-effect transistor, the method comprising: forming a multilayer stack on the substrate, wherein the multilayer stack comprises a group III nitride epilayer, a back barrier layer, and a spacer layer; 5 forming a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; forming a dielectric, discontinuous thin film layer comprising SiO 2 on portions of the ultrathin barrier layer while leaving other portions exposed; forming a plurality of source electrodes and drain electrodes on the exposed areas of the 10 ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; and forming gate electrodes on the dielectric, discontinuous thin film layer.

The method of claim 5, wherein the source electrodes and the drain electrodes have an interlaced source-gate drain electrode structure. 22 Attorney Docket No.: USC-410-DIV (1093)

A method of forming a semiconductor field-effect transistor, the method comprising: forming a multilayer stack on the substrate, wherein the multilayer stack comprises a group III nitride epilayer, a back barrier layer, and a spacer layer; 5 forming a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; forming a dielectric, discontinuous thin film layer comprising SiO 2 on portions of the ultrathin barrier layer while leaving other portions exposed; forming a plurality of source electrodes and drain electrodes on the exposed areas of the 10 ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; and forming gate electrodes on the dielectric, discontinuous thin film layer.

The method of claim 5, wherein the source electrodes and the drain electrodes have an interlaced source-gate drain electrode structure. 22 Attorney Docket No.: USC-410-DIV (1093)

A method of forming a semiconductor field-effect transistor, the method comprising: forming a multilayer stack on the substrate, wherein the multilayer stack comprises a group III nitride epilayer, a back barrier layer, and a spacer layer; 5 forming a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; forming a dielectric, discontinuous thin film layer comprising SiO 2 on portions of the ultrathin barrier layer while leaving other portions exposed; forming a plurality of source electrodes and drain electrodes on the exposed areas of the 10 ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; and forming gate electrodes on the dielectric, discontinuous thin film layer.

The method of claim 5, wherein the source electrodes and the drain electrodes have an interlaced source-gate drain electrode structure. 22 Attorney Docket No.: USC-410-DIV (1093)