Patent
US 10,497,785GALLIUM NITRIDE VOLTAGE REGULATOR
Sansaptak Dasgupta
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,497,785Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic block diagram of a gallium nitride based voltage regulator in accordance with embodiments of the present disclosure. [4]
FIG. 2 is a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 3 is an isometric view of a schematic block diagram a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 4A-4E are schematic block diagrams for forming a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 5 a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 6 a schematic block diagram of a gallium nitride based n-type MOS transistor with a plurality of p-type MOS transistors in accordance with embodiments of …
FIG. 7 illustrates an interposer that includes one or more embodiments of the invention. [10]
FIG. 8 illustrates a computing device in accordance with one embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride transistor comprising: a substrate; a first dielectric material and a second dielectric material on the substrate, each of the first and second dielectric materials including oxygen; a first gallium nitride layer on the substrate and on the first and second dielectric material; a polarization layer on the first gallium nitride layer; a second gallium nitride layer on the first dielectric material and adjacent a first sidewall of the polarization layer; a first doped gallium nitride layer on the second gallium nitride layer; a third gallium nitride layer on the second dielectric material nd adjacent a second sidewall of the polarization layer; and a second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The gallium nitride transistor of claim 1, wherein the first gallium nitride layer is in the C+ crystalline direction. Currently amended
The gallium nitride transistor of claim 1, wherein the polarization layer comprises one of aluminum nitride (AIN), aluminum gallium nitride (AIGaN), or aluminum indium nitride (AlIn N). Original
he gallium nitride transistor of claim 1, wherein the gallium nitride transistor comprises: an n-type metal oxide semiconductor (NMOS) transistor comprising at least the first gallium nitride layer on the substrate and the first dielectric material, the polarization layer on the first gallium nitride layer [[,]]; a first p-type MOS (PMOS) transistor comprising at least the second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer and the first doped gallium nitride layer on the second gallium nitride layer form; and a second p-type MOS (PMOS) transistor comprising at least the third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer and the second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The gallium nitride transistor of claim 1, further comprising a two dimensional electron gas at an interface between the first gallium nitride layer and the polarization layer. Currently amended
The gallium nitride transistor of claim 1, wherein the second gallium nitride layer comprises an undoped gallium nitride layer having a thickness between 30 and [[to]] 50 nanometers. Currently amended
The gallium nitride transistor of claim 1, wherein the substrate comprises silicon 111, silicon 100, or silicon 110. Currently amended
The gallium nitride transistor of claim 1, further comprising a gate electrode on the polarization layer. Original
The gallium nitride transistor of claim 1, further comprising: a first gate electrode on the first doped gallium nitride layer on the second gallium nitride layer; and a second gate electrode on the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
A method for forming a gallium nitride complementary metal-oxide- semiconductor device, the method comprising: forming a first oxide island and a second oxide island on a substrate, the first and second oxide islands separated by a trench; forming a first gallium nitride layer in the trench and on a portion of the first and second oxide islands; forming a polarization layer on a top side of the first gallium nitride layer and on a first and second side wall of the first gallium nitride layer; forming a second gallium nitride layer on the first oxide island and on a first sidewall of the polarization layer; forming a doped gallium nitride layer on the second gallium nitride layer. Currently amended
The method of claim 11, further comprising: forming a third gallium nitride layer on the second oxide island and on a second sidewall of the polarization layer; and forming a doped gallium nitride layer on the third gallium nitride layer. Original
The method of claim 11, wherein forming the first gallium nitride layer comprises epitaxially growing the first gallium nitride layer from a seed layer in the trench. Original
The method of claim 11, wherein forming the first gallium nitride layer comprises forming the first gallium nitride layer in a direction substantially parallel to a C crystalline axis. Previously presented
The method of claim 11, wherein forming the polarization layer comprises forming the polarization layer on a top side of the first gallium nitride layer and one a first or second sidewall of the first gallium nitride layer. Original
The method of claim 11, wherein forming the polarization layer comprises forming one of an aluminum nitride (AIN) layer, an aluminum gallium nitride (AIGaN) layer, or an aluminum indium nitride (A II nN) layer on the first gallium nitride layer. Previously presented
The method of claim 11, wherein forming the first and second oxide isl and comprises: forming an oxide layer on the substrate; etching a trench in the oxide layer to expose the substrate, the trench isolating a portion of the oxide layer. Currently amended
The method of claim 11, wherein the doped-gallium nitride layer on the second gallium nitride layer comprises a magnesium dopant. Currently amended
The method of claim 11, wherein forming the second gallium nitride layer comprises growing an undoped gallium nitride layer with a thickness between 30 and [[to]] 50 nanometers. Currently amended
The method of claim 11, wherein the two dimensional electron gas is substantially parallel to a c-plane of the first gallium nitride layer. Original
A computing device, comprising: SVG 16079337.08-05-2019.JYYMFND₈RXEAPX4.CLM.1.svg 0.15 2.67 Black and white a voltage regulator circuit, the voltage regulator circuit comprising t a gallium nitride transistor, the gallium nitride transistor comprising: a substrate s [[;]] a first dielectric material and a second dielectric material on the substrate, each of the first and second dielectric materials including ox y gen [[;]] a first gallium nitride layer on the substrate and the first dielectric material and on the second dielectric material s [[;]] a polarization layer on the first gallium nitride layer s [[;]] a second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer s [[;]] a first doped gallium nitride layer on the second gallium nitride layer; a third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer s [[;]] and a second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The computing device of claim 21, wherein the first gallium nitride layer is in the C+ crystalline direction. Currently amended
The computing device of claim 21, wherein the gallium nitride transistor comprises: an n-type metal oxide semiconductor (NMOS) transistor comprising at least the first gallium nitride layer on the substrate and the first and second dielectric material, the polarization layer on the first gallium nitride layer; a first p-type MOS (PMOS) transistor comprising at least the second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer and the first doped gallium nitride layer on the second gallium nitride layer form; and a second p-type MOS (PMOS) transistor comprising at least the third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer and the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
The computing device of claim 21, further comprising a gate electrode on the polarization layer. Original
The computing device of claim 21, further comprising: a first gate electrode on the first doped gallium nitride layer on the second gallium nitride layer; and a second gate electrode on the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor
GaN first PMOS transistor
Materials described outside the worked examples.
oxide dielectric (STI)
first gallium nitride layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
undoped GaN PMOS channel layer thickness | 30–50 nm | GaN |
2DEG extent from GaN/polarization-layer interface | 1–3 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,497,785Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic block diagram of a gallium nitride based voltage regulator in accordance with embodiments of the present disclosure. [4]
FIG. 2 is a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 3 is an isometric view of a schematic block diagram a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 4A-4E are schematic block diagrams for forming a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 5 a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 6 a schematic block diagram of a gallium nitride based n-type MOS transistor with a plurality of p-type MOS transistors in accordance with embodiments of …
FIG. 7 illustrates an interposer that includes one or more embodiments of the invention. [10]
FIG. 8 illustrates a computing device in accordance with one embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride transistor comprising: a substrate; a first dielectric material and a second dielectric material on the substrate, each of the first and second dielectric materials including oxygen; a first gallium nitride layer on the substrate and on the first and second dielectric material; a polarization layer on the first gallium nitride layer; a second gallium nitride layer on the first dielectric material and adjacent a first sidewall of the polarization layer; a first doped gallium nitride layer on the second gallium nitride layer; a third gallium nitride layer on the second dielectric material nd adjacent a second sidewall of the polarization layer; and a second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The gallium nitride transistor of claim 1, wherein the first gallium nitride layer is in the C+ crystalline direction. Currently amended
The gallium nitride transistor of claim 1, wherein the polarization layer comprises one of aluminum nitride (AIN), aluminum gallium nitride (AIGaN), or aluminum indium nitride (AlIn N). Original
he gallium nitride transistor of claim 1, wherein the gallium nitride transistor comprises: an n-type metal oxide semiconductor (NMOS) transistor comprising at least the first gallium nitride layer on the substrate and the first dielectric material, the polarization layer on the first gallium nitride layer [[,]]; a first p-type MOS (PMOS) transistor comprising at least the second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer and the first doped gallium nitride layer on the second gallium nitride layer form; and a second p-type MOS (PMOS) transistor comprising at least the third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer and the second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The gallium nitride transistor of claim 1, further comprising a two dimensional electron gas at an interface between the first gallium nitride layer and the polarization layer. Currently amended
The gallium nitride transistor of claim 1, wherein the second gallium nitride layer comprises an undoped gallium nitride layer having a thickness between 30 and [[to]] 50 nanometers. Currently amended
The gallium nitride transistor of claim 1, wherein the substrate comprises silicon 111, silicon 100, or silicon 110. Currently amended
The gallium nitride transistor of claim 1, further comprising a gate electrode on the polarization layer. Original
The gallium nitride transistor of claim 1, further comprising: a first gate electrode on the first doped gallium nitride layer on the second gallium nitride layer; and a second gate electrode on the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
A method for forming a gallium nitride complementary metal-oxide- semiconductor device, the method comprising: forming a first oxide island and a second oxide island on a substrate, the first and second oxide islands separated by a trench; forming a first gallium nitride layer in the trench and on a portion of the first and second oxide islands; forming a polarization layer on a top side of the first gallium nitride layer and on a first and second side wall of the first gallium nitride layer; forming a second gallium nitride layer on the first oxide island and on a first sidewall of the polarization layer; forming a doped gallium nitride layer on the second gallium nitride layer. Currently amended
The method of claim 11, further comprising: forming a third gallium nitride layer on the second oxide island and on a second sidewall of the polarization layer; and forming a doped gallium nitride layer on the third gallium nitride layer. Original
The method of claim 11, wherein forming the first gallium nitride layer comprises epitaxially growing the first gallium nitride layer from a seed layer in the trench. Original
The method of claim 11, wherein forming the first gallium nitride layer comprises forming the first gallium nitride layer in a direction substantially parallel to a C crystalline axis. Previously presented
The method of claim 11, wherein forming the polarization layer comprises forming the polarization layer on a top side of the first gallium nitride layer and one a first or second sidewall of the first gallium nitride layer. Original
The method of claim 11, wherein forming the polarization layer comprises forming one of an aluminum nitride (AIN) layer, an aluminum gallium nitride (AIGaN) layer, or an aluminum indium nitride (A II nN) layer on the first gallium nitride layer. Previously presented
The method of claim 11, wherein forming the first and second oxide isl and comprises: forming an oxide layer on the substrate; etching a trench in the oxide layer to expose the substrate, the trench isolating a portion of the oxide layer. Currently amended
The method of claim 11, wherein the doped-gallium nitride layer on the second gallium nitride layer comprises a magnesium dopant. Currently amended
The method of claim 11, wherein forming the second gallium nitride layer comprises growing an undoped gallium nitride layer with a thickness between 30 and [[to]] 50 nanometers. Currently amended
The method of claim 11, wherein the two dimensional electron gas is substantially parallel to a c-plane of the first gallium nitride layer. Original
A computing device, comprising: SVG 16079337.08-05-2019.JYYMFND₈RXEAPX4.CLM.1.svg 0.15 2.67 Black and white a voltage regulator circuit, the voltage regulator circuit comprising t a gallium nitride transistor, the gallium nitride transistor comprising: a substrate s [[;]] a first dielectric material and a second dielectric material on the substrate, each of the first and second dielectric materials including ox y gen [[;]] a first gallium nitride layer on the substrate and the first dielectric material and on the second dielectric material s [[;]] a polarization layer on the first gallium nitride layer s [[;]] a second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer s [[;]] a first doped gallium nitride layer on the second gallium nitride layer; a third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer s [[;]] and a second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The computing device of claim 21, wherein the first gallium nitride layer is in the C+ crystalline direction. Currently amended
The computing device of claim 21, wherein the gallium nitride transistor comprises: an n-type metal oxide semiconductor (NMOS) transistor comprising at least the first gallium nitride layer on the substrate and the first and second dielectric material, the polarization layer on the first gallium nitride layer; a first p-type MOS (PMOS) transistor comprising at least the second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer and the first doped gallium nitride layer on the second gallium nitride layer form; and a second p-type MOS (PMOS) transistor comprising at least the third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer and the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
The computing device of claim 21, further comprising a gate electrode on the polarization layer. Original
The computing device of claim 21, further comprising: a first gate electrode on the first doped gallium nitride layer on the second gallium nitride layer; and a second gate electrode on the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor
GaN first PMOS transistor
Materials described outside the worked examples.
oxide dielectric (STI)
first gallium nitride layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
undoped GaN PMOS channel layer thickness | 30–50 nm | GaN |
2DEG extent from GaN/polarization-layer interface | 1–3 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,497,785Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic block diagram of a gallium nitride based voltage regulator in accordance with embodiments of the present disclosure. [4]
FIG. 2 is a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 3 is an isometric view of a schematic block diagram a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 4A-4E are schematic block diagrams for forming a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 5 a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 6 a schematic block diagram of a gallium nitride based n-type MOS transistor with a plurality of p-type MOS transistors in accordance with embodiments of …
FIG. 7 illustrates an interposer that includes one or more embodiments of the invention. [10]
FIG. 8 illustrates a computing device in accordance with one embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride transistor comprising: a substrate; a first dielectric material and a second dielectric material on the substrate, each of the first and second dielectric materials including oxygen; a first gallium nitride layer on the substrate and on the first and second dielectric material; a polarization layer on the first gallium nitride layer; a second gallium nitride layer on the first dielectric material and adjacent a first sidewall of the polarization layer; a first doped gallium nitride layer on the second gallium nitride layer; a third gallium nitride layer on the second dielectric material nd adjacent a second sidewall of the polarization layer; and a second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The gallium nitride transistor of claim 1, wherein the first gallium nitride layer is in the C+ crystalline direction. Currently amended
The gallium nitride transistor of claim 1, wherein the polarization layer comprises one of aluminum nitride (AIN), aluminum gallium nitride (AIGaN), or aluminum indium nitride (AlIn N). Original
he gallium nitride transistor of claim 1, wherein the gallium nitride transistor comprises: an n-type metal oxide semiconductor (NMOS) transistor comprising at least the first gallium nitride layer on the substrate and the first dielectric material, the polarization layer on the first gallium nitride layer [[,]]; a first p-type MOS (PMOS) transistor comprising at least the second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer and the first doped gallium nitride layer on the second gallium nitride layer form; and a second p-type MOS (PMOS) transistor comprising at least the third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer and the second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The gallium nitride transistor of claim 1, further comprising a two dimensional electron gas at an interface between the first gallium nitride layer and the polarization layer. Currently amended
The gallium nitride transistor of claim 1, wherein the second gallium nitride layer comprises an undoped gallium nitride layer having a thickness between 30 and [[to]] 50 nanometers. Currently amended
The gallium nitride transistor of claim 1, wherein the substrate comprises silicon 111, silicon 100, or silicon 110. Currently amended
The gallium nitride transistor of claim 1, further comprising a gate electrode on the polarization layer. Original
The gallium nitride transistor of claim 1, further comprising: a first gate electrode on the first doped gallium nitride layer on the second gallium nitride layer; and a second gate electrode on the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
A method for forming a gallium nitride complementary metal-oxide- semiconductor device, the method comprising: forming a first oxide island and a second oxide island on a substrate, the first and second oxide islands separated by a trench; forming a first gallium nitride layer in the trench and on a portion of the first and second oxide islands; forming a polarization layer on a top side of the first gallium nitride layer and on a first and second side wall of the first gallium nitride layer; forming a second gallium nitride layer on the first oxide island and on a first sidewall of the polarization layer; forming a doped gallium nitride layer on the second gallium nitride layer. Currently amended
The method of claim 11, further comprising: forming a third gallium nitride layer on the second oxide island and on a second sidewall of the polarization layer; and forming a doped gallium nitride layer on the third gallium nitride layer. Original
The method of claim 11, wherein forming the first gallium nitride layer comprises epitaxially growing the first gallium nitride layer from a seed layer in the trench. Original
The method of claim 11, wherein forming the first gallium nitride layer comprises forming the first gallium nitride layer in a direction substantially parallel to a C crystalline axis. Previously presented
The method of claim 11, wherein forming the polarization layer comprises forming the polarization layer on a top side of the first gallium nitride layer and one a first or second sidewall of the first gallium nitride layer. Original
The method of claim 11, wherein forming the polarization layer comprises forming one of an aluminum nitride (AIN) layer, an aluminum gallium nitride (AIGaN) layer, or an aluminum indium nitride (A II nN) layer on the first gallium nitride layer. Previously presented
The method of claim 11, wherein forming the first and second oxide isl and comprises: forming an oxide layer on the substrate; etching a trench in the oxide layer to expose the substrate, the trench isolating a portion of the oxide layer. Currently amended
The method of claim 11, wherein the doped-gallium nitride layer on the second gallium nitride layer comprises a magnesium dopant. Currently amended
The method of claim 11, wherein forming the second gallium nitride layer comprises growing an undoped gallium nitride layer with a thickness between 30 and [[to]] 50 nanometers. Currently amended
The method of claim 11, wherein the two dimensional electron gas is substantially parallel to a c-plane of the first gallium nitride layer. Original
A computing device, comprising: SVG 16079337.08-05-2019.JYYMFND₈RXEAPX4.CLM.1.svg 0.15 2.67 Black and white a voltage regulator circuit, the voltage regulator circuit comprising t a gallium nitride transistor, the gallium nitride transistor comprising: a substrate s [[;]] a first dielectric material and a second dielectric material on the substrate, each of the first and second dielectric materials including ox y gen [[;]] a first gallium nitride layer on the substrate and the first dielectric material and on the second dielectric material s [[;]] a polarization layer on the first gallium nitride layer s [[;]] a second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer s [[;]] a first doped gallium nitride layer on the second gallium nitride layer; a third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer s [[;]] and a second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The computing device of claim 21, wherein the first gallium nitride layer is in the C+ crystalline direction. Currently amended
The computing device of claim 21, wherein the gallium nitride transistor comprises: an n-type metal oxide semiconductor (NMOS) transistor comprising at least the first gallium nitride layer on the substrate and the first and second dielectric material, the polarization layer on the first gallium nitride layer; a first p-type MOS (PMOS) transistor comprising at least the second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer and the first doped gallium nitride layer on the second gallium nitride layer form; and a second p-type MOS (PMOS) transistor comprising at least the third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer and the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
The computing device of claim 21, further comprising a gate electrode on the polarization layer. Original
The computing device of claim 21, further comprising: a first gate electrode on the first doped gallium nitride layer on the second gallium nitride layer; and a second gate electrode on the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor
GaN first PMOS transistor
Materials described outside the worked examples.
oxide dielectric (STI)
first gallium nitride layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
undoped GaN PMOS channel layer thickness | 30–50 nm | GaN |
2DEG extent from GaN/polarization-layer interface | 1–3 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,497,785Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic block diagram of a gallium nitride based voltage regulator in accordance with embodiments of the present disclosure. [4]
FIG. 2 is a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 3 is an isometric view of a schematic block diagram a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 4A-4E are schematic block diagrams for forming a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 5 a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 6 a schematic block diagram of a gallium nitride based n-type MOS transistor with a plurality of p-type MOS transistors in accordance with embodiments of …
FIG. 7 illustrates an interposer that includes one or more embodiments of the invention. [10]
FIG. 8 illustrates a computing device in accordance with one embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride transistor comprising: a substrate; a first dielectric material and a second dielectric material on the substrate, each of the first and second dielectric materials including oxygen; a first gallium nitride layer on the substrate and on the first and second dielectric material; a polarization layer on the first gallium nitride layer; a second gallium nitride layer on the first dielectric material and adjacent a first sidewall of the polarization layer; a first doped gallium nitride layer on the second gallium nitride layer; a third gallium nitride layer on the second dielectric material nd adjacent a second sidewall of the polarization layer; and a second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The gallium nitride transistor of claim 1, wherein the first gallium nitride layer is in the C+ crystalline direction. Currently amended
The gallium nitride transistor of claim 1, wherein the polarization layer comprises one of aluminum nitride (AIN), aluminum gallium nitride (AIGaN), or aluminum indium nitride (AlIn N). Original
he gallium nitride transistor of claim 1, wherein the gallium nitride transistor comprises: an n-type metal oxide semiconductor (NMOS) transistor comprising at least the first gallium nitride layer on the substrate and the first dielectric material, the polarization layer on the first gallium nitride layer [[,]]; a first p-type MOS (PMOS) transistor comprising at least the second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer and the first doped gallium nitride layer on the second gallium nitride layer form; and a second p-type MOS (PMOS) transistor comprising at least the third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer and the second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The gallium nitride transistor of claim 1, further comprising a two dimensional electron gas at an interface between the first gallium nitride layer and the polarization layer. Currently amended
The gallium nitride transistor of claim 1, wherein the second gallium nitride layer comprises an undoped gallium nitride layer having a thickness between 30 and [[to]] 50 nanometers. Currently amended
The gallium nitride transistor of claim 1, wherein the substrate comprises silicon 111, silicon 100, or silicon 110. Currently amended
The gallium nitride transistor of claim 1, further comprising a gate electrode on the polarization layer. Original
The gallium nitride transistor of claim 1, further comprising: a first gate electrode on the first doped gallium nitride layer on the second gallium nitride layer; and a second gate electrode on the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
A method for forming a gallium nitride complementary metal-oxide- semiconductor device, the method comprising: forming a first oxide island and a second oxide island on a substrate, the first and second oxide islands separated by a trench; forming a first gallium nitride layer in the trench and on a portion of the first and second oxide islands; forming a polarization layer on a top side of the first gallium nitride layer and on a first and second side wall of the first gallium nitride layer; forming a second gallium nitride layer on the first oxide island and on a first sidewall of the polarization layer; forming a doped gallium nitride layer on the second gallium nitride layer. Currently amended
The method of claim 11, further comprising: forming a third gallium nitride layer on the second oxide island and on a second sidewall of the polarization layer; and forming a doped gallium nitride layer on the third gallium nitride layer. Original
The method of claim 11, wherein forming the first gallium nitride layer comprises epitaxially growing the first gallium nitride layer from a seed layer in the trench. Original
The method of claim 11, wherein forming the first gallium nitride layer comprises forming the first gallium nitride layer in a direction substantially parallel to a C crystalline axis. Previously presented
The method of claim 11, wherein forming the polarization layer comprises forming the polarization layer on a top side of the first gallium nitride layer and one a first or second sidewall of the first gallium nitride layer. Original
The method of claim 11, wherein forming the polarization layer comprises forming one of an aluminum nitride (AIN) layer, an aluminum gallium nitride (AIGaN) layer, or an aluminum indium nitride (A II nN) layer on the first gallium nitride layer. Previously presented
The method of claim 11, wherein forming the first and second oxide isl and comprises: forming an oxide layer on the substrate; etching a trench in the oxide layer to expose the substrate, the trench isolating a portion of the oxide layer. Currently amended
The method of claim 11, wherein the doped-gallium nitride layer on the second gallium nitride layer comprises a magnesium dopant. Currently amended
The method of claim 11, wherein forming the second gallium nitride layer comprises growing an undoped gallium nitride layer with a thickness between 30 and [[to]] 50 nanometers. Currently amended
The method of claim 11, wherein the two dimensional electron gas is substantially parallel to a c-plane of the first gallium nitride layer. Original
A computing device, comprising: SVG 16079337.08-05-2019.JYYMFND₈RXEAPX4.CLM.1.svg 0.15 2.67 Black and white a voltage regulator circuit, the voltage regulator circuit comprising t a gallium nitride transistor, the gallium nitride transistor comprising: a substrate s [[;]] a first dielectric material and a second dielectric material on the substrate, each of the first and second dielectric materials including ox y gen [[;]] a first gallium nitride layer on the substrate and the first dielectric material and on the second dielectric material s [[;]] a polarization layer on the first gallium nitride layer s [[;]] a second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer s [[;]] a first doped gallium nitride layer on the second gallium nitride layer; a third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer s [[;]] and a second doped-gallium nitride layer on the third gallium nitride layer. Currently amended
The computing device of claim 21, wherein the first gallium nitride layer is in the C+ crystalline direction. Currently amended
The computing device of claim 21, wherein the gallium nitride transistor comprises: an n-type metal oxide semiconductor (NMOS) transistor comprising at least the first gallium nitride layer on the substrate and the first and second dielectric material, the polarization layer on the first gallium nitride layer; a first p-type MOS (PMOS) transistor comprising at least the second gallium nitride layer on the first dielectric material n the substrate and adjacent a first sidewall of the polarization layer and the first doped gallium nitride layer on the second gallium nitride layer form; and a second p-type MOS (PMOS) transistor comprising at least the third gallium nitride layer on the second dielectric material on the substrate and adjacent a second sidewall of the polarization layer and the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
The computing device of claim 21, further comprising a gate electrode on the polarization layer. Original
The computing device of claim 21, further comprising: a first gate electrode on the first doped gallium nitride layer on the second gallium nitride layer; and a second gate electrode on the second doped gallium nitride layer on the third gallium nitride layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN NMOS transistor
GaN first PMOS transistor
Materials described outside the worked examples.
oxide dielectric (STI)
first gallium nitride layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 is a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
undoped GaN PMOS channel layer thickness | 30–50 nm | GaN |
2DEG extent from GaN/polarization-layer interface | 1–3 nm |
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FIG. 3 is an isometric view of a schematic block diagram a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 4A-4E are schematic block diagrams for forming a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 5 a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 6 a schematic block diagram of a gallium nitride based n-type MOS transistor with a plurality of p-type MOS transistors in accordance with embodiments of …
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
GaN second PMOS transistor
GaN CMOS voltage regulator in computing device
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aluminum gallium nitride
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aluminum indium nitride
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silicon substrate
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magnesium dopant
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aluminum oxide gate dielectric
Al₂O₃
hafnium oxide gate dielectric
HfO₂
FIG. 3 is an isometric view of a schematic block diagram a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 4A-4E are schematic block diagrams for forming a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 5 a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 6 a schematic block diagram of a gallium nitride based n-type MOS transistor with a plurality of p-type MOS transistors in accordance with embodiments of …
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
GaN second PMOS transistor
GaN CMOS voltage regulator in computing device
polarization layer
first doped gallium nitride layer (p-doped)
GaN:Mg
aluminum nitride
AlN
aluminum gallium nitride
AlGaN
aluminum indium nitride
AlInN
silicon substrate
Si
magnesium dopant
Mg
two dimensional electron gas
aluminum oxide gate dielectric
Al₂O₃
hafnium oxide gate dielectric
HfO₂
FIG. 3 is an isometric view of a schematic block diagram a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 4A-4E are schematic block diagrams for forming a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 5 a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 6 a schematic block diagram of a gallium nitride based n-type MOS transistor with a plurality of p-type MOS transistors in accordance with embodiments of …
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
GaN second PMOS transistor
GaN CMOS voltage regulator in computing device
polarization layer
first doped gallium nitride layer (p-doped)
GaN:Mg
aluminum nitride
AlN
aluminum gallium nitride
AlGaN
aluminum indium nitride
AlInN
silicon substrate
Si
magnesium dopant
Mg
two dimensional electron gas
aluminum oxide gate dielectric
Al₂O₃
hafnium oxide gate dielectric
HfO₂
FIG. 3 is an isometric view of a schematic block diagram a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 4A-4E are schematic block diagrams for forming a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with …
FIG. 5 a schematic block diagram of a gallium nitride based complementary metal oxide semiconductor (CMOS) transistor in accordance with embodiments of the …
FIG. 6 a schematic block diagram of a gallium nitride based n-type MOS transistor with a plurality of p-type MOS transistors in accordance with embodiments of …
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |