Patent
US 10,777,654METHOD FOR MANUFACTURING NITROGEN-FACE POLARITY GALLIUM NITRIDE EPITAXIAL STRUCTURE
Xianfeng NI
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A method for m anu factur ing a nitrogen-face polarity galli um nitride epitaxial st ruc ture, comprising: providing a galli um nitride t e mplate, wherein the galli um nitride template co m prises a substrate and a first nitrogen-face polarity gallium nitride la y er positioned on the substrate; loading the g alli mu nitride template in air to a vacuum chamber and re-g row ing g alli um nitride on a surface of the first n i tro g en-face polarity gallium nitride layer to fo rm a second nitrogen-face polarity galli um nitride layer; and sequentially gro w ing a barrier layer and a channel layer on the second nitrogen-face polarity gall iumn nitride layer to form a two-dimensional electron 2a s, wh erei n sequentially growing the barrier layer and the channel la v er dif fu ses n-ty pe unintentional dopi ng impurities from an interface bet w een the fi r st n itrogen-face polarity galli um nitride la yer and the second nitrogen-face polarit y galli um nitride layer to an inter face bet w een the second nitro z en-f a ce polarity u alli um nitride l ay er and the barr i er la y er. Currently amended
2. (O r iginal) The method for manufacturing the nitrogen- face polarity galli um nitride epitaxial struc tu re according to claim 1, wherein the first n itrogen-face pola r ity galli um nitride layer has a thickness of 1 ptm to 5 p in. Original
(O rigi n al) The method for m anufacturing the nitrogen-face polarity galli um nitride epitaxial structure according to claim 1, wherein the second nitrogen-face polarity galli um nitride layer ha s a thickness of 1 0 mu to 5 tm. Original
(O r iginal) The method for manufacturing the nitrogen- fa ce polarity gallium nitride epitaxial struct ur e according to claim 1, wherei n the channel layer ha s a thickness of 10 un to 100 nm. Original
6. (Curre n tly amended) T he method for ma nufac turing the ni troge n -face pola riny gallium nitride e p itaxial structure according to claim 1, fir ther com prisi n wash ing and blow dr ying the g alli um nitride te mp late, before loadi ng the gallium nitride template i n air to the vacuum cha mb er. Currently amended
S. (N ew) The method for man ufact urin g the itaxial st ruc ture according to claim 1, wherein comprise silicon i ons. Canceled
(N ew) The method for manuf actur ing the ni truc ture according to cla im 1, wherein the n-type oxygen ions. New nitro gen-fac e pol ar ity ga llimln nitride ep the n-t yp e un int enti o nal dop ing i mpur ities trogen-face p olarity g a llium nitride epitaxial s unin tentio n al doping impurities c omprise
Layer stacks claimed or described, ordered top of device to substrate.
nitrogen-face polarity GaN HEMT epitaxial structure with 2DEG
Materials described outside the worked examples.
first nitrogen-face polarity gallium nitride layer
GaN
barrier layer
channel layer
silicon ions (n-type unintentional doping impurities)
Si
oxygen ions (n-type unintentional doping impurities)
O
InGaN channel layer
InGaN
AlGaN barrier layer
AlGaN
InAlN barrier layer
InAlN
substrate
carbon-face polarity silicon carbide substrate
SiC
sapphire substrate
Al₂O₃
cap layer (AlGaN or AlN)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first nitrogen-face polarity GaN layer thickness | 1–5 µm | GaN |
second nitrogen-face polarity GaN layer thickness | 10–5000 nm | GaN |
channel layer thickness | 10–100 nm | channel layer |
barrier layer thickness | 10–100 nm | barrier layer |
substrate thickness | ≥ 10 µm | substrate |
Related documents with shared materials, methods, properties, or citations.
Stacked Multilayer 3D GaN High Electron Mobility Transistor Structure and Process Method
NORMALLY-OFF GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICES
GaN-Based High Electron Mobility Transistors and Fabrication Method Thereof
HIGH-QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON
SELF-ALIGNED SIDEWALL GATE GAN HEMT
GaN-BASED SUPERJUNCTION VERTICAL POWER TRANSISTOR AND MANUFACTURING METHOD THEREOF
METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE WITH DEVICE AREAS FOR DEFINITION OF GAN-BASED DEVICES AND CMOS DEVICES
INTEGRATION OF GALLIUM NITRIDE LEDS WITH ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE DEVICES ON SILICON SUBSTRATES FOR AC LEDS
METHOD FOR MANUFACTURING GALLIUM NITRIDE WAFER
GALLIUM NITRIDE VOLTAGE REGULATOR
VERTICAL SEMICONDUCTOR DEVICE HAVING A NON-CONDUCTIVE SUBSTRATE AND A GALLIUM NITRIDE LAYER
GALLIUM NITRIDE DEVICES HAVING LOW OHMIC CONTACT RESISTANCE
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A method for m anu factur ing a nitrogen-face polarity galli um nitride epitaxial st ruc ture, comprising: providing a galli um nitride t e mplate, wherein the galli um nitride template co m prises a substrate and a first nitrogen-face polarity gallium nitride la y er positioned on the substrate; loading the g alli mu nitride template in air to a vacuum chamber and re-g row ing g alli um nitride on a surface of the first n i tro g en-face polarity gallium nitride layer to fo rm a second nitrogen-face polarity galli um nitride layer; and sequentially gro w ing a barrier layer and a channel layer on the second nitrogen-face polarity gall iumn nitride layer to form a two-dimensional electron 2a s, wh erei n sequentially growing the barrier layer and the channel la v er dif fu ses n-ty pe unintentional dopi ng impurities from an interface bet w een the fi r st n itrogen-face polarity galli um nitride la yer and the second nitrogen-face polarit y galli um nitride layer to an inter face bet w een the second nitro z en-f a ce polarity u alli um nitride l ay er and the barr i er la y er. Currently amended
2. (O r iginal) The method for manufacturing the nitrogen- face polarity galli um nitride epitaxial struc tu re according to claim 1, wherein the first n itrogen-face pola r ity galli um nitride layer has a thickness of 1 ptm to 5 p in. Original
(O rigi n al) The method for m anufacturing the nitrogen-face polarity galli um nitride epitaxial structure according to claim 1, wherein the second nitrogen-face polarity galli um nitride layer ha s a thickness of 1 0 mu to 5 tm. Original
(O r iginal) The method for manufacturing the nitrogen- fa ce polarity gallium nitride epitaxial struct ur e according to claim 1, wherei n the channel layer ha s a thickness of 10 un to 100 nm. Original
6. (Curre n tly amended) T he method for ma nufac turing the ni troge n -face pola riny gallium nitride e p itaxial structure according to claim 1, fir ther com prisi n wash ing and blow dr ying the g alli um nitride te mp late, before loadi ng the gallium nitride template i n air to the vacuum cha mb er. Currently amended
S. (N ew) The method for man ufact urin g the itaxial st ruc ture according to claim 1, wherein comprise silicon i ons. Canceled
(N ew) The method for manuf actur ing the ni truc ture according to cla im 1, wherein the n-type oxygen ions. New nitro gen-fac e pol ar ity ga llimln nitride ep the n-t yp e un int enti o nal dop ing i mpur ities trogen-face p olarity g a llium nitride epitaxial s unin tentio n al doping impurities c omprise
Layer stacks claimed or described, ordered top of device to substrate.
nitrogen-face polarity GaN HEMT epitaxial structure with 2DEG
Materials described outside the worked examples.
first nitrogen-face polarity gallium nitride layer
GaN
barrier layer
channel layer
silicon ions (n-type unintentional doping impurities)
Si
oxygen ions (n-type unintentional doping impurities)
O
InGaN channel layer
InGaN
AlGaN barrier layer
AlGaN
InAlN barrier layer
InAlN
substrate
carbon-face polarity silicon carbide substrate
SiC
sapphire substrate
Al₂O₃
cap layer (AlGaN or AlN)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first nitrogen-face polarity GaN layer thickness | 1–5 µm | GaN |
second nitrogen-face polarity GaN layer thickness | 10–5000 nm | GaN |
channel layer thickness | 10–100 nm | channel layer |
barrier layer thickness | 10–100 nm | barrier layer |
substrate thickness | ≥ 10 µm | substrate |
Related documents with shared materials, methods, properties, or citations.
Stacked Multilayer 3D GaN High Electron Mobility Transistor Structure and Process Method
NORMALLY-OFF GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICES
GaN-Based High Electron Mobility Transistors and Fabrication Method Thereof
HIGH-QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON
SELF-ALIGNED SIDEWALL GATE GAN HEMT
GaN-BASED SUPERJUNCTION VERTICAL POWER TRANSISTOR AND MANUFACTURING METHOD THEREOF
METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE WITH DEVICE AREAS FOR DEFINITION OF GAN-BASED DEVICES AND CMOS DEVICES
INTEGRATION OF GALLIUM NITRIDE LEDS WITH ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE DEVICES ON SILICON SUBSTRATES FOR AC LEDS
METHOD FOR MANUFACTURING GALLIUM NITRIDE WAFER
GALLIUM NITRIDE VOLTAGE REGULATOR
VERTICAL SEMICONDUCTOR DEVICE HAVING A NON-CONDUCTIVE SUBSTRATE AND A GALLIUM NITRIDE LAYER
GALLIUM NITRIDE DEVICES HAVING LOW OHMIC CONTACT RESISTANCE
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A method for m anu factur ing a nitrogen-face polarity galli um nitride epitaxial st ruc ture, comprising: providing a galli um nitride t e mplate, wherein the galli um nitride template co m prises a substrate and a first nitrogen-face polarity gallium nitride la y er positioned on the substrate; loading the g alli mu nitride template in air to a vacuum chamber and re-g row ing g alli um nitride on a surface of the first n i tro g en-face polarity gallium nitride layer to fo rm a second nitrogen-face polarity galli um nitride layer; and sequentially gro w ing a barrier layer and a channel layer on the second nitrogen-face polarity gall iumn nitride layer to form a two-dimensional electron 2a s, wh erei n sequentially growing the barrier layer and the channel la v er dif fu ses n-ty pe unintentional dopi ng impurities from an interface bet w een the fi r st n itrogen-face polarity galli um nitride la yer and the second nitrogen-face polarit y galli um nitride layer to an inter face bet w een the second nitro z en-f a ce polarity u alli um nitride l ay er and the barr i er la y er. Currently amended
2. (O r iginal) The method for manufacturing the nitrogen- face polarity galli um nitride epitaxial struc tu re according to claim 1, wherein the first n itrogen-face pola r ity galli um nitride layer has a thickness of 1 ptm to 5 p in. Original
(O rigi n al) The method for m anufacturing the nitrogen-face polarity galli um nitride epitaxial structure according to claim 1, wherein the second nitrogen-face polarity galli um nitride layer ha s a thickness of 1 0 mu to 5 tm. Original
(O r iginal) The method for manufacturing the nitrogen- fa ce polarity gallium nitride epitaxial struct ur e according to claim 1, wherei n the channel layer ha s a thickness of 10 un to 100 nm. Original
6. (Curre n tly amended) T he method for ma nufac turing the ni troge n -face pola riny gallium nitride e p itaxial structure according to claim 1, fir ther com prisi n wash ing and blow dr ying the g alli um nitride te mp late, before loadi ng the gallium nitride template i n air to the vacuum cha mb er. Currently amended
S. (N ew) The method for man ufact urin g the itaxial st ruc ture according to claim 1, wherein comprise silicon i ons. Canceled
(N ew) The method for manuf actur ing the ni truc ture according to cla im 1, wherein the n-type oxygen ions. New nitro gen-fac e pol ar ity ga llimln nitride ep the n-t yp e un int enti o nal dop ing i mpur ities trogen-face p olarity g a llium nitride epitaxial s unin tentio n al doping impurities c omprise
Layer stacks claimed or described, ordered top of device to substrate.
nitrogen-face polarity GaN HEMT epitaxial structure with 2DEG
Materials described outside the worked examples.
first nitrogen-face polarity gallium nitride layer
GaN
barrier layer
channel layer
silicon ions (n-type unintentional doping impurities)
Si
oxygen ions (n-type unintentional doping impurities)
O
InGaN channel layer
InGaN
AlGaN barrier layer
AlGaN
InAlN barrier layer
InAlN
substrate
carbon-face polarity silicon carbide substrate
SiC
sapphire substrate
Al₂O₃
cap layer (AlGaN or AlN)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first nitrogen-face polarity GaN layer thickness | 1–5 µm | GaN |
second nitrogen-face polarity GaN layer thickness | 10–5000 nm | GaN |
channel layer thickness | 10–100 nm | channel layer |
barrier layer thickness | 10–100 nm | barrier layer |
substrate thickness | ≥ 10 µm | substrate |
Related documents with shared materials, methods, properties, or citations.
Stacked Multilayer 3D GaN High Electron Mobility Transistor Structure and Process Method
NORMALLY-OFF GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICES
GaN-Based High Electron Mobility Transistors and Fabrication Method Thereof
HIGH-QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON
SELF-ALIGNED SIDEWALL GATE GAN HEMT
GaN-BASED SUPERJUNCTION VERTICAL POWER TRANSISTOR AND MANUFACTURING METHOD THEREOF
METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE WITH DEVICE AREAS FOR DEFINITION OF GAN-BASED DEVICES AND CMOS DEVICES
INTEGRATION OF GALLIUM NITRIDE LEDS WITH ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE DEVICES ON SILICON SUBSTRATES FOR AC LEDS
METHOD FOR MANUFACTURING GALLIUM NITRIDE WAFER
GALLIUM NITRIDE VOLTAGE REGULATOR
VERTICAL SEMICONDUCTOR DEVICE HAVING A NON-CONDUCTIVE SUBSTRATE AND A GALLIUM NITRIDE LAYER
GALLIUM NITRIDE DEVICES HAVING LOW OHMIC CONTACT RESISTANCE
Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1. A method for m anu factur ing a nitrogen-face polarity galli um nitride epitaxial st ruc ture, comprising: providing a galli um nitride t e mplate, wherein the galli um nitride template co m prises a substrate and a first nitrogen-face polarity gallium nitride la y er positioned on the substrate; loading the g alli mu nitride template in air to a vacuum chamber and re-g row ing g alli um nitride on a surface of the first n i tro g en-face polarity gallium nitride layer to fo rm a second nitrogen-face polarity galli um nitride layer; and sequentially gro w ing a barrier layer and a channel layer on the second nitrogen-face polarity gall iumn nitride layer to form a two-dimensional electron 2a s, wh erei n sequentially growing the barrier layer and the channel la v er dif fu ses n-ty pe unintentional dopi ng impurities from an interface bet w een the fi r st n itrogen-face polarity galli um nitride la yer and the second nitrogen-face polarit y galli um nitride layer to an inter face bet w een the second nitro z en-f a ce polarity u alli um nitride l ay er and the barr i er la y er. Currently amended
2. (O r iginal) The method for manufacturing the nitrogen- face polarity galli um nitride epitaxial struc tu re according to claim 1, wherein the first n itrogen-face pola r ity galli um nitride layer has a thickness of 1 ptm to 5 p in. Original
(O rigi n al) The method for m anufacturing the nitrogen-face polarity galli um nitride epitaxial structure according to claim 1, wherein the second nitrogen-face polarity galli um nitride layer ha s a thickness of 1 0 mu to 5 tm. Original
(O r iginal) The method for manufacturing the nitrogen- fa ce polarity gallium nitride epitaxial struct ur e according to claim 1, wherei n the channel layer ha s a thickness of 10 un to 100 nm. Original
6. (Curre n tly amended) T he method for ma nufac turing the ni troge n -face pola riny gallium nitride e p itaxial structure according to claim 1, fir ther com prisi n wash ing and blow dr ying the g alli um nitride te mp late, before loadi ng the gallium nitride template i n air to the vacuum cha mb er. Currently amended
S. (N ew) The method for man ufact urin g the itaxial st ruc ture according to claim 1, wherein comprise silicon i ons. Canceled
(N ew) The method for manuf actur ing the ni truc ture according to cla im 1, wherein the n-type oxygen ions. New nitro gen-fac e pol ar ity ga llimln nitride ep the n-t yp e un int enti o nal dop ing i mpur ities trogen-face p olarity g a llium nitride epitaxial s unin tentio n al doping impurities c omprise
Layer stacks claimed or described, ordered top of device to substrate.
nitrogen-face polarity GaN HEMT epitaxial structure with 2DEG
Materials described outside the worked examples.
first nitrogen-face polarity gallium nitride layer
GaN
barrier layer
channel layer
silicon ions (n-type unintentional doping impurities)
Si
oxygen ions (n-type unintentional doping impurities)
O
InGaN channel layer
InGaN
AlGaN barrier layer
AlGaN
InAlN barrier layer
InAlN
substrate
carbon-face polarity silicon carbide substrate
SiC
sapphire substrate
Al₂O₃
cap layer (AlGaN or AlN)
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first nitrogen-face polarity GaN layer thickness | 1–5 µm | GaN |
second nitrogen-face polarity GaN layer thickness | 10–5000 nm | GaN |
channel layer thickness | 10–100 nm | channel layer |
barrier layer thickness | 10–100 nm | barrier layer |
substrate thickness | ≥ 10 µm | substrate |
Related documents with shared materials, methods, properties, or citations.
Stacked Multilayer 3D GaN High Electron Mobility Transistor Structure and Process Method
NORMALLY-OFF GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICES
GaN-Based High Electron Mobility Transistors and Fabrication Method Thereof
HIGH-QUALITY GAN HIGH-VOLTAGE HFETS ON SILICON
SELF-ALIGNED SIDEWALL GATE GAN HEMT
GaN-BASED SUPERJUNCTION VERTICAL POWER TRANSISTOR AND MANUFACTURING METHOD THEREOF
METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR SUBSTRATE STRUCTURE WITH DEVICE AREAS FOR DEFINITION OF GAN-BASED DEVICES AND CMOS DEVICES
INTEGRATION OF GALLIUM NITRIDE LEDS WITH ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE DEVICES ON SILICON SUBSTRATES FOR AC LEDS
METHOD FOR MANUFACTURING GALLIUM NITRIDE WAFER
GALLIUM NITRIDE VOLTAGE REGULATOR
VERTICAL SEMICONDUCTOR DEVICE HAVING A NON-CONDUCTIVE SUBSTRATE AND A GALLIUM NITRIDE LAYER
GALLIUM NITRIDE DEVICES HAVING LOW OHMIC CONTACT RESISTANCE