Patent
US 8,766,321SELF ALIGNED SIDEWALL GATE GaN HEMT
Keisuke Shinohara
US
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US 8,766,321Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 I. [0048] All layers were deposited by PECVD. The resulting structure had a dielectric spacer thickness of 29-34 nm and a silicon sacrificial gate …
FIG. 2 shows SEM images of a preliminary demonstration of the sidewall gate process using a sacrificial Si gate and SiO 2 dielectric spacers in accordance with …
FIG. 3C, a third dielectric film 28 such as SiO2, SiN, A 1203, polymers, etc., is deposited using a deposi t ion technique such as CVD, sputtering, ALD, spin …
FIG. 4 is a larger view of FIG. l Z, showing a transistor with a self aligned gate in accordance with the present disclosure.
FIG. 10 and in step 232 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
456789101112131415161718192021222324252627. Preliminary amendment 3 Amendments to the Claims Please amend the claims as follows. This listing of claims will replace all prior versions, and listings of claims in the application: 1 -27. Cancelled
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with self-aligned sidewall gate
Materials described outside the worked examples.
AlGaN (first epitaxial layer/buffer layer)
AlGaN
GaN (second epitaxial layer/channel)
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 I. [0048] All layers were deposited by PECVD. The resulting structure had a dielectric spacer thickness of 29-34 nm and a silicon sacrificial gate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Gate Length | ≤ 50 nm | — |
Thickness | 29–34 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,766,321Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 I. [0048] All layers were deposited by PECVD. The resulting structure had a dielectric spacer thickness of 29-34 nm and a silicon sacrificial gate …
FIG. 2 shows SEM images of a preliminary demonstration of the sidewall gate process using a sacrificial Si gate and SiO 2 dielectric spacers in accordance with …
FIG. 3C, a third dielectric film 28 such as SiO2, SiN, A 1203, polymers, etc., is deposited using a deposi t ion technique such as CVD, sputtering, ALD, spin …
FIG. 4 is a larger view of FIG. l Z, showing a transistor with a self aligned gate in accordance with the present disclosure.
FIG. 10 and in step 232 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
456789101112131415161718192021222324252627. Preliminary amendment 3 Amendments to the Claims Please amend the claims as follows. This listing of claims will replace all prior versions, and listings of claims in the application: 1 -27. Cancelled
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with self-aligned sidewall gate
Materials described outside the worked examples.
AlGaN (first epitaxial layer/buffer layer)
AlGaN
GaN (second epitaxial layer/channel)
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 I. [0048] All layers were deposited by PECVD. The resulting structure had a dielectric spacer thickness of 29-34 nm and a silicon sacrificial gate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Gate Length | ≤ 50 nm | — |
Thickness | 29–34 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,766,321Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 I. [0048] All layers were deposited by PECVD. The resulting structure had a dielectric spacer thickness of 29-34 nm and a silicon sacrificial gate …
FIG. 2 shows SEM images of a preliminary demonstration of the sidewall gate process using a sacrificial Si gate and SiO 2 dielectric spacers in accordance with …
FIG. 3C, a third dielectric film 28 such as SiO2, SiN, A 1203, polymers, etc., is deposited using a deposi t ion technique such as CVD, sputtering, ALD, spin …
FIG. 4 is a larger view of FIG. l Z, showing a transistor with a self aligned gate in accordance with the present disclosure.
FIG. 10 and in step 232 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
456789101112131415161718192021222324252627. Preliminary amendment 3 Amendments to the Claims Please amend the claims as follows. This listing of claims will replace all prior versions, and listings of claims in the application: 1 -27. Cancelled
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with self-aligned sidewall gate
Materials described outside the worked examples.
AlGaN (first epitaxial layer/buffer layer)
AlGaN
GaN (second epitaxial layer/channel)
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 I. [0048] All layers were deposited by PECVD. The resulting structure had a dielectric spacer thickness of 29-34 nm and a silicon sacrificial gate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Gate Length | ≤ 50 nm | — |
Thickness | 29–34 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,766,321Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 I. [0048] All layers were deposited by PECVD. The resulting structure had a dielectric spacer thickness of 29-34 nm and a silicon sacrificial gate …
FIG. 2 shows SEM images of a preliminary demonstration of the sidewall gate process using a sacrificial Si gate and SiO 2 dielectric spacers in accordance with …
FIG. 3C, a third dielectric film 28 such as SiO2, SiN, A 1203, polymers, etc., is deposited using a deposi t ion technique such as CVD, sputtering, ALD, spin …
FIG. 4 is a larger view of FIG. l Z, showing a transistor with a self aligned gate in accordance with the present disclosure.
FIG. 10 and in step 232 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
456789101112131415161718192021222324252627. Preliminary amendment 3 Amendments to the Claims Please amend the claims as follows. This listing of claims will replace all prior versions, and listings of claims in the application: 1 -27. Cancelled
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with self-aligned sidewall gate
Materials described outside the worked examples.
AlGaN (first epitaxial layer/buffer layer)
AlGaN
GaN (second epitaxial layer/channel)
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 I. [0048] All layers were deposited by PECVD. The resulting structure had a dielectric spacer thickness of 29-34 nm and a silicon sacrificial gate …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Gate Length | ≤ 50 nm | — |
Thickness | 29–34 nm |
Related documents with shared materials, methods, properties, or citations.
AlGaN or AlN (third epitaxial layer/top barrier)
sapphire substrate
SiC substrate
SiC
silicon substrate
Si
Al₂O₃ (high-k gate dielectric)
Al₂O₃
HfO₂ (high-k gate dielectric)
HfO₂
TiO₂ (high-k gate dielectric)
TiO₂
FIG. 2 shows SEM images of a preliminary demonstration of the sidewall gate process using a sacrificial Si gate and SiO 2 dielectric spacers in accordance with …
FIG. 4 is a larger view of FIG. l Z, showing a transistor with a self aligned gate in accordance with the present disclosure.
| — |
AlGaN or AlN (third epitaxial layer/top barrier)
sapphire substrate
SiC substrate
SiC
silicon substrate
Si
Al₂O₃ (high-k gate dielectric)
Al₂O₃
HfO₂ (high-k gate dielectric)
HfO₂
TiO₂ (high-k gate dielectric)
TiO₂
FIG. 2 shows SEM images of a preliminary demonstration of the sidewall gate process using a sacrificial Si gate and SiO 2 dielectric spacers in accordance with …
FIG. 4 is a larger view of FIG. l Z, showing a transistor with a self aligned gate in accordance with the present disclosure.
| — |
AlGaN or AlN (third epitaxial layer/top barrier)
sapphire substrate
SiC substrate
SiC
silicon substrate
Si
Al₂O₃ (high-k gate dielectric)
Al₂O₃
HfO₂ (high-k gate dielectric)
HfO₂
TiO₂ (high-k gate dielectric)
TiO₂
FIG. 2 shows SEM images of a preliminary demonstration of the sidewall gate process using a sacrificial Si gate and SiO 2 dielectric spacers in accordance with …
FIG. 4 is a larger view of FIG. l Z, showing a transistor with a self aligned gate in accordance with the present disclosure.
| — |
AlGaN or AlN (third epitaxial layer/top barrier)
sapphire substrate
SiC substrate
SiC
silicon substrate
Si
Al₂O₃ (high-k gate dielectric)
Al₂O₃
HfO₂ (high-k gate dielectric)
HfO₂
TiO₂ (high-k gate dielectric)
TiO₂
FIG. 2 shows SEM images of a preliminary demonstration of the sidewall gate process using a sacrificial Si gate and SiO 2 dielectric spacers in accordance with …
FIG. 4 is a larger view of FIG. l Z, showing a transistor with a self aligned gate in accordance with the present disclosure.
| — |