Patent
US 12,268,018 B2GaN VERTICAL TRENCH MOSFETs AND METHODS OF MANUFACTURING THE SAME
Kei May Lau, Renqiang Zhu
The Hong Kong University of Science and Technology, Hong Kong (CN)·Apr. 1, 2025·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 12,268,018 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A.
FIG. 2 illustrates different channel doping profiles in accordance with certain example embodiments. 65
FIG. 3A.
FIG. 4A.
FIG. 5 illustrates a method of manufacturing a GaN vertical trench MOSFET in accordance with certain example embodiments.
FIG. 6 is a schematic view illustrating a top view of a hexagonal vertical MOSFET structure including multiple cells with each cell including a GaN vertical …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN vertical trench MOSFET comprising a semiconductor transistor that has a first surface and a second surface, and a trench that extends from the first surface into the semiconductor transistor along a first direction perpen-dicular to the first and second surfaces, wherein the semiconductor transistor includes a body region having a channel region arranged along the first direction along at least a portion of a wall of the trench, and wherein a doping concentration of the channel region is non-uniform, wherein the channel region includes a first portion and a second portion having an interface with the first por-tion, the interface being in parallel with the first and second surfaces, the doping concentration of the first portion being uniform across the first portion, the doping concentration of the second portion being uni-form across the second portion, the doping concentra-tion of the second portion being greater than the doping concentration of the first portion, wherein the semiconductor transistor comprises a source region, and the source region is disposed on the body region and comprises the first surface, wherein the second portion is sandwiched between the source region and the first portion, wherein the first portion and the second portion are doped with a same type of dopants.
The GaN vertical trench MOSFET of claim 1, wherein the doping concentration of the channel region varies along the first direction.
The GaN vertical trench MOSFET of claim 1, wherein the channel region is doped with Mg having a doping concentration not less than 1E₁₇ cm⁻³.
A hexagonal vertical MOSFET structure comprising a plurality of cells with each cell including a GaN vertical trench MOSFET according to claim 1.
A GaN vertical trench MOSFET comprising: a semiconductor transistor, the semiconductor transistor having a first surface and a second surface and com-prising: a base comprising the second surface; a first epilayer of a first conductivity type that is disposed on the base and has a first doping concen-tration; a second epilayer of the first conductivity type that is disposed on the first epilayer and has a second doping concentration, the first doping concentration being greater than the second doping concentration; a body region of a second conductivity type that is disposed on the second epilayer, the second conduc-tivity type being opposite to the first conductivity type; and a source region that is disposed on the body region and comprises the first surface; and a trench that extends through the source region and the body region and into the second epilayer, the trench extending from the first surface into the semiconductor transistor along a first direction perpendicular to the first and second surface, wherein each of the first epilayer, the second epilayer, the body region, and the source region includes GaN, wherein the body region has a channel region arranged along the first direction along at least a portion of a wall of the trench, the channel region comprising a plurality of channel portions, and wherein a doping concentra-tion of the channel region is non-uniform, wherein the body region has a varying doping concentra-tion such that two or more channel portions are formed in the body region with different electrical parameters, wherein the channel region includes a first portion and a second portion having an interface with the first por-tion, the interface being in parallel with the first and second surfaces, the doping concentration of the first portion being uniform across the first portion, the doping concentration of the second portion being uni-form across the second portion, the doping concentra-tion of the second portion being greater than the doping concentration of the first portion, wherein the second portion is sandwiched between the source region and the first portion, wherein the first portion and the second portion are doped with a same type of dopants.
The GaN vertical trench MOSFET of claim 4, wherein the electrical parameters include one or more of maximum drain current, specific ON-resistance, and threshold voltage.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region decreases along a direction from the source region towards the base.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region varies in a non-linear manner along a direction from the source region towards the base.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region is not less than 1E₁₇ cm⁻³.
The GaN vertical trench MOSFET of claim 4, wherein the body region is doped with Mg having a doping concen-tration not less than 1E₁₇ cm⁻³.
The GaN vertical trench MOSFET of claim 4, wherein the base includes a substrate and a buffer layer, the substrate including one or more of GaN, Si, Sapphire, and SiC, the buffer layer being disposed on the substrate and including GaN. 11 12
The GaN vertical trench MOSFET of claim 4, wherein the first conductivity type is n-type and the second conduc-tivity type is p-type.
Layer stacks claimed or described, ordered top of device to substrate.
GaN vertical trench MOSFET (claim 1 generic)
GaN vertical trench MOSFET (claim 4 detailed)
Materials described outside the worked examples.
GaN
Mg dopant
Mg
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage (Vth) typical range for CAVETs and vertical FinFETs (prior art/background context) | 1–2 V | — |
Thickness | 1–100 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,268,018 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A.
FIG. 2 illustrates different channel doping profiles in accordance with certain example embodiments. 65
FIG. 3A.
FIG. 4A.
FIG. 5 illustrates a method of manufacturing a GaN vertical trench MOSFET in accordance with certain example embodiments.
FIG. 6 is a schematic view illustrating a top view of a hexagonal vertical MOSFET structure including multiple cells with each cell including a GaN vertical …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN vertical trench MOSFET comprising a semiconductor transistor that has a first surface and a second surface, and a trench that extends from the first surface into the semiconductor transistor along a first direction perpen-dicular to the first and second surfaces, wherein the semiconductor transistor includes a body region having a channel region arranged along the first direction along at least a portion of a wall of the trench, and wherein a doping concentration of the channel region is non-uniform, wherein the channel region includes a first portion and a second portion having an interface with the first por-tion, the interface being in parallel with the first and second surfaces, the doping concentration of the first portion being uniform across the first portion, the doping concentration of the second portion being uni-form across the second portion, the doping concentra-tion of the second portion being greater than the doping concentration of the first portion, wherein the semiconductor transistor comprises a source region, and the source region is disposed on the body region and comprises the first surface, wherein the second portion is sandwiched between the source region and the first portion, wherein the first portion and the second portion are doped with a same type of dopants.
The GaN vertical trench MOSFET of claim 1, wherein the doping concentration of the channel region varies along the first direction.
The GaN vertical trench MOSFET of claim 1, wherein the channel region is doped with Mg having a doping concentration not less than 1E₁₇ cm⁻³.
A hexagonal vertical MOSFET structure comprising a plurality of cells with each cell including a GaN vertical trench MOSFET according to claim 1.
A GaN vertical trench MOSFET comprising: a semiconductor transistor, the semiconductor transistor having a first surface and a second surface and com-prising: a base comprising the second surface; a first epilayer of a first conductivity type that is disposed on the base and has a first doping concen-tration; a second epilayer of the first conductivity type that is disposed on the first epilayer and has a second doping concentration, the first doping concentration being greater than the second doping concentration; a body region of a second conductivity type that is disposed on the second epilayer, the second conduc-tivity type being opposite to the first conductivity type; and a source region that is disposed on the body region and comprises the first surface; and a trench that extends through the source region and the body region and into the second epilayer, the trench extending from the first surface into the semiconductor transistor along a first direction perpendicular to the first and second surface, wherein each of the first epilayer, the second epilayer, the body region, and the source region includes GaN, wherein the body region has a channel region arranged along the first direction along at least a portion of a wall of the trench, the channel region comprising a plurality of channel portions, and wherein a doping concentra-tion of the channel region is non-uniform, wherein the body region has a varying doping concentra-tion such that two or more channel portions are formed in the body region with different electrical parameters, wherein the channel region includes a first portion and a second portion having an interface with the first por-tion, the interface being in parallel with the first and second surfaces, the doping concentration of the first portion being uniform across the first portion, the doping concentration of the second portion being uni-form across the second portion, the doping concentra-tion of the second portion being greater than the doping concentration of the first portion, wherein the second portion is sandwiched between the source region and the first portion, wherein the first portion and the second portion are doped with a same type of dopants.
The GaN vertical trench MOSFET of claim 4, wherein the electrical parameters include one or more of maximum drain current, specific ON-resistance, and threshold voltage.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region decreases along a direction from the source region towards the base.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region varies in a non-linear manner along a direction from the source region towards the base.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region is not less than 1E₁₇ cm⁻³.
The GaN vertical trench MOSFET of claim 4, wherein the body region is doped with Mg having a doping concen-tration not less than 1E₁₇ cm⁻³.
The GaN vertical trench MOSFET of claim 4, wherein the base includes a substrate and a buffer layer, the substrate including one or more of GaN, Si, Sapphire, and SiC, the buffer layer being disposed on the substrate and including GaN. 11 12
The GaN vertical trench MOSFET of claim 4, wherein the first conductivity type is n-type and the second conduc-tivity type is p-type.
Layer stacks claimed or described, ordered top of device to substrate.
GaN vertical trench MOSFET (claim 1 generic)
GaN vertical trench MOSFET (claim 4 detailed)
Materials described outside the worked examples.
GaN
Mg dopant
Mg
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage (Vth) typical range for CAVETs and vertical FinFETs (prior art/background context) | 1–2 V | — |
Thickness | 1–100 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,268,018 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A.
FIG. 2 illustrates different channel doping profiles in accordance with certain example embodiments. 65
FIG. 3A.
FIG. 4A.
FIG. 5 illustrates a method of manufacturing a GaN vertical trench MOSFET in accordance with certain example embodiments.
FIG. 6 is a schematic view illustrating a top view of a hexagonal vertical MOSFET structure including multiple cells with each cell including a GaN vertical …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN vertical trench MOSFET comprising a semiconductor transistor that has a first surface and a second surface, and a trench that extends from the first surface into the semiconductor transistor along a first direction perpen-dicular to the first and second surfaces, wherein the semiconductor transistor includes a body region having a channel region arranged along the first direction along at least a portion of a wall of the trench, and wherein a doping concentration of the channel region is non-uniform, wherein the channel region includes a first portion and a second portion having an interface with the first por-tion, the interface being in parallel with the first and second surfaces, the doping concentration of the first portion being uniform across the first portion, the doping concentration of the second portion being uni-form across the second portion, the doping concentra-tion of the second portion being greater than the doping concentration of the first portion, wherein the semiconductor transistor comprises a source region, and the source region is disposed on the body region and comprises the first surface, wherein the second portion is sandwiched between the source region and the first portion, wherein the first portion and the second portion are doped with a same type of dopants.
The GaN vertical trench MOSFET of claim 1, wherein the doping concentration of the channel region varies along the first direction.
The GaN vertical trench MOSFET of claim 1, wherein the channel region is doped with Mg having a doping concentration not less than 1E₁₇ cm⁻³.
A hexagonal vertical MOSFET structure comprising a plurality of cells with each cell including a GaN vertical trench MOSFET according to claim 1.
A GaN vertical trench MOSFET comprising: a semiconductor transistor, the semiconductor transistor having a first surface and a second surface and com-prising: a base comprising the second surface; a first epilayer of a first conductivity type that is disposed on the base and has a first doping concen-tration; a second epilayer of the first conductivity type that is disposed on the first epilayer and has a second doping concentration, the first doping concentration being greater than the second doping concentration; a body region of a second conductivity type that is disposed on the second epilayer, the second conduc-tivity type being opposite to the first conductivity type; and a source region that is disposed on the body region and comprises the first surface; and a trench that extends through the source region and the body region and into the second epilayer, the trench extending from the first surface into the semiconductor transistor along a first direction perpendicular to the first and second surface, wherein each of the first epilayer, the second epilayer, the body region, and the source region includes GaN, wherein the body region has a channel region arranged along the first direction along at least a portion of a wall of the trench, the channel region comprising a plurality of channel portions, and wherein a doping concentra-tion of the channel region is non-uniform, wherein the body region has a varying doping concentra-tion such that two or more channel portions are formed in the body region with different electrical parameters, wherein the channel region includes a first portion and a second portion having an interface with the first por-tion, the interface being in parallel with the first and second surfaces, the doping concentration of the first portion being uniform across the first portion, the doping concentration of the second portion being uni-form across the second portion, the doping concentra-tion of the second portion being greater than the doping concentration of the first portion, wherein the second portion is sandwiched between the source region and the first portion, wherein the first portion and the second portion are doped with a same type of dopants.
The GaN vertical trench MOSFET of claim 4, wherein the electrical parameters include one or more of maximum drain current, specific ON-resistance, and threshold voltage.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region decreases along a direction from the source region towards the base.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region varies in a non-linear manner along a direction from the source region towards the base.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region is not less than 1E₁₇ cm⁻³.
The GaN vertical trench MOSFET of claim 4, wherein the body region is doped with Mg having a doping concen-tration not less than 1E₁₇ cm⁻³.
The GaN vertical trench MOSFET of claim 4, wherein the base includes a substrate and a buffer layer, the substrate including one or more of GaN, Si, Sapphire, and SiC, the buffer layer being disposed on the substrate and including GaN. 11 12
The GaN vertical trench MOSFET of claim 4, wherein the first conductivity type is n-type and the second conduc-tivity type is p-type.
Layer stacks claimed or described, ordered top of device to substrate.
GaN vertical trench MOSFET (claim 1 generic)
GaN vertical trench MOSFET (claim 4 detailed)
Materials described outside the worked examples.
GaN
Mg dopant
Mg
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage (Vth) typical range for CAVETs and vertical FinFETs (prior art/background context) | 1–2 V | — |
Thickness | 1–100 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,268,018 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A.
FIG. 2 illustrates different channel doping profiles in accordance with certain example embodiments. 65
FIG. 3A.
FIG. 4A.
FIG. 5 illustrates a method of manufacturing a GaN vertical trench MOSFET in accordance with certain example embodiments.
FIG. 6 is a schematic view illustrating a top view of a hexagonal vertical MOSFET structure including multiple cells with each cell including a GaN vertical …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN vertical trench MOSFET comprising a semiconductor transistor that has a first surface and a second surface, and a trench that extends from the first surface into the semiconductor transistor along a first direction perpen-dicular to the first and second surfaces, wherein the semiconductor transistor includes a body region having a channel region arranged along the first direction along at least a portion of a wall of the trench, and wherein a doping concentration of the channel region is non-uniform, wherein the channel region includes a first portion and a second portion having an interface with the first por-tion, the interface being in parallel with the first and second surfaces, the doping concentration of the first portion being uniform across the first portion, the doping concentration of the second portion being uni-form across the second portion, the doping concentra-tion of the second portion being greater than the doping concentration of the first portion, wherein the semiconductor transistor comprises a source region, and the source region is disposed on the body region and comprises the first surface, wherein the second portion is sandwiched between the source region and the first portion, wherein the first portion and the second portion are doped with a same type of dopants.
The GaN vertical trench MOSFET of claim 1, wherein the doping concentration of the channel region varies along the first direction.
The GaN vertical trench MOSFET of claim 1, wherein the channel region is doped with Mg having a doping concentration not less than 1E₁₇ cm⁻³.
A hexagonal vertical MOSFET structure comprising a plurality of cells with each cell including a GaN vertical trench MOSFET according to claim 1.
A GaN vertical trench MOSFET comprising: a semiconductor transistor, the semiconductor transistor having a first surface and a second surface and com-prising: a base comprising the second surface; a first epilayer of a first conductivity type that is disposed on the base and has a first doping concen-tration; a second epilayer of the first conductivity type that is disposed on the first epilayer and has a second doping concentration, the first doping concentration being greater than the second doping concentration; a body region of a second conductivity type that is disposed on the second epilayer, the second conduc-tivity type being opposite to the first conductivity type; and a source region that is disposed on the body region and comprises the first surface; and a trench that extends through the source region and the body region and into the second epilayer, the trench extending from the first surface into the semiconductor transistor along a first direction perpendicular to the first and second surface, wherein each of the first epilayer, the second epilayer, the body region, and the source region includes GaN, wherein the body region has a channel region arranged along the first direction along at least a portion of a wall of the trench, the channel region comprising a plurality of channel portions, and wherein a doping concentra-tion of the channel region is non-uniform, wherein the body region has a varying doping concentra-tion such that two or more channel portions are formed in the body region with different electrical parameters, wherein the channel region includes a first portion and a second portion having an interface with the first por-tion, the interface being in parallel with the first and second surfaces, the doping concentration of the first portion being uniform across the first portion, the doping concentration of the second portion being uni-form across the second portion, the doping concentra-tion of the second portion being greater than the doping concentration of the first portion, wherein the second portion is sandwiched between the source region and the first portion, wherein the first portion and the second portion are doped with a same type of dopants.
The GaN vertical trench MOSFET of claim 4, wherein the electrical parameters include one or more of maximum drain current, specific ON-resistance, and threshold voltage.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region decreases along a direction from the source region towards the base.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region varies in a non-linear manner along a direction from the source region towards the base.
The GaN vertical trench MOSFET of claim 4, wherein the doping concentration of the body region is not less than 1E₁₇ cm⁻³.
The GaN vertical trench MOSFET of claim 4, wherein the body region is doped with Mg having a doping concen-tration not less than 1E₁₇ cm⁻³.
The GaN vertical trench MOSFET of claim 4, wherein the base includes a substrate and a buffer layer, the substrate including one or more of GaN, Si, Sapphire, and SiC, the buffer layer being disposed on the substrate and including GaN. 11 12
The GaN vertical trench MOSFET of claim 4, wherein the first conductivity type is n-type and the second conduc-tivity type is p-type.
Layer stacks claimed or described, ordered top of device to substrate.
GaN vertical trench MOSFET (claim 1 generic)
GaN vertical trench MOSFET (claim 4 detailed)
Materials described outside the worked examples.
GaN
Mg dopant
Mg
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
threshold voltage (Vth) typical range for CAVETs and vertical FinFETs (prior art/background context) | 1–2 V | — |
Thickness | 1–100 µm |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 12
Related documents with shared materials, methods, properties, or citations.
hexagonal vertical MOSFET structure (multi-cell)
No layer stack recorded.
Si
Sapphire
SiC
aluminum oxide gate dielectric
Al₂O₃
FIG. 6 is a schematic view illustrating a top view of a hexagonal vertical MOSFET structure including multiple cells with each cell including a GaN vertical …
| — |
Thickness | 5–30 µm | — |
Thickness | 20–70 µm | — |
Thickness | 40–90 µm | — |
Temperature | ≥ 600 °C | — |
Thickness | ≤ 100000000000000000 cm | — |
Cited non-patent literature · 2
hexagonal vertical MOSFET structure (multi-cell)
No layer stack recorded.
Si
Sapphire
SiC
aluminum oxide gate dielectric
Al₂O₃
FIG. 6 is a schematic view illustrating a top view of a hexagonal vertical MOSFET structure including multiple cells with each cell including a GaN vertical …
| — |
Thickness | 5–30 µm | — |
Thickness | 20–70 µm | — |
Thickness | 40–90 µm | — |
Temperature | ≥ 600 °C | — |
Thickness | ≤ 100000000000000000 cm | — |
Cited non-patent literature · 2
hexagonal vertical MOSFET structure (multi-cell)
No layer stack recorded.
Si
Sapphire
SiC
aluminum oxide gate dielectric
Al₂O₃
FIG. 6 is a schematic view illustrating a top view of a hexagonal vertical MOSFET structure including multiple cells with each cell including a GaN vertical …
| — |
Thickness | 5–30 µm | — |
Thickness | 20–70 µm | — |
Thickness | 40–90 µm | — |
Temperature | ≥ 600 °C | — |
Thickness | ≤ 100000000000000000 cm | — |
Cited non-patent literature · 2
hexagonal vertical MOSFET structure (multi-cell)
No layer stack recorded.
Si
Sapphire
SiC
aluminum oxide gate dielectric
Al₂O₃
FIG. 6 is a schematic view illustrating a top view of a hexagonal vertical MOSFET structure including multiple cells with each cell including a GaN vertical …
| — |
Thickness | 5–30 µm | — |
Thickness | 20–70 µm | — |
Thickness | 40–90 µm | — |
Temperature | ≥ 600 °C | — |
Thickness | ≤ 100000000000000000 cm | — |
Cited non-patent literature · 2