Patent
US 9,318,619VERTICAL GALLIUM NITRIDE JFET WITH GATE AND SOURCE ELECTRODES ON REGROWN GATE
Donald R. Disney
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 9,318,619Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Source regions 705 may be disposed on the top of channel regions 702. Source regions 705 may have the same conductivity type (e.g. N-type) as channel …
FIG. 2 illustrates a cross-sectional view of vertical power device 100 taken along the A- A' line illustrated in
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0037] In some …
FIG. 4 is a top view of a vertical power device 400 according to another embodiment of the present invention. In some embodiments, vertical power device 400 …
FIGS. 5A-7 B illustrate cross-sectional views during various steps in the fabrication of vertical power device with edge termination structures according to an …
FIG. 6B. Thus, continuous gate region 510 along with finger-shaped gate regions 704 together form the gate of the vertical power device. 30 This is more clearly …
FIG. 7 B, source contacts 706 are formed and coupled to each source region 705. Each source contact 706 is then coupled to a source electrode 708 5 that …
FIG. 8 is a simplified flowchart illustrating a method of fabricating a vertical JFET with 15 edge termination structures enclosing a regrown gate region …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
A method of manufacturing a vertical junction field effect transistor (VJF E T), the method comprising: providing a I II -nitride substrate; forming a first I II -nitride layer coupled to the substrate, wherein the first III- nitride layer has a first conductivity type; after forming the first I II -nitride layer, forming a plurality of gate projections in a second I II -nitride layer, wherein the second I II -nitride layer has a second conductivity type; after forming the gate projections, forming a plurality of channel regions in the first I II -nitride layer, wherein the channel regions are interleaved with the gate projections; and forming a plurality of source regions in a third I II-nitride layer, wherein the third III -nitride layer has the first conductivity type, and wherein each of the source regions is coupled to one of the channel regions.
The method of claim 2, claim 1, wherein forming the channel regions comprises epitaxially growing the channel regions in the first I II -nitride layer.
The method of claim 2, claim 1, f u rther comprising forming an edge termination structure surrounding the channel regions, the gate projections, and the source regions.
The method of claim 2, claim 1, wherein a drain is at least partly formed by a portion of the I II -nitride substrate.
The method of claim 2, claim 1, wherein: the I II -nitride substrate comprises GaN; Page 2 of 7 App l. No. 14/606,822 PATENT Am dt. dated Response to Office Action of the first I II -nitride layer comprises GaN; the second I II -nitride layer comprises GaN; and the third I II -nitride layer comprises GaN.
The method of claim 2, claim 1, further comprising: forming a source electrode electrically connected to the source regions; forming a gate electrode electrically connected to the gate projections; and forming a drain electrode electrically connected to the I II -nitride substrate.
A vertical junction field effect transistor (VJFET) formed by a method comprising: providing a I II -nitride substrate; forming a first I II -nitride layer coupled to the substrate, wherein the first III- nitride layer has a first conductivity type; after forming the first I II -nitride layer, forming a plurality of gate projections in a second I II -nitride layer, wherein the second I II -nitride layer has a second conductivity type, after forming the gate projections, forming a plurality of channel regions in the first I II -nitride layer, wherein the channel regions are interleaved with the gate projections; and Page 3 of 7 App l. No. 14/606,822 PATENT Am dt. dated Response to Office Action of forming a plurality of source regions in a third I II -nitride layer, wherein the third III -nitride layer has the first conductivity type, and wherein each of the source regions is coupled to one of the channel regions.
The VJFET of claim 12, wherein forming the channel regions comprises epitaxially growing the channel regions in the first I II -nitride layer.
The VJFET of claim 12, wherein the method further comprises forming an edge termination structure surrounding the channel regions, the gate projections, and the source regions.
The VJFET of claim 12, wherein a drain is at least partly formed by a portion of the III-nitride substrate.
The VJFET of claim 12, wherein: the III -nitride substrate comprises GaN; the first III -nitride layer comprises GaN; the second I II -nitride layer comprises GaN; and the third III -nitride layer comprises GaN.
The VJFET of claim 12, wherein the method further comprises: forming a source electrode electrically connected to the source regions; forming a gate electrode electrically connected to the gate projections; and forming a drain electrode electrically connected to the III -nitride substrate.
Layer stacks claimed or described, ordered top of device to substrate.
Vertical Junction Field Effect Transistor (VJFET)
Vertical JFET with GaN layers and edge termination
Materials described outside the worked examples.
III-nitride substrate
first III-nitride layer
second III-nitride layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0037] In some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,318,619Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Source regions 705 may be disposed on the top of channel regions 702. Source regions 705 may have the same conductivity type (e.g. N-type) as channel …
FIG. 2 illustrates a cross-sectional view of vertical power device 100 taken along the A- A' line illustrated in
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0037] In some …
FIG. 4 is a top view of a vertical power device 400 according to another embodiment of the present invention. In some embodiments, vertical power device 400 …
FIGS. 5A-7 B illustrate cross-sectional views during various steps in the fabrication of vertical power device with edge termination structures according to an …
FIG. 6B. Thus, continuous gate region 510 along with finger-shaped gate regions 704 together form the gate of the vertical power device. 30 This is more clearly …
FIG. 7 B, source contacts 706 are formed and coupled to each source region 705. Each source contact 706 is then coupled to a source electrode 708 5 that …
FIG. 8 is a simplified flowchart illustrating a method of fabricating a vertical JFET with 15 edge termination structures enclosing a regrown gate region …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
A method of manufacturing a vertical junction field effect transistor (VJF E T), the method comprising: providing a I II -nitride substrate; forming a first I II -nitride layer coupled to the substrate, wherein the first III- nitride layer has a first conductivity type; after forming the first I II -nitride layer, forming a plurality of gate projections in a second I II -nitride layer, wherein the second I II -nitride layer has a second conductivity type; after forming the gate projections, forming a plurality of channel regions in the first I II -nitride layer, wherein the channel regions are interleaved with the gate projections; and forming a plurality of source regions in a third I II-nitride layer, wherein the third III -nitride layer has the first conductivity type, and wherein each of the source regions is coupled to one of the channel regions.
The method of claim 2, claim 1, wherein forming the channel regions comprises epitaxially growing the channel regions in the first I II -nitride layer.
The method of claim 2, claim 1, f u rther comprising forming an edge termination structure surrounding the channel regions, the gate projections, and the source regions.
The method of claim 2, claim 1, wherein a drain is at least partly formed by a portion of the I II -nitride substrate.
The method of claim 2, claim 1, wherein: the I II -nitride substrate comprises GaN; Page 2 of 7 App l. No. 14/606,822 PATENT Am dt. dated Response to Office Action of the first I II -nitride layer comprises GaN; the second I II -nitride layer comprises GaN; and the third I II -nitride layer comprises GaN.
The method of claim 2, claim 1, further comprising: forming a source electrode electrically connected to the source regions; forming a gate electrode electrically connected to the gate projections; and forming a drain electrode electrically connected to the I II -nitride substrate.
A vertical junction field effect transistor (VJFET) formed by a method comprising: providing a I II -nitride substrate; forming a first I II -nitride layer coupled to the substrate, wherein the first III- nitride layer has a first conductivity type; after forming the first I II -nitride layer, forming a plurality of gate projections in a second I II -nitride layer, wherein the second I II -nitride layer has a second conductivity type, after forming the gate projections, forming a plurality of channel regions in the first I II -nitride layer, wherein the channel regions are interleaved with the gate projections; and Page 3 of 7 App l. No. 14/606,822 PATENT Am dt. dated Response to Office Action of forming a plurality of source regions in a third I II -nitride layer, wherein the third III -nitride layer has the first conductivity type, and wherein each of the source regions is coupled to one of the channel regions.
The VJFET of claim 12, wherein forming the channel regions comprises epitaxially growing the channel regions in the first I II -nitride layer.
The VJFET of claim 12, wherein the method further comprises forming an edge termination structure surrounding the channel regions, the gate projections, and the source regions.
The VJFET of claim 12, wherein a drain is at least partly formed by a portion of the III-nitride substrate.
The VJFET of claim 12, wherein: the III -nitride substrate comprises GaN; the first III -nitride layer comprises GaN; the second I II -nitride layer comprises GaN; and the third III -nitride layer comprises GaN.
The VJFET of claim 12, wherein the method further comprises: forming a source electrode electrically connected to the source regions; forming a gate electrode electrically connected to the gate projections; and forming a drain electrode electrically connected to the III -nitride substrate.
Layer stacks claimed or described, ordered top of device to substrate.
Vertical Junction Field Effect Transistor (VJFET)
Vertical JFET with GaN layers and edge termination
Materials described outside the worked examples.
III-nitride substrate
first III-nitride layer
second III-nitride layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0037] In some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,318,619Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Source regions 705 may be disposed on the top of channel regions 702. Source regions 705 may have the same conductivity type (e.g. N-type) as channel …
FIG. 2 illustrates a cross-sectional view of vertical power device 100 taken along the A- A' line illustrated in
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0037] In some …
FIG. 4 is a top view of a vertical power device 400 according to another embodiment of the present invention. In some embodiments, vertical power device 400 …
FIGS. 5A-7 B illustrate cross-sectional views during various steps in the fabrication of vertical power device with edge termination structures according to an …
FIG. 6B. Thus, continuous gate region 510 along with finger-shaped gate regions 704 together form the gate of the vertical power device. 30 This is more clearly …
FIG. 7 B, source contacts 706 are formed and coupled to each source region 705. Each source contact 706 is then coupled to a source electrode 708 5 that …
FIG. 8 is a simplified flowchart illustrating a method of fabricating a vertical JFET with 15 edge termination structures enclosing a regrown gate region …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
A method of manufacturing a vertical junction field effect transistor (VJF E T), the method comprising: providing a I II -nitride substrate; forming a first I II -nitride layer coupled to the substrate, wherein the first III- nitride layer has a first conductivity type; after forming the first I II -nitride layer, forming a plurality of gate projections in a second I II -nitride layer, wherein the second I II -nitride layer has a second conductivity type; after forming the gate projections, forming a plurality of channel regions in the first I II -nitride layer, wherein the channel regions are interleaved with the gate projections; and forming a plurality of source regions in a third I II-nitride layer, wherein the third III -nitride layer has the first conductivity type, and wherein each of the source regions is coupled to one of the channel regions.
The method of claim 2, claim 1, wherein forming the channel regions comprises epitaxially growing the channel regions in the first I II -nitride layer.
The method of claim 2, claim 1, f u rther comprising forming an edge termination structure surrounding the channel regions, the gate projections, and the source regions.
The method of claim 2, claim 1, wherein a drain is at least partly formed by a portion of the I II -nitride substrate.
The method of claim 2, claim 1, wherein: the I II -nitride substrate comprises GaN; Page 2 of 7 App l. No. 14/606,822 PATENT Am dt. dated Response to Office Action of the first I II -nitride layer comprises GaN; the second I II -nitride layer comprises GaN; and the third I II -nitride layer comprises GaN.
The method of claim 2, claim 1, further comprising: forming a source electrode electrically connected to the source regions; forming a gate electrode electrically connected to the gate projections; and forming a drain electrode electrically connected to the I II -nitride substrate.
A vertical junction field effect transistor (VJFET) formed by a method comprising: providing a I II -nitride substrate; forming a first I II -nitride layer coupled to the substrate, wherein the first III- nitride layer has a first conductivity type; after forming the first I II -nitride layer, forming a plurality of gate projections in a second I II -nitride layer, wherein the second I II -nitride layer has a second conductivity type, after forming the gate projections, forming a plurality of channel regions in the first I II -nitride layer, wherein the channel regions are interleaved with the gate projections; and Page 3 of 7 App l. No. 14/606,822 PATENT Am dt. dated Response to Office Action of forming a plurality of source regions in a third I II -nitride layer, wherein the third III -nitride layer has the first conductivity type, and wherein each of the source regions is coupled to one of the channel regions.
The VJFET of claim 12, wherein forming the channel regions comprises epitaxially growing the channel regions in the first I II -nitride layer.
The VJFET of claim 12, wherein the method further comprises forming an edge termination structure surrounding the channel regions, the gate projections, and the source regions.
The VJFET of claim 12, wherein a drain is at least partly formed by a portion of the III-nitride substrate.
The VJFET of claim 12, wherein: the III -nitride substrate comprises GaN; the first III -nitride layer comprises GaN; the second I II -nitride layer comprises GaN; and the third III -nitride layer comprises GaN.
The VJFET of claim 12, wherein the method further comprises: forming a source electrode electrically connected to the source regions; forming a gate electrode electrically connected to the gate projections; and forming a drain electrode electrically connected to the III -nitride substrate.
Layer stacks claimed or described, ordered top of device to substrate.
Vertical Junction Field Effect Transistor (VJFET)
Vertical JFET with GaN layers and edge termination
Materials described outside the worked examples.
III-nitride substrate
first III-nitride layer
second III-nitride layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0037] In some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,318,619Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. Source regions 705 may be disposed on the top of channel regions 702. Source regions 705 may have the same conductivity type (e.g. N-type) as channel …
FIG. 2 illustrates a cross-sectional view of vertical power device 100 taken along the A- A' line illustrated in
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0037] In some …
FIG. 4 is a top view of a vertical power device 400 according to another embodiment of the present invention. In some embodiments, vertical power device 400 …
FIGS. 5A-7 B illustrate cross-sectional views during various steps in the fabrication of vertical power device with edge termination structures according to an …
FIG. 6B. Thus, continuous gate region 510 along with finger-shaped gate regions 704 together form the gate of the vertical power device. 30 This is more clearly …
FIG. 7 B, source contacts 706 are formed and coupled to each source region 705. Each source contact 706 is then coupled to a source electrode 708 5 that …
FIG. 8 is a simplified flowchart illustrating a method of fabricating a vertical JFET with 15 edge termination structures enclosing a regrown gate region …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
A method of manufacturing a vertical junction field effect transistor (VJF E T), the method comprising: providing a I II -nitride substrate; forming a first I II -nitride layer coupled to the substrate, wherein the first III- nitride layer has a first conductivity type; after forming the first I II -nitride layer, forming a plurality of gate projections in a second I II -nitride layer, wherein the second I II -nitride layer has a second conductivity type; after forming the gate projections, forming a plurality of channel regions in the first I II -nitride layer, wherein the channel regions are interleaved with the gate projections; and forming a plurality of source regions in a third I II-nitride layer, wherein the third III -nitride layer has the first conductivity type, and wherein each of the source regions is coupled to one of the channel regions.
The method of claim 2, claim 1, wherein forming the channel regions comprises epitaxially growing the channel regions in the first I II -nitride layer.
The method of claim 2, claim 1, f u rther comprising forming an edge termination structure surrounding the channel regions, the gate projections, and the source regions.
The method of claim 2, claim 1, wherein a drain is at least partly formed by a portion of the I II -nitride substrate.
The method of claim 2, claim 1, wherein: the I II -nitride substrate comprises GaN; Page 2 of 7 App l. No. 14/606,822 PATENT Am dt. dated Response to Office Action of the first I II -nitride layer comprises GaN; the second I II -nitride layer comprises GaN; and the third I II -nitride layer comprises GaN.
The method of claim 2, claim 1, further comprising: forming a source electrode electrically connected to the source regions; forming a gate electrode electrically connected to the gate projections; and forming a drain electrode electrically connected to the I II -nitride substrate.
A vertical junction field effect transistor (VJFET) formed by a method comprising: providing a I II -nitride substrate; forming a first I II -nitride layer coupled to the substrate, wherein the first III- nitride layer has a first conductivity type; after forming the first I II -nitride layer, forming a plurality of gate projections in a second I II -nitride layer, wherein the second I II -nitride layer has a second conductivity type, after forming the gate projections, forming a plurality of channel regions in the first I II -nitride layer, wherein the channel regions are interleaved with the gate projections; and Page 3 of 7 App l. No. 14/606,822 PATENT Am dt. dated Response to Office Action of forming a plurality of source regions in a third I II -nitride layer, wherein the third III -nitride layer has the first conductivity type, and wherein each of the source regions is coupled to one of the channel regions.
The VJFET of claim 12, wherein forming the channel regions comprises epitaxially growing the channel regions in the first I II -nitride layer.
The VJFET of claim 12, wherein the method further comprises forming an edge termination structure surrounding the channel regions, the gate projections, and the source regions.
The VJFET of claim 12, wherein a drain is at least partly formed by a portion of the III-nitride substrate.
The VJFET of claim 12, wherein: the III -nitride substrate comprises GaN; the first III -nitride layer comprises GaN; the second I II -nitride layer comprises GaN; and the third III -nitride layer comprises GaN.
The VJFET of claim 12, wherein the method further comprises: forming a source electrode electrically connected to the source regions; forming a gate electrode electrically connected to the gate projections; and forming a drain electrode electrically connected to the III -nitride substrate.
Layer stacks claimed or described, ordered top of device to substrate.
Vertical Junction Field Effect Transistor (VJFET)
Vertical JFET with GaN layers and edge termination
Materials described outside the worked examples.
III-nitride substrate
first III-nitride layer
second III-nitride layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0037] In some …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
third III-nitride layer
GaN substrate
GaN
FIG. 4 is a top view of a vertical power device 400 according to another embodiment of the present invention. In some embodiments, vertical power device 400 …
FIG. 7 B, source contacts 706 are formed and coupled to each source region 705. Each source contact 706 is then coupled to a source electrode 708 5 that …
third III-nitride layer
GaN substrate
GaN
FIG. 4 is a top view of a vertical power device 400 according to another embodiment of the present invention. In some embodiments, vertical power device 400 …
FIG. 7 B, source contacts 706 are formed and coupled to each source region 705. Each source contact 706 is then coupled to a source electrode 708 5 that …
third III-nitride layer
GaN substrate
GaN
FIG. 4 is a top view of a vertical power device 400 according to another embodiment of the present invention. In some embodiments, vertical power device 400 …
FIG. 7 B, source contacts 706 are formed and coupled to each source region 705. Each source contact 706 is then coupled to a source electrode 708 5 that …
third III-nitride layer
GaN substrate
GaN
FIG. 4 is a top view of a vertical power device 400 according to another embodiment of the present invention. In some embodiments, vertical power device 400 …
FIG. 7 B, source contacts 706 are formed and coupled to each source region 705. Each source contact 706 is then coupled to a source electrode 708 5 that …