Patent
US 9,029,210GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS
Hui Nie, Andrew P. Edwards, Donald R. Disney, Isik C. Kizilyalli
AVOGY, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,029,210Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified cross-sectional diagram of a vertical superjunction diode according to one embodiment; 3 Kilpatrick Townsend 66346116 1 [0009]
FIGS. 2-11 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction diode according to an embodiment of the present …
FIG. 3, a second GaN epitaxial layer 310 is provided, which can be 5 coupled to the first GaN epitaxial layer 220. The second GaN epitaxial layer 310, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 410 coupled to the second GaN epitaxial layer 310. The third GaN epitaxial layer 410 may have …
FIG. 5, portions of the third GaN epitaxial layer 410, and the second GaN epitaxial layer 310 are removed to expose sidewalls 513 of the second GaN epitaxial …
FIG. 6 illustrates how masking materia l 610 can be formed on remaining portion(s) of the third GaN epitaxial layer 410. In this embodiment, this masking …
FIGS. 7-8, illustrate a selective regrowth process used to form a fourth GaN epitaxial 25 layer 710 and a fifth GaN epitaxial layer 810. These epitaxial layers …
FIG. 9 illustrates the formation of a metal structure 910 below the GaN substrate 210. The metal structure 910 can be one or more layers of Ohmic metal that …
FIG. 10. Here, however, a third GaN epitaxial layer 1310 10 can comprise a more heavily-doped epitaxial layer than the corresponding third GaN epitaxial layer …
FIG. 11 shows the formation of a metal structure 1110 on the exposed surfaces 417, 717, 817 (shown in
FIG. 12 is a flowchart illustrating a method of fabricating a vertical superjunction diode according to one embodiment; 5 [0011]
FIGS. 13-15 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction junction field-effect transistor (JFET) according to …
FIG. 14 illustrates the formation of the source contacts 1410 of the vertical superjunction JFET. The source contacts 1410 can comprise one or more metal …
FIG. 16 is a simplified flowchart illustrating a method of fabricating a vertical superjunction JFET according to another embodiment of the present invention; …
FIG. 17 is a schematic drawing illustrating a simplified circuit implementation of a vertical superjunction JFET. [0014] In the appended figures, similar …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical superjunction device, the method comp ri sing: providing a III -nitride substrate of a first conductivity type; forming a first I II -nitride epitaxial layer of the first conductivity type coupled to the I II -nitride substrate; forming a second I II -nitride epitaxial layer coupled to the first I II -nitride epitaxial layer; forming a third I II -nitride epitaxial layer of the first conductivity type coupled to the second I II -nitride epitaxial layer; removing a portion of the third I II -nitride epitaxial layer and a portion of the second I II -nitride epitaxial layer to expose a sidewall of the second I II -nitride epitaxial layer and an exposed surface of the first I II-nitride epitaxial layer; forming a masking material coupled to a surface of a remaining portion of the third I II -nitride epitaxial layer; forming a fourth I II -nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second I II -nitride epitaxial layer and the exposed surface of the first I II -nitride epitaxial layer; forming a fifth I II -nitride epitaxial layer of a second conductivity type coupled to the fourth I II -nitride epitaxial layer; removing at least a portion of the masking material to expose: the surface of the remaining portion of the third I II-nitride epitaxial layer, a surface of the fourth I II -nitride epitaxial layer, and a surface of the fifth I II -nitride epitaxial layer; and forming one or more insulating structures coupled to the fifth I II-nitride epitaxial layer.
The method of claim 1 f u rther comprising forming a metal structure coupled to: at least one of the one or more insulating structures; 20 Kilpatrick Townsend 66346116 1 the exposed surface of the remaining portion of the third I II -nitride epitaxial layer; the exposed surface of the fourth I II -nitride epitaxial layer; and the exposed surface of the fifth I II -nitride epitaxial layer.
The method of claim 1 wherein forming at least one of the fourth III- nitride epitaxial layer or the fifth I II -nitride epitaxial layer comprises an epitaxial regrowth process.
The method of claim 1 f u rther comprising forming a metal structure coupled to the I II -nitride substrate, wherein the metal structure forms an ohmic electrical contact with the I II -nitride substrate.
The method of claim 1 wherein the second I II -nitride epitaxial layer is of the second conductivity type.
The method of claim 1 wherein the second I II -nitride epitaxial layer has intrinsic conductivity.
The method of claim 1 f u rther comprising: forming a first metal structure coupled to the exposed surface of the remaining portion of the third I II -nitride epitaxial layer, wherein the first metal structure forms a first ohmic contact with the exposed surface of the remaining portion of the third I II -nitride epitaxial layer; and forming a second metal structure coupled to: at least one of the one or more insulating structures; and the fifth I II -nitride epitaxial layer, wherein the second metal structure forms a second ohmic contact with the surface of the fifth I II -nitride epitaxial layer.
The method of claim 1 wherein the fourth I II epitaxial layer are substantially charge balanced.
The method of claim 1 wherein the first conductivity at least one of silicon or oxygen. 21 Kilpatrick -nitride epitaxial layer and the fifth I II -nitride type is n-type having a dopant including Townsend 66346116 1
Layer stacks claimed or described, ordered top of device to substrate.
vertical superjunction JFET/GaN vertical superjunction device
Materials described outside the worked examples.
III-nitride substrate of first conductivity type
first III-nitride epitaxial layer of first conductivity type
second III-nitride epitaxial layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 13-15 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction junction field-effect transistor (JFET) according to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,029,210Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified cross-sectional diagram of a vertical superjunction diode according to one embodiment; 3 Kilpatrick Townsend 66346116 1 [0009]
FIGS. 2-11 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction diode according to an embodiment of the present …
FIG. 3, a second GaN epitaxial layer 310 is provided, which can be 5 coupled to the first GaN epitaxial layer 220. The second GaN epitaxial layer 310, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 410 coupled to the second GaN epitaxial layer 310. The third GaN epitaxial layer 410 may have …
FIG. 5, portions of the third GaN epitaxial layer 410, and the second GaN epitaxial layer 310 are removed to expose sidewalls 513 of the second GaN epitaxial …
FIG. 6 illustrates how masking materia l 610 can be formed on remaining portion(s) of the third GaN epitaxial layer 410. In this embodiment, this masking …
FIGS. 7-8, illustrate a selective regrowth process used to form a fourth GaN epitaxial 25 layer 710 and a fifth GaN epitaxial layer 810. These epitaxial layers …
FIG. 9 illustrates the formation of a metal structure 910 below the GaN substrate 210. The metal structure 910 can be one or more layers of Ohmic metal that …
FIG. 10. Here, however, a third GaN epitaxial layer 1310 10 can comprise a more heavily-doped epitaxial layer than the corresponding third GaN epitaxial layer …
FIG. 11 shows the formation of a metal structure 1110 on the exposed surfaces 417, 717, 817 (shown in
FIG. 12 is a flowchart illustrating a method of fabricating a vertical superjunction diode according to one embodiment; 5 [0011]
FIGS. 13-15 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction junction field-effect transistor (JFET) according to …
FIG. 14 illustrates the formation of the source contacts 1410 of the vertical superjunction JFET. The source contacts 1410 can comprise one or more metal …
FIG. 16 is a simplified flowchart illustrating a method of fabricating a vertical superjunction JFET according to another embodiment of the present invention; …
FIG. 17 is a schematic drawing illustrating a simplified circuit implementation of a vertical superjunction JFET. [0014] In the appended figures, similar …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical superjunction device, the method comp ri sing: providing a III -nitride substrate of a first conductivity type; forming a first I II -nitride epitaxial layer of the first conductivity type coupled to the I II -nitride substrate; forming a second I II -nitride epitaxial layer coupled to the first I II -nitride epitaxial layer; forming a third I II -nitride epitaxial layer of the first conductivity type coupled to the second I II -nitride epitaxial layer; removing a portion of the third I II -nitride epitaxial layer and a portion of the second I II -nitride epitaxial layer to expose a sidewall of the second I II -nitride epitaxial layer and an exposed surface of the first I II-nitride epitaxial layer; forming a masking material coupled to a surface of a remaining portion of the third I II -nitride epitaxial layer; forming a fourth I II -nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second I II -nitride epitaxial layer and the exposed surface of the first I II -nitride epitaxial layer; forming a fifth I II -nitride epitaxial layer of a second conductivity type coupled to the fourth I II -nitride epitaxial layer; removing at least a portion of the masking material to expose: the surface of the remaining portion of the third I II-nitride epitaxial layer, a surface of the fourth I II -nitride epitaxial layer, and a surface of the fifth I II -nitride epitaxial layer; and forming one or more insulating structures coupled to the fifth I II-nitride epitaxial layer.
The method of claim 1 f u rther comprising forming a metal structure coupled to: at least one of the one or more insulating structures; 20 Kilpatrick Townsend 66346116 1 the exposed surface of the remaining portion of the third I II -nitride epitaxial layer; the exposed surface of the fourth I II -nitride epitaxial layer; and the exposed surface of the fifth I II -nitride epitaxial layer.
The method of claim 1 wherein forming at least one of the fourth III- nitride epitaxial layer or the fifth I II -nitride epitaxial layer comprises an epitaxial regrowth process.
The method of claim 1 f u rther comprising forming a metal structure coupled to the I II -nitride substrate, wherein the metal structure forms an ohmic electrical contact with the I II -nitride substrate.
The method of claim 1 wherein the second I II -nitride epitaxial layer is of the second conductivity type.
The method of claim 1 wherein the second I II -nitride epitaxial layer has intrinsic conductivity.
The method of claim 1 f u rther comprising: forming a first metal structure coupled to the exposed surface of the remaining portion of the third I II -nitride epitaxial layer, wherein the first metal structure forms a first ohmic contact with the exposed surface of the remaining portion of the third I II -nitride epitaxial layer; and forming a second metal structure coupled to: at least one of the one or more insulating structures; and the fifth I II -nitride epitaxial layer, wherein the second metal structure forms a second ohmic contact with the surface of the fifth I II -nitride epitaxial layer.
The method of claim 1 wherein the fourth I II epitaxial layer are substantially charge balanced.
The method of claim 1 wherein the first conductivity at least one of silicon or oxygen. 21 Kilpatrick -nitride epitaxial layer and the fifth I II -nitride type is n-type having a dopant including Townsend 66346116 1
Layer stacks claimed or described, ordered top of device to substrate.
vertical superjunction JFET/GaN vertical superjunction device
Materials described outside the worked examples.
III-nitride substrate of first conductivity type
first III-nitride epitaxial layer of first conductivity type
second III-nitride epitaxial layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 13-15 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction junction field-effect transistor (JFET) according to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,029,210Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified cross-sectional diagram of a vertical superjunction diode according to one embodiment; 3 Kilpatrick Townsend 66346116 1 [0009]
FIGS. 2-11 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction diode according to an embodiment of the present …
FIG. 3, a second GaN epitaxial layer 310 is provided, which can be 5 coupled to the first GaN epitaxial layer 220. The second GaN epitaxial layer 310, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 410 coupled to the second GaN epitaxial layer 310. The third GaN epitaxial layer 410 may have …
FIG. 5, portions of the third GaN epitaxial layer 410, and the second GaN epitaxial layer 310 are removed to expose sidewalls 513 of the second GaN epitaxial …
FIG. 6 illustrates how masking materia l 610 can be formed on remaining portion(s) of the third GaN epitaxial layer 410. In this embodiment, this masking …
FIGS. 7-8, illustrate a selective regrowth process used to form a fourth GaN epitaxial 25 layer 710 and a fifth GaN epitaxial layer 810. These epitaxial layers …
FIG. 9 illustrates the formation of a metal structure 910 below the GaN substrate 210. The metal structure 910 can be one or more layers of Ohmic metal that …
FIG. 10. Here, however, a third GaN epitaxial layer 1310 10 can comprise a more heavily-doped epitaxial layer than the corresponding third GaN epitaxial layer …
FIG. 11 shows the formation of a metal structure 1110 on the exposed surfaces 417, 717, 817 (shown in
FIG. 12 is a flowchart illustrating a method of fabricating a vertical superjunction diode according to one embodiment; 5 [0011]
FIGS. 13-15 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction junction field-effect transistor (JFET) according to …
FIG. 14 illustrates the formation of the source contacts 1410 of the vertical superjunction JFET. The source contacts 1410 can comprise one or more metal …
FIG. 16 is a simplified flowchart illustrating a method of fabricating a vertical superjunction JFET according to another embodiment of the present invention; …
FIG. 17 is a schematic drawing illustrating a simplified circuit implementation of a vertical superjunction JFET. [0014] In the appended figures, similar …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical superjunction device, the method comp ri sing: providing a III -nitride substrate of a first conductivity type; forming a first I II -nitride epitaxial layer of the first conductivity type coupled to the I II -nitride substrate; forming a second I II -nitride epitaxial layer coupled to the first I II -nitride epitaxial layer; forming a third I II -nitride epitaxial layer of the first conductivity type coupled to the second I II -nitride epitaxial layer; removing a portion of the third I II -nitride epitaxial layer and a portion of the second I II -nitride epitaxial layer to expose a sidewall of the second I II -nitride epitaxial layer and an exposed surface of the first I II-nitride epitaxial layer; forming a masking material coupled to a surface of a remaining portion of the third I II -nitride epitaxial layer; forming a fourth I II -nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second I II -nitride epitaxial layer and the exposed surface of the first I II -nitride epitaxial layer; forming a fifth I II -nitride epitaxial layer of a second conductivity type coupled to the fourth I II -nitride epitaxial layer; removing at least a portion of the masking material to expose: the surface of the remaining portion of the third I II-nitride epitaxial layer, a surface of the fourth I II -nitride epitaxial layer, and a surface of the fifth I II -nitride epitaxial layer; and forming one or more insulating structures coupled to the fifth I II-nitride epitaxial layer.
The method of claim 1 f u rther comprising forming a metal structure coupled to: at least one of the one or more insulating structures; 20 Kilpatrick Townsend 66346116 1 the exposed surface of the remaining portion of the third I II -nitride epitaxial layer; the exposed surface of the fourth I II -nitride epitaxial layer; and the exposed surface of the fifth I II -nitride epitaxial layer.
The method of claim 1 wherein forming at least one of the fourth III- nitride epitaxial layer or the fifth I II -nitride epitaxial layer comprises an epitaxial regrowth process.
The method of claim 1 f u rther comprising forming a metal structure coupled to the I II -nitride substrate, wherein the metal structure forms an ohmic electrical contact with the I II -nitride substrate.
The method of claim 1 wherein the second I II -nitride epitaxial layer is of the second conductivity type.
The method of claim 1 wherein the second I II -nitride epitaxial layer has intrinsic conductivity.
The method of claim 1 f u rther comprising: forming a first metal structure coupled to the exposed surface of the remaining portion of the third I II -nitride epitaxial layer, wherein the first metal structure forms a first ohmic contact with the exposed surface of the remaining portion of the third I II -nitride epitaxial layer; and forming a second metal structure coupled to: at least one of the one or more insulating structures; and the fifth I II -nitride epitaxial layer, wherein the second metal structure forms a second ohmic contact with the surface of the fifth I II -nitride epitaxial layer.
The method of claim 1 wherein the fourth I II epitaxial layer are substantially charge balanced.
The method of claim 1 wherein the first conductivity at least one of silicon or oxygen. 21 Kilpatrick -nitride epitaxial layer and the fifth I II -nitride type is n-type having a dopant including Townsend 66346116 1
Layer stacks claimed or described, ordered top of device to substrate.
vertical superjunction JFET/GaN vertical superjunction device
Materials described outside the worked examples.
III-nitride substrate of first conductivity type
first III-nitride epitaxial layer of first conductivity type
second III-nitride epitaxial layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 13-15 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction junction field-effect transistor (JFET) according to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,029,210Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified cross-sectional diagram of a vertical superjunction diode according to one embodiment; 3 Kilpatrick Townsend 66346116 1 [0009]
FIGS. 2-11 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction diode according to an embodiment of the present …
FIG. 3, a second GaN epitaxial layer 310 is provided, which can be 5 coupled to the first GaN epitaxial layer 220. The second GaN epitaxial layer 310, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 410 coupled to the second GaN epitaxial layer 310. The third GaN epitaxial layer 410 may have …
FIG. 5, portions of the third GaN epitaxial layer 410, and the second GaN epitaxial layer 310 are removed to expose sidewalls 513 of the second GaN epitaxial …
FIG. 6 illustrates how masking materia l 610 can be formed on remaining portion(s) of the third GaN epitaxial layer 410. In this embodiment, this masking …
FIGS. 7-8, illustrate a selective regrowth process used to form a fourth GaN epitaxial 25 layer 710 and a fifth GaN epitaxial layer 810. These epitaxial layers …
FIG. 9 illustrates the formation of a metal structure 910 below the GaN substrate 210. The metal structure 910 can be one or more layers of Ohmic metal that …
FIG. 10. Here, however, a third GaN epitaxial layer 1310 10 can comprise a more heavily-doped epitaxial layer than the corresponding third GaN epitaxial layer …
FIG. 11 shows the formation of a metal structure 1110 on the exposed surfaces 417, 717, 817 (shown in
FIG. 12 is a flowchart illustrating a method of fabricating a vertical superjunction diode according to one embodiment; 5 [0011]
FIGS. 13-15 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction junction field-effect transistor (JFET) according to …
FIG. 14 illustrates the formation of the source contacts 1410 of the vertical superjunction JFET. The source contacts 1410 can comprise one or more metal …
FIG. 16 is a simplified flowchart illustrating a method of fabricating a vertical superjunction JFET according to another embodiment of the present invention; …
FIG. 17 is a schematic drawing illustrating a simplified circuit implementation of a vertical superjunction JFET. [0014] In the appended figures, similar …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical superjunction device, the method comp ri sing: providing a III -nitride substrate of a first conductivity type; forming a first I II -nitride epitaxial layer of the first conductivity type coupled to the I II -nitride substrate; forming a second I II -nitride epitaxial layer coupled to the first I II -nitride epitaxial layer; forming a third I II -nitride epitaxial layer of the first conductivity type coupled to the second I II -nitride epitaxial layer; removing a portion of the third I II -nitride epitaxial layer and a portion of the second I II -nitride epitaxial layer to expose a sidewall of the second I II -nitride epitaxial layer and an exposed surface of the first I II-nitride epitaxial layer; forming a masking material coupled to a surface of a remaining portion of the third I II -nitride epitaxial layer; forming a fourth I II -nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second I II -nitride epitaxial layer and the exposed surface of the first I II -nitride epitaxial layer; forming a fifth I II -nitride epitaxial layer of a second conductivity type coupled to the fourth I II -nitride epitaxial layer; removing at least a portion of the masking material to expose: the surface of the remaining portion of the third I II-nitride epitaxial layer, a surface of the fourth I II -nitride epitaxial layer, and a surface of the fifth I II -nitride epitaxial layer; and forming one or more insulating structures coupled to the fifth I II-nitride epitaxial layer.
The method of claim 1 f u rther comprising forming a metal structure coupled to: at least one of the one or more insulating structures; 20 Kilpatrick Townsend 66346116 1 the exposed surface of the remaining portion of the third I II -nitride epitaxial layer; the exposed surface of the fourth I II -nitride epitaxial layer; and the exposed surface of the fifth I II -nitride epitaxial layer.
The method of claim 1 wherein forming at least one of the fourth III- nitride epitaxial layer or the fifth I II -nitride epitaxial layer comprises an epitaxial regrowth process.
The method of claim 1 f u rther comprising forming a metal structure coupled to the I II -nitride substrate, wherein the metal structure forms an ohmic electrical contact with the I II -nitride substrate.
The method of claim 1 wherein the second I II -nitride epitaxial layer is of the second conductivity type.
The method of claim 1 wherein the second I II -nitride epitaxial layer has intrinsic conductivity.
The method of claim 1 f u rther comprising: forming a first metal structure coupled to the exposed surface of the remaining portion of the third I II -nitride epitaxial layer, wherein the first metal structure forms a first ohmic contact with the exposed surface of the remaining portion of the third I II -nitride epitaxial layer; and forming a second metal structure coupled to: at least one of the one or more insulating structures; and the fifth I II -nitride epitaxial layer, wherein the second metal structure forms a second ohmic contact with the surface of the fifth I II -nitride epitaxial layer.
The method of claim 1 wherein the fourth I II epitaxial layer are substantially charge balanced.
The method of claim 1 wherein the first conductivity at least one of silicon or oxygen. 21 Kilpatrick -nitride epitaxial layer and the fifth I II -nitride type is n-type having a dopant including Townsend 66346116 1
Layer stacks claimed or described, ordered top of device to substrate.
vertical superjunction JFET/GaN vertical superjunction device
Materials described outside the worked examples.
III-nitride substrate of first conductivity type
first III-nitride epitaxial layer of first conductivity type
second III-nitride epitaxial layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 13-15 are simplified cross-sectional diagrams illustrating the fabrication of a vertical superjunction junction field-effect transistor (JFET) according to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
vertical superjunction gate field-effect transistor (JFET)
fourth III-nitride epitaxial layer of first conductivity type
fifth III-nitride epitaxial layer of second conductivity type
third III-nitride epitaxial layer of first conductivity type
metal structure
GaN (gallium nitride)
GaN
masking material
insulating/dielectric structures
vertical superjunction gate field-effect transistor (JFET)
fourth III-nitride epitaxial layer of first conductivity type
fifth III-nitride epitaxial layer of second conductivity type
third III-nitride epitaxial layer of first conductivity type
metal structure
GaN (gallium nitride)
GaN
masking material
insulating/dielectric structures
vertical superjunction gate field-effect transistor (JFET)
fourth III-nitride epitaxial layer of first conductivity type
fifth III-nitride epitaxial layer of second conductivity type
third III-nitride epitaxial layer of first conductivity type
metal structure
GaN (gallium nitride)
GaN
masking material
insulating/dielectric structures
vertical superjunction gate field-effect transistor (JFET)
fourth III-nitride epitaxial layer of first conductivity type
fifth III-nitride epitaxial layer of second conductivity type
third III-nitride epitaxial layer of first conductivity type
metal structure
GaN (gallium nitride)
GaN
masking material
insulating/dielectric structures