Patent
Atlas literature
Patent
US 12,336,268 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1E illustrate cross-sectional views representing various operations in a method of fabricating differing aspect ratio GaN islands in trenches in a …
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 45 multi-gate technology, in accordance with …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8B illustrate cross-sectional views representing various operations in a method of fabricating a GaN/Si device foundation structure, in accordance …
FIGS. 9A and 9B illustrate cross-sectional views along a 60 fin cut and a gate cut respectfully, in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure. B₂
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
FIG. 50 9A). With reference to the GaN portions of the devices of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; 10 a first trench in the substrate, the first trench having a first width; a second trench in the substrate, the second trench having a second width less than the first width; a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets below the top surface of the substrate; a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets below the top surface of the substrate; and 20 a hardmask material adjacent to the first corner facets and the second corner facets.
The integrated circuit structure of claim 1, wherein the hardmask material comprises silicon and nitrogen.
The integrated circuit structure of claim 1, wherein the first island has a top surface co-planar with the top surface of the substrate, and wherein the second island has a top surface co-planar with the top surface of the substrate.
The integrated circuit structure of claim 1, further comprising 30 a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A computing device, comprising: a board; and 40 a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width; a second trench in the substrate, the second trench having a second width less than the first width; a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets below the top surface of the substrate; a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets below the top surface of the substrate; and B₂ a hardmask material adjacent to the first corner facets and the second corner facets.
The computing device of claim 5, further comprising: a memory coupled to the board.
The computing device of claim 5, further comprising: a communication chip coupled to the board.
The computing device of claim 5, further comprising: a camera coupled to the board.
The computing device of claim 5, wherein the compo-nent is a packaged integrated circuit die.
An integrated circuit structure, comprising: a fin, the fin comprising gallium and nitrogen; a nanowire comprising silicon, the nanowire vertically over the fin; a gate structure around the nanowire and over the fin, the gate structure comprising an N-type gate electrode layer over the fin, and the gate structure comprising a P-type gate electrode layer around the nanowire.
The integrated circuit structure of claim 10, wherein the gate structure includes a conductive gate fill material continuous between the N-type gate electrode layer and the P-type gate electrode layer.
The integrated circuit structure of claim 10, wherein the gate structure includes a conductive gate fill material non-continuous between the N-type gate electrode layer and the P-type gate electrode layer.
The integrated circuit structure of claim 10, further comprising an isolation layer between the nanowire and the fin.
The integrated circuit structure of claim 10, wherein there is no isolation layer between the nanowire and the fin.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a fin, the fin comprising gallium and nitrogen; a nanowire comprising silicon, the nanowire vertically over the fin; a gate structure around the nanowire and over the fin, the gate structure comprising an N-type gate electrode layer over the fin, and the gate structure comprising a P-type gate electrode layer around the nanowire.
The computing device of claim 15, further compris-ing: a memory coupled to the board.
The computing device of claim 15, further compris-ing: a communication chip coupled to the board.
The computing device of claim 15, further compris-ing: a camera coupled to the board.
The computing device of claim 15, wherein the component is a packaged integrated circuit die. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN island integrated circuit structure with dual-width trenches
GaN fin/Si nanowire gate-all-around integrated circuit structure
Materials described outside the worked examples.
silicon substrate
Si
gallium nitride island/fin
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
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Patent
Atlas literature
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US 12,336,268 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1E illustrate cross-sectional views representing various operations in a method of fabricating differing aspect ratio GaN islands in trenches in a …
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 45 multi-gate technology, in accordance with …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8B illustrate cross-sectional views representing various operations in a method of fabricating a GaN/Si device foundation structure, in accordance …
FIGS. 9A and 9B illustrate cross-sectional views along a 60 fin cut and a gate cut respectfully, in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure. B₂
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
FIG. 50 9A). With reference to the GaN portions of the devices of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; 10 a first trench in the substrate, the first trench having a first width; a second trench in the substrate, the second trench having a second width less than the first width; a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets below the top surface of the substrate; a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets below the top surface of the substrate; and 20 a hardmask material adjacent to the first corner facets and the second corner facets.
The integrated circuit structure of claim 1, wherein the hardmask material comprises silicon and nitrogen.
The integrated circuit structure of claim 1, wherein the first island has a top surface co-planar with the top surface of the substrate, and wherein the second island has a top surface co-planar with the top surface of the substrate.
The integrated circuit structure of claim 1, further comprising 30 a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A computing device, comprising: a board; and 40 a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width; a second trench in the substrate, the second trench having a second width less than the first width; a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets below the top surface of the substrate; a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets below the top surface of the substrate; and B₂ a hardmask material adjacent to the first corner facets and the second corner facets.
The computing device of claim 5, further comprising: a memory coupled to the board.
The computing device of claim 5, further comprising: a communication chip coupled to the board.
The computing device of claim 5, further comprising: a camera coupled to the board.
The computing device of claim 5, wherein the compo-nent is a packaged integrated circuit die.
An integrated circuit structure, comprising: a fin, the fin comprising gallium and nitrogen; a nanowire comprising silicon, the nanowire vertically over the fin; a gate structure around the nanowire and over the fin, the gate structure comprising an N-type gate electrode layer over the fin, and the gate structure comprising a P-type gate electrode layer around the nanowire.
The integrated circuit structure of claim 10, wherein the gate structure includes a conductive gate fill material continuous between the N-type gate electrode layer and the P-type gate electrode layer.
The integrated circuit structure of claim 10, wherein the gate structure includes a conductive gate fill material non-continuous between the N-type gate electrode layer and the P-type gate electrode layer.
The integrated circuit structure of claim 10, further comprising an isolation layer between the nanowire and the fin.
The integrated circuit structure of claim 10, wherein there is no isolation layer between the nanowire and the fin.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a fin, the fin comprising gallium and nitrogen; a nanowire comprising silicon, the nanowire vertically over the fin; a gate structure around the nanowire and over the fin, the gate structure comprising an N-type gate electrode layer over the fin, and the gate structure comprising a P-type gate electrode layer around the nanowire.
The computing device of claim 15, further compris-ing: a memory coupled to the board.
The computing device of claim 15, further compris-ing: a communication chip coupled to the board.
The computing device of claim 15, further compris-ing: a camera coupled to the board.
The computing device of claim 15, wherein the component is a packaged integrated circuit die. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN island integrated circuit structure with dual-width trenches
GaN fin/Si nanowire gate-all-around integrated circuit structure
Materials described outside the worked examples.
silicon substrate
Si
gallium nitride island/fin
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,336,268 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1E illustrate cross-sectional views representing various operations in a method of fabricating differing aspect ratio GaN islands in trenches in a …
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 45 multi-gate technology, in accordance with …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8B illustrate cross-sectional views representing various operations in a method of fabricating a GaN/Si device foundation structure, in accordance …
FIGS. 9A and 9B illustrate cross-sectional views along a 60 fin cut and a gate cut respectfully, in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure. B₂
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
FIG. 50 9A). With reference to the GaN portions of the devices of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; 10 a first trench in the substrate, the first trench having a first width; a second trench in the substrate, the second trench having a second width less than the first width; a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets below the top surface of the substrate; a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets below the top surface of the substrate; and 20 a hardmask material adjacent to the first corner facets and the second corner facets.
The integrated circuit structure of claim 1, wherein the hardmask material comprises silicon and nitrogen.
The integrated circuit structure of claim 1, wherein the first island has a top surface co-planar with the top surface of the substrate, and wherein the second island has a top surface co-planar with the top surface of the substrate.
The integrated circuit structure of claim 1, further comprising 30 a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A computing device, comprising: a board; and 40 a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width; a second trench in the substrate, the second trench having a second width less than the first width; a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets below the top surface of the substrate; a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets below the top surface of the substrate; and B₂ a hardmask material adjacent to the first corner facets and the second corner facets.
The computing device of claim 5, further comprising: a memory coupled to the board.
The computing device of claim 5, further comprising: a communication chip coupled to the board.
The computing device of claim 5, further comprising: a camera coupled to the board.
The computing device of claim 5, wherein the compo-nent is a packaged integrated circuit die.
An integrated circuit structure, comprising: a fin, the fin comprising gallium and nitrogen; a nanowire comprising silicon, the nanowire vertically over the fin; a gate structure around the nanowire and over the fin, the gate structure comprising an N-type gate electrode layer over the fin, and the gate structure comprising a P-type gate electrode layer around the nanowire.
The integrated circuit structure of claim 10, wherein the gate structure includes a conductive gate fill material continuous between the N-type gate electrode layer and the P-type gate electrode layer.
The integrated circuit structure of claim 10, wherein the gate structure includes a conductive gate fill material non-continuous between the N-type gate electrode layer and the P-type gate electrode layer.
The integrated circuit structure of claim 10, further comprising an isolation layer between the nanowire and the fin.
The integrated circuit structure of claim 10, wherein there is no isolation layer between the nanowire and the fin.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a fin, the fin comprising gallium and nitrogen; a nanowire comprising silicon, the nanowire vertically over the fin; a gate structure around the nanowire and over the fin, the gate structure comprising an N-type gate electrode layer over the fin, and the gate structure comprising a P-type gate electrode layer around the nanowire.
The computing device of claim 15, further compris-ing: a memory coupled to the board.
The computing device of claim 15, further compris-ing: a communication chip coupled to the board.
The computing device of claim 15, further compris-ing: a camera coupled to the board.
The computing device of claim 15, wherein the component is a packaged integrated circuit die. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN island integrated circuit structure with dual-width trenches
GaN fin/Si nanowire gate-all-around integrated circuit structure
Materials described outside the worked examples.
silicon substrate
Si
gallium nitride island/fin
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,336,268 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1A-1E illustrate cross-sectional views representing various operations in a method of fabricating differing aspect ratio GaN islands in trenches in a …
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 45 multi-gate technology, in accordance with …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8B illustrate cross-sectional views representing various operations in a method of fabricating a GaN/Si device foundation structure, in accordance …
FIGS. 9A and 9B illustrate cross-sectional views along a 60 fin cut and a gate cut respectfully, in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure. B₂
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
FIG. 50 9A). With reference to the GaN portions of the devices of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; 10 a first trench in the substrate, the first trench having a first width; a second trench in the substrate, the second trench having a second width less than the first width; a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets below the top surface of the substrate; a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets below the top surface of the substrate; and 20 a hardmask material adjacent to the first corner facets and the second corner facets.
The integrated circuit structure of claim 1, wherein the hardmask material comprises silicon and nitrogen.
The integrated circuit structure of claim 1, wherein the first island has a top surface co-planar with the top surface of the substrate, and wherein the second island has a top surface co-planar with the top surface of the substrate.
The integrated circuit structure of claim 1, further comprising 30 a plurality of gate structures over the first island or the second island; a source region on a first side of the plurality of gate structures; a drain region on a second side of the plurality of gate structures, the second side opposite the first side; and a drain field plate above the drain region wherein the drain field plate is coupled to the source region.
A computing device, comprising: a board; and 40 a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a substrate comprising silicon, the substrate having a top surface; a first trench in the substrate, the first trench having a first width; a second trench in the substrate, the second trench having a second width less than the first width; a first island in the first trench, the first island comprising gallium and nitrogen and having first corner facets below the top surface of the substrate; a second island in the second trench, the second island comprising gallium and nitrogen and having second corner facets below the top surface of the substrate; and B₂ a hardmask material adjacent to the first corner facets and the second corner facets.
The computing device of claim 5, further comprising: a memory coupled to the board.
The computing device of claim 5, further comprising: a communication chip coupled to the board.
The computing device of claim 5, further comprising: a camera coupled to the board.
The computing device of claim 5, wherein the compo-nent is a packaged integrated circuit die.
An integrated circuit structure, comprising: a fin, the fin comprising gallium and nitrogen; a nanowire comprising silicon, the nanowire vertically over the fin; a gate structure around the nanowire and over the fin, the gate structure comprising an N-type gate electrode layer over the fin, and the gate structure comprising a P-type gate electrode layer around the nanowire.
The integrated circuit structure of claim 10, wherein the gate structure includes a conductive gate fill material continuous between the N-type gate electrode layer and the P-type gate electrode layer.
The integrated circuit structure of claim 10, wherein the gate structure includes a conductive gate fill material non-continuous between the N-type gate electrode layer and the P-type gate electrode layer.
The integrated circuit structure of claim 10, further comprising an isolation layer between the nanowire and the fin.
The integrated circuit structure of claim 10, wherein there is no isolation layer between the nanowire and the fin.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: a fin, the fin comprising gallium and nitrogen; a nanowire comprising silicon, the nanowire vertically over the fin; a gate structure around the nanowire and over the fin, the gate structure comprising an N-type gate electrode layer over the fin, and the gate structure comprising a P-type gate electrode layer around the nanowire.
The computing device of claim 15, further compris-ing: a memory coupled to the board.
The computing device of claim 15, further compris-ing: a communication chip coupled to the board.
The computing device of claim 15, further compris-ing: a camera coupled to the board.
The computing device of claim 15, wherein the component is a packaged integrated circuit die. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN island integrated circuit structure with dual-width trenches
GaN fin/Si nanowire gate-all-around integrated circuit structure
Materials described outside the worked examples.
silicon substrate
Si
gallium nitride island/fin
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 35 having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Related documents with shared materials, methods, properties, or citations.
hardmask material (silicon nitride)
SiN
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
Thickness | 200–25000 nm | — |
Thickness | 50–1000 nm | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
hardmask material (silicon nitride)
SiN
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
Thickness | 200–25000 nm | — |
Thickness | 50–1000 nm | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
hardmask material (silicon nitride)
SiN
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
Thickness | 200–25000 nm | — |
Thickness | 50–1000 nm | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
hardmask material (silicon nitride)
SiN
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
Thickness | 200–25000 nm | — |
Thickness | 50–1000 nm | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
