MULTI-LAYER SILICON/GALLIUM NITRIDE SEMICONDUCTOR

Sansaptak W. DASGUPTA

Patent

Atlas literature

Patent

US 10,763,248

MULTI-LAYER SILICON/GALLIUM NITRIDE SEMICONDUCTOR

Sansaptak W. DASGUPTA, MARKO RADOSAVLJEVIC, HAN WUI THEN, RAVI PILLARISETTY et al.

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 is a cross-section of an example multi-layer silicon/gallium nitride integrated circuit formed by the layer transfer of a full-size, completed gallium …

FIG. 2

FIG. 2 is a cross-section of another example multi-layer silicon/gallium nitride integrated circuit formed by the layer transfer of a full-size, completed …

FIG. 3

FIG. 3 is a schematic diagram of an example multi-layer silicon/gallium nitride integrated circuit fabrication system that includes the layer transfer of a …

FIG. 4

FIG. 4 is a schematic diagram of another example multi-layer silicon/gallium nitride integrated circuit fabrication system that includes the layer transfer of …

FIG. 5

FIG. 5 is a high-level ﬂow diagram of an example multi-layer silicon/gallium nitride integrated circuit fabrication method, in accordance with at least one …

FIG. 6

FIG. 6 is a high-level ﬂow diagram of an example multi-layer silicon/gallium nitride integrated circuit fabrication method that includes the deposition of an …

FIG. 7

FIG. 7 is a high-level ﬂow diagram of example gallium nitride growth method that includes growing a gallium nitride wafer on a silicon substrate, in accordance …

FIG. 8

FIG. 8 is a high-level ﬂow diagram of an example integrated silicon/gallium nitride integrated circuit fabrication method, in accordance with at least one …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

7 independent · 19 dependent

1
Independent
25 Canceled
25
Independent
Canceled
26
IndependentGaNSicompound semiconductor device with thru-GaN vias
A compound semiconductor device; comprising: a completed silicon layer that includes a number of silicon dies, each of the silicon dies including at least one silicon integrated circuit; a completed gallium nitride (GaN) layer that includes a number of GaN dies, each of the GaN dies including at least one GaN integrated circuit, the completed GaN layer bonded, via layer transfer, to the completed silicon layer such that each of the number of silicon dies lies proximate a respective one of the number of GaN dies; and an interconnect layer deposited on the completed GaN layer, the interconnect layer including a number of thru-GaN vias that conductively couple the at least one GaN integrated circuit on each GaN die with the at least one silicon integrated circuit on each silicon die. New
1. 27
  Dependent← claim 26GaNcompound semiconductor device with thru-GaN vias
  The compound semiconductor device of claim 26 wherein the GaN dies have a deﬁned polarization. New
2. 29
  Dependent← claim 26GaNSicompound semiconductor device with thru-GaN vias
  The compound semiconductor device of any of claim 26 wherein the at least one GaN integrated circuit comprises a power management integrated circuit (PMIC) and the at least one silicon integrated circuit comprises a complementary metal oxide semiconductor (CMOS) PMIC controller. New
30
IndependentGaNSimulti-layer semiconductor package
A compound semiconductor, comprising a completed silicon layer that includes a number of silicon dies; a completed gallium nitride (GaN) layer that includes a number of GaN dies, the completed GaN layer bonded, via layer transfer, to the completed silicon layer such that each of the number of silicon dies lies proximate a respective one of the number of GaN dies; and a number of interconnections conductively coupling each of the number of silicon dies to a respective one of the GaN die to provide a multi-layer semiconductor package. New
1. 31
  Dependent← claim 30GaNmulti-layer semiconductor package
  The multilayer semiconductor of claim 30 wherein the GaN dies have a deﬁned polarization. New
2. 33
  Dependent← claim 30GaNmulti-layer semiconductor package
  The multilayer semiconductor of claim 30 wherein the number of interconnections comprises an interconnect layer patterned onto the completed GaN layer. New
34
IndependentGaNSi
A method of forming a compound semiconductor, the method comprising: bonding a completed gallium nitride (GaN) layer having a ﬁrst diameter and including a number of completed GaN dies to a completed silicon layer having a second diameter and including a number of completed silicon dies; and conductively coupling at least one integrated circuit on each of the number of GaN dies to New
1. 35
  Dependent← claim 34GaNSi
  The method of claim 34 wherein bonding a completed gallium nitride (GaN) layer to a completed silicon layer comprises: layer transferring the completed GaN layer to the completed silicon layer. New
2. 36
  Dependent← claim 34GaNSi
  The method of claim 34 wherein bonding a completed gallium nitride (GaN) layer having a ﬁrst diameter and including a number of completed GaN dies to a completed silicon layer having a second diameter comprises: bonding a completed gallium nitride (GaN) layer having a ﬁrst diameter and including a number of completed GaN dies to a completed silicon layer having a second diameter approximately equal to the ﬁrst diameter. New
3. 37
  Dependent← claim 34GaNSi
  The method of claim 34, further comprising: growing a GaN wafer on a silicon substrate; disposing a number of devices in, on, or about the GaN wafer; and patterning a number of conductors on the GaN wafer to conductively couple at least some of the number of devices to provide the completed GaN layer. New
42
IndependentGaNSi
The method of claim 44 wherein conductively coupling at least one integrated circuit on each of the number of GaN dies to at least one integrated circuit on each of the completed silicon dies comprises: patterning one or more conductive interconnect layers on the exposed portion of the surface of the completed GaN layer. New
49
IndependentGaNSi
A system for forming a compound semiconductor, the system comprising: a means for bonding a completed gallium nitride (GaN) layer including a number of completed GaN dies to a completed silicon layer including a number of completed silicon dies; and a means for conductively coupling at least one integrated circuit on each of the number of GaN dies to at least one integrated circuit on each of the completed silicon dies. New

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

compound semiconductor device with thru-GaN vias

interconnect layer with thru-GaN viasinterconnect layer with thru-GaN vias

GaNcompleted GaN PMIC layer (bonded via layer transfer)

Sisilicon CMOS layer

multi-layer semiconductor package

interconnections coupling silicon and GaN diesinterconnections coupling silicon and GaN dies

GaNcompleted GaN layer with GaN dies (bonded via layer transfer)

Materials

Materials described outside the worked examples.

gallium nitride

GaN

Power Management Semiconductor Layer/PMIC Die Material

silicon

CMOS Control Circuit Semiconductor Layer/Silicon Die Material

Process steps

Additional fabrication and treatment steps described in the patent.

Layer Transfer Bonding

Step 1

Process details

description:Full-size completed GaN wafer (e.g., 300mm or 450mm) layer transferred and bonded to full-size completed silicon wafer; silicon substrate subsequently removed to expose GaN layer surface.

Materials:GaN

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
Thickness	25–450 mm	—

Why these are connected

Related documents with shared materials, methods, properties, or citations.

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