Patent
US 11,152,313USING THREADING DISLOCATIONS IN GaN/Si SYSTEMS TO GENERATE PHYSICALLY UNCLONABLE FUNCTIONS
Hiu Yung Wong, Rimvydas Mickevicius
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,152,313Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 7 illustrates various processes performed in the design, verification and fabrication of an item of manufacture such as an integrated circuit using …
FIGS. 8A, 8B and 8C are simplified block diagrams of a computer system suitable for use with embodiments of the technology, as well as circuit design and …
FIG. 9. Each FPGA can include one or more FPGA interfaces through which the FPGA is connected to other FPGAs of the emulator (and potentially other emulator …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Withdrawn-Currently Amended) A physically unclonable function (PUF) device comprising: a substrate having a crystalline top surface; a stack of at rystalline la y ers on the substrate crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and a lowest crystalline layer, the stack of crystalline layers including a plurality of threading dislocations extending from the substrate top surface up through the stack to a top surface of the stack of crystalline layers; a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, each of the diodes having upper diode pole material formed on the top surface of the stack and forming a diode junction at the top surface of the stack with a diode pole region in the stack below the upper diode pole material; and interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation, wherein the uppermost crystalline la y er of the stack is a first piezoelectric material formed on a second la y er of the stack, the second la y er of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a hetero j unction at an interface between the uppermost and second la y ers of the stack. Currently amended
2-16 Canceled
Canceled
A method for developing a physically unclonable function (PUF) for an integrated circuit device, comprising: epitaxially growing a stack of crystalline la y ers on a substrate having a crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and having a lowest crystalline layer which has a lattice constant that differs from that of the crystalline top surface of the substrate, the stack of cry stalline layers including a plurality of threading dislocations extending from the substrate top surface through the stack to a top surface of the stack of crystalline layers; forming a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, by forming upper diode pole material for each of the diodes on the top surface of the stack of crystalline layers, each diode forming a diode junction at the top surface of the stack with a diode pole region in the stack and below the upper diode pole material; and forming interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation, and wherein the uppermost crystalline la y er of the stack is a first piezoelectric material formed on a second la y er of the stack, the second la y er of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a hetero j unction at an interface between the uppermost and second la y ers of the stack. Currently amended
The method of claim 17, wherein, the diode pole regions of the diodes formed in the forming of a plurality of diodes are in the uppermost crystalline layer of the stack. Currently amended
The method of claim 17, wherein the second layer of the stack is GaN and the uppermost crystalline layer of the stack is an alloy including GaN. Original
The method of claim 17, wherein the uppermost crystalline layer of the stack is an alloy of GaN having a larger bandgap than GaN, and is formed on [[a]]the second layer of the stack being GaN, so as to form [[a]]the heterojunction at the interface between the uppermost and second layers of the stack, the method further including forming an integrated circuit having a plurality of transistors in the stack. Currently amended
The method of claim 17, wherein the uppermost crystalline layer of the stack is an N-type semiconductor material, and wherein the upper pole material for at least one of the diodes is a P-type semiconductor material and the diode junction is a P-N junction. Original
The method of claim 17, wherein the uppermost crystalline layer of the stack is a P-type semiconductor material, and wherein the upper pole material for at least one of the diodes is an N-type semiconductor material and the diode junction is a P-N junction. Currently amended
The method of claim 17, wherein [[the]]an anode material for at least one of the diodes is a metal and the diode junction is a Schottky junction. Currently amended
[[The]]A method, for developing a physically unclonable function (PUF) for an integrated circuit device, comprising: epitaxially growing a stack of crystalline la y ers on a substrate having a crystalline top surface, the stack of crystalline la y ers having an uppermost crystalline la y er and having a lowest crystalline la y er which has a lattice constant that differs from that of the crystalline top surface of the substrate, the stack of crystalline la y ers including a plurality of threading dislocations extending from the substrate top surface through the stack to a top surface of the stack of crystalline la y ers; forming a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, by forming upper diode pole material for each of the diodes on the top surface of the stack of crystalline la y ers, each diode forming a diode j unction at the top surface of the stack with a diode pole region in the stack and below the upper diode pole material; forming interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation; forming a first set of at least one first conductor each connected to the upper diode pole material of a respective one of a first plurality of the diodes; forming a second set of at least one second conductor each connected to the diode pole region of a respective one of a second set of at least one of the diodes, each of the diodes connected to both one of the first conductors and one of the second conductors; and connecting the first and second conductors to the interrogation/decoding circuitry. Currently amended
The method of claim 24, wherein the uppermost crystalline layer of the stack is a first piezoelectric material formed on a second layer of the stack, the second layer of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a heterojunction at [[the]]an interface between the uppermost and second layers of the stack; and wherein the second conductors include a 2DEG layer or a 2DHG layer below the heterojunction. Currently amended
The method of claim 24, wherein none of the diodes is connected to more than one of the first conductors nor more than one of the second conductors, the combination of one of the first conductors and one of the second conductors uniquely identifying a single one of the diodes. Original
29-36 Canceled
Canceled
A physically unclonable function (PUF) device comprising: a substrate having a crystalline top surface; a stack of at crystalline layers on the substrate crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and a lowest crystalline layer, the stack of crystalline layers including a plurality of threading dislocations extending from the substrate top surface up through the stack to a top surface of the stack of crystalline layers; a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, each of the diodes having upper diode pole material formed on the top surface of the stack and forming a diode junction at the top surface of the stack with a diode pole region in the stack below the upper diode pole material; interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation; a first set of at least one first conductor each connected to the upper diode pole material of a respective one of a first plurality of the diodes; and a second set of at least one second conductor each connected to the diode pole region of a respective one of a second set of at least one of the diodes, each of the diodes connected to both one of the first conductors and one of the second conductors, wherein the first and second conductors are connected to the interrogation/decoding circuitry. New
Layer stacks claimed or described, ordered top of device to substrate.
PUF device with diode array (heterojunction stack)
PUF method device-epitaxially grown stack with diodes
Materials described outside the worked examples.
first piezoelectric material (uppermost crystalline layer)
second piezoelectric material (second layer of stack)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,152,313Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 7 illustrates various processes performed in the design, verification and fabrication of an item of manufacture such as an integrated circuit using …
FIGS. 8A, 8B and 8C are simplified block diagrams of a computer system suitable for use with embodiments of the technology, as well as circuit design and …
FIG. 9. Each FPGA can include one or more FPGA interfaces through which the FPGA is connected to other FPGAs of the emulator (and potentially other emulator …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Withdrawn-Currently Amended) A physically unclonable function (PUF) device comprising: a substrate having a crystalline top surface; a stack of at rystalline la y ers on the substrate crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and a lowest crystalline layer, the stack of crystalline layers including a plurality of threading dislocations extending from the substrate top surface up through the stack to a top surface of the stack of crystalline layers; a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, each of the diodes having upper diode pole material formed on the top surface of the stack and forming a diode junction at the top surface of the stack with a diode pole region in the stack below the upper diode pole material; and interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation, wherein the uppermost crystalline la y er of the stack is a first piezoelectric material formed on a second la y er of the stack, the second la y er of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a hetero j unction at an interface between the uppermost and second la y ers of the stack. Currently amended
2-16 Canceled
Canceled
A method for developing a physically unclonable function (PUF) for an integrated circuit device, comprising: epitaxially growing a stack of crystalline la y ers on a substrate having a crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and having a lowest crystalline layer which has a lattice constant that differs from that of the crystalline top surface of the substrate, the stack of cry stalline layers including a plurality of threading dislocations extending from the substrate top surface through the stack to a top surface of the stack of crystalline layers; forming a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, by forming upper diode pole material for each of the diodes on the top surface of the stack of crystalline layers, each diode forming a diode junction at the top surface of the stack with a diode pole region in the stack and below the upper diode pole material; and forming interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation, and wherein the uppermost crystalline la y er of the stack is a first piezoelectric material formed on a second la y er of the stack, the second la y er of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a hetero j unction at an interface between the uppermost and second la y ers of the stack. Currently amended
The method of claim 17, wherein, the diode pole regions of the diodes formed in the forming of a plurality of diodes are in the uppermost crystalline layer of the stack. Currently amended
The method of claim 17, wherein the second layer of the stack is GaN and the uppermost crystalline layer of the stack is an alloy including GaN. Original
The method of claim 17, wherein the uppermost crystalline layer of the stack is an alloy of GaN having a larger bandgap than GaN, and is formed on [[a]]the second layer of the stack being GaN, so as to form [[a]]the heterojunction at the interface between the uppermost and second layers of the stack, the method further including forming an integrated circuit having a plurality of transistors in the stack. Currently amended
The method of claim 17, wherein the uppermost crystalline layer of the stack is an N-type semiconductor material, and wherein the upper pole material for at least one of the diodes is a P-type semiconductor material and the diode junction is a P-N junction. Original
The method of claim 17, wherein the uppermost crystalline layer of the stack is a P-type semiconductor material, and wherein the upper pole material for at least one of the diodes is an N-type semiconductor material and the diode junction is a P-N junction. Currently amended
The method of claim 17, wherein [[the]]an anode material for at least one of the diodes is a metal and the diode junction is a Schottky junction. Currently amended
[[The]]A method, for developing a physically unclonable function (PUF) for an integrated circuit device, comprising: epitaxially growing a stack of crystalline la y ers on a substrate having a crystalline top surface, the stack of crystalline la y ers having an uppermost crystalline la y er and having a lowest crystalline la y er which has a lattice constant that differs from that of the crystalline top surface of the substrate, the stack of crystalline la y ers including a plurality of threading dislocations extending from the substrate top surface through the stack to a top surface of the stack of crystalline la y ers; forming a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, by forming upper diode pole material for each of the diodes on the top surface of the stack of crystalline la y ers, each diode forming a diode j unction at the top surface of the stack with a diode pole region in the stack and below the upper diode pole material; forming interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation; forming a first set of at least one first conductor each connected to the upper diode pole material of a respective one of a first plurality of the diodes; forming a second set of at least one second conductor each connected to the diode pole region of a respective one of a second set of at least one of the diodes, each of the diodes connected to both one of the first conductors and one of the second conductors; and connecting the first and second conductors to the interrogation/decoding circuitry. Currently amended
The method of claim 24, wherein the uppermost crystalline layer of the stack is a first piezoelectric material formed on a second layer of the stack, the second layer of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a heterojunction at [[the]]an interface between the uppermost and second layers of the stack; and wherein the second conductors include a 2DEG layer or a 2DHG layer below the heterojunction. Currently amended
The method of claim 24, wherein none of the diodes is connected to more than one of the first conductors nor more than one of the second conductors, the combination of one of the first conductors and one of the second conductors uniquely identifying a single one of the diodes. Original
29-36 Canceled
Canceled
A physically unclonable function (PUF) device comprising: a substrate having a crystalline top surface; a stack of at crystalline layers on the substrate crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and a lowest crystalline layer, the stack of crystalline layers including a plurality of threading dislocations extending from the substrate top surface up through the stack to a top surface of the stack of crystalline layers; a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, each of the diodes having upper diode pole material formed on the top surface of the stack and forming a diode junction at the top surface of the stack with a diode pole region in the stack below the upper diode pole material; interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation; a first set of at least one first conductor each connected to the upper diode pole material of a respective one of a first plurality of the diodes; and a second set of at least one second conductor each connected to the diode pole region of a respective one of a second set of at least one of the diodes, each of the diodes connected to both one of the first conductors and one of the second conductors, wherein the first and second conductors are connected to the interrogation/decoding circuitry. New
Layer stacks claimed or described, ordered top of device to substrate.
PUF device with diode array (heterojunction stack)
PUF method device-epitaxially grown stack with diodes
Materials described outside the worked examples.
first piezoelectric material (uppermost crystalline layer)
second piezoelectric material (second layer of stack)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,152,313Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 7 illustrates various processes performed in the design, verification and fabrication of an item of manufacture such as an integrated circuit using …
FIGS. 8A, 8B and 8C are simplified block diagrams of a computer system suitable for use with embodiments of the technology, as well as circuit design and …
FIG. 9. Each FPGA can include one or more FPGA interfaces through which the FPGA is connected to other FPGAs of the emulator (and potentially other emulator …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Withdrawn-Currently Amended) A physically unclonable function (PUF) device comprising: a substrate having a crystalline top surface; a stack of at rystalline la y ers on the substrate crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and a lowest crystalline layer, the stack of crystalline layers including a plurality of threading dislocations extending from the substrate top surface up through the stack to a top surface of the stack of crystalline layers; a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, each of the diodes having upper diode pole material formed on the top surface of the stack and forming a diode junction at the top surface of the stack with a diode pole region in the stack below the upper diode pole material; and interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation, wherein the uppermost crystalline la y er of the stack is a first piezoelectric material formed on a second la y er of the stack, the second la y er of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a hetero j unction at an interface between the uppermost and second la y ers of the stack. Currently amended
2-16 Canceled
Canceled
A method for developing a physically unclonable function (PUF) for an integrated circuit device, comprising: epitaxially growing a stack of crystalline la y ers on a substrate having a crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and having a lowest crystalline layer which has a lattice constant that differs from that of the crystalline top surface of the substrate, the stack of cry stalline layers including a plurality of threading dislocations extending from the substrate top surface through the stack to a top surface of the stack of crystalline layers; forming a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, by forming upper diode pole material for each of the diodes on the top surface of the stack of crystalline layers, each diode forming a diode junction at the top surface of the stack with a diode pole region in the stack and below the upper diode pole material; and forming interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation, and wherein the uppermost crystalline la y er of the stack is a first piezoelectric material formed on a second la y er of the stack, the second la y er of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a hetero j unction at an interface between the uppermost and second la y ers of the stack. Currently amended
The method of claim 17, wherein, the diode pole regions of the diodes formed in the forming of a plurality of diodes are in the uppermost crystalline layer of the stack. Currently amended
The method of claim 17, wherein the second layer of the stack is GaN and the uppermost crystalline layer of the stack is an alloy including GaN. Original
The method of claim 17, wherein the uppermost crystalline layer of the stack is an alloy of GaN having a larger bandgap than GaN, and is formed on [[a]]the second layer of the stack being GaN, so as to form [[a]]the heterojunction at the interface between the uppermost and second layers of the stack, the method further including forming an integrated circuit having a plurality of transistors in the stack. Currently amended
The method of claim 17, wherein the uppermost crystalline layer of the stack is an N-type semiconductor material, and wherein the upper pole material for at least one of the diodes is a P-type semiconductor material and the diode junction is a P-N junction. Original
The method of claim 17, wherein the uppermost crystalline layer of the stack is a P-type semiconductor material, and wherein the upper pole material for at least one of the diodes is an N-type semiconductor material and the diode junction is a P-N junction. Currently amended
The method of claim 17, wherein [[the]]an anode material for at least one of the diodes is a metal and the diode junction is a Schottky junction. Currently amended
[[The]]A method, for developing a physically unclonable function (PUF) for an integrated circuit device, comprising: epitaxially growing a stack of crystalline la y ers on a substrate having a crystalline top surface, the stack of crystalline la y ers having an uppermost crystalline la y er and having a lowest crystalline la y er which has a lattice constant that differs from that of the crystalline top surface of the substrate, the stack of crystalline la y ers including a plurality of threading dislocations extending from the substrate top surface through the stack to a top surface of the stack of crystalline la y ers; forming a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, by forming upper diode pole material for each of the diodes on the top surface of the stack of crystalline la y ers, each diode forming a diode j unction at the top surface of the stack with a diode pole region in the stack and below the upper diode pole material; forming interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation; forming a first set of at least one first conductor each connected to the upper diode pole material of a respective one of a first plurality of the diodes; forming a second set of at least one second conductor each connected to the diode pole region of a respective one of a second set of at least one of the diodes, each of the diodes connected to both one of the first conductors and one of the second conductors; and connecting the first and second conductors to the interrogation/decoding circuitry. Currently amended
The method of claim 24, wherein the uppermost crystalline layer of the stack is a first piezoelectric material formed on a second layer of the stack, the second layer of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a heterojunction at [[the]]an interface between the uppermost and second layers of the stack; and wherein the second conductors include a 2DEG layer or a 2DHG layer below the heterojunction. Currently amended
The method of claim 24, wherein none of the diodes is connected to more than one of the first conductors nor more than one of the second conductors, the combination of one of the first conductors and one of the second conductors uniquely identifying a single one of the diodes. Original
29-36 Canceled
Canceled
A physically unclonable function (PUF) device comprising: a substrate having a crystalline top surface; a stack of at crystalline layers on the substrate crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and a lowest crystalline layer, the stack of crystalline layers including a plurality of threading dislocations extending from the substrate top surface up through the stack to a top surface of the stack of crystalline layers; a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, each of the diodes having upper diode pole material formed on the top surface of the stack and forming a diode junction at the top surface of the stack with a diode pole region in the stack below the upper diode pole material; interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation; a first set of at least one first conductor each connected to the upper diode pole material of a respective one of a first plurality of the diodes; and a second set of at least one second conductor each connected to the diode pole region of a respective one of a second set of at least one of the diodes, each of the diodes connected to both one of the first conductors and one of the second conductors, wherein the first and second conductors are connected to the interrogation/decoding circuitry. New
Layer stacks claimed or described, ordered top of device to substrate.
PUF device with diode array (heterojunction stack)
PUF method device-epitaxially grown stack with diodes
Materials described outside the worked examples.
first piezoelectric material (uppermost crystalline layer)
second piezoelectric material (second layer of stack)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,152,313Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 7 illustrates various processes performed in the design, verification and fabrication of an item of manufacture such as an integrated circuit using …
FIGS. 8A, 8B and 8C are simplified block diagrams of a computer system suitable for use with embodiments of the technology, as well as circuit design and …
FIG. 9. Each FPGA can include one or more FPGA interfaces through which the FPGA is connected to other FPGAs of the emulator (and potentially other emulator …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Withdrawn-Currently Amended) A physically unclonable function (PUF) device comprising: a substrate having a crystalline top surface; a stack of at rystalline la y ers on the substrate crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and a lowest crystalline layer, the stack of crystalline layers including a plurality of threading dislocations extending from the substrate top surface up through the stack to a top surface of the stack of crystalline layers; a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, each of the diodes having upper diode pole material formed on the top surface of the stack and forming a diode junction at the top surface of the stack with a diode pole region in the stack below the upper diode pole material; and interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation, wherein the uppermost crystalline la y er of the stack is a first piezoelectric material formed on a second la y er of the stack, the second la y er of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a hetero j unction at an interface between the uppermost and second la y ers of the stack. Currently amended
2-16 Canceled
Canceled
A method for developing a physically unclonable function (PUF) for an integrated circuit device, comprising: epitaxially growing a stack of crystalline la y ers on a substrate having a crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and having a lowest crystalline layer which has a lattice constant that differs from that of the crystalline top surface of the substrate, the stack of cry stalline layers including a plurality of threading dislocations extending from the substrate top surface through the stack to a top surface of the stack of crystalline layers; forming a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, by forming upper diode pole material for each of the diodes on the top surface of the stack of crystalline layers, each diode forming a diode junction at the top surface of the stack with a diode pole region in the stack and below the upper diode pole material; and forming interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation, and wherein the uppermost crystalline la y er of the stack is a first piezoelectric material formed on a second la y er of the stack, the second la y er of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a hetero j unction at an interface between the uppermost and second la y ers of the stack. Currently amended
The method of claim 17, wherein, the diode pole regions of the diodes formed in the forming of a plurality of diodes are in the uppermost crystalline layer of the stack. Currently amended
The method of claim 17, wherein the second layer of the stack is GaN and the uppermost crystalline layer of the stack is an alloy including GaN. Original
The method of claim 17, wherein the uppermost crystalline layer of the stack is an alloy of GaN having a larger bandgap than GaN, and is formed on [[a]]the second layer of the stack being GaN, so as to form [[a]]the heterojunction at the interface between the uppermost and second layers of the stack, the method further including forming an integrated circuit having a plurality of transistors in the stack. Currently amended
The method of claim 17, wherein the uppermost crystalline layer of the stack is an N-type semiconductor material, and wherein the upper pole material for at least one of the diodes is a P-type semiconductor material and the diode junction is a P-N junction. Original
The method of claim 17, wherein the uppermost crystalline layer of the stack is a P-type semiconductor material, and wherein the upper pole material for at least one of the diodes is an N-type semiconductor material and the diode junction is a P-N junction. Currently amended
The method of claim 17, wherein [[the]]an anode material for at least one of the diodes is a metal and the diode junction is a Schottky junction. Currently amended
[[The]]A method, for developing a physically unclonable function (PUF) for an integrated circuit device, comprising: epitaxially growing a stack of crystalline la y ers on a substrate having a crystalline top surface, the stack of crystalline la y ers having an uppermost crystalline la y er and having a lowest crystalline la y er which has a lattice constant that differs from that of the crystalline top surface of the substrate, the stack of crystalline la y ers including a plurality of threading dislocations extending from the substrate top surface through the stack to a top surface of the stack of crystalline la y ers; forming a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, by forming upper diode pole material for each of the diodes on the top surface of the stack of crystalline la y ers, each diode forming a diode j unction at the top surface of the stack with a diode pole region in the stack and below the upper diode pole material; forming interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation; forming a first set of at least one first conductor each connected to the upper diode pole material of a respective one of a first plurality of the diodes; forming a second set of at least one second conductor each connected to the diode pole region of a respective one of a second set of at least one of the diodes, each of the diodes connected to both one of the first conductors and one of the second conductors; and connecting the first and second conductors to the interrogation/decoding circuitry. Currently amended
The method of claim 24, wherein the uppermost crystalline layer of the stack is a first piezoelectric material formed on a second layer of the stack, the second layer of the stack being a second piezoelectric material having a different bandgap than the first piezoelectric material so as to form a heterojunction at [[the]]an interface between the uppermost and second layers of the stack; and wherein the second conductors include a 2DEG layer or a 2DHG layer below the heterojunction. Currently amended
The method of claim 24, wherein none of the diodes is connected to more than one of the first conductors nor more than one of the second conductors, the combination of one of the first conductors and one of the second conductors uniquely identifying a single one of the diodes. Original
29-36 Canceled
Canceled
A physically unclonable function (PUF) device comprising: a substrate having a crystalline top surface; a stack of at crystalline layers on the substrate crystalline top surface, the stack of crystalline layers having an uppermost crystalline layer and a lowest crystalline layer, the stack of crystalline layers including a plurality of threading dislocations extending from the substrate top surface up through the stack to a top surface of the stack of crystalline layers; a plurality of diodes, each occupying a respective distinct lateral region on the top surface of the stack, each of the diodes having upper diode pole material formed on the top surface of the stack and forming a diode junction at the top surface of the stack with a diode pole region in the stack below the upper diode pole material; interrogation/decoding circuitry connected to the diodes and arranged to provide binary output values indicating, for each of the diodes, whether the diode includes a threading dislocation; a first set of at least one first conductor each connected to the upper diode pole material of a respective one of a first plurality of the diodes; and a second set of at least one second conductor each connected to the diode pole region of a respective one of a second set of at least one of the diodes, each of the diodes connected to both one of the first conductors and one of the second conductors, wherein the first and second conductors are connected to the interrogation/decoding circuitry. New
Layer stacks claimed or described, ordered top of device to substrate.
PUF device with diode array (heterojunction stack)
PUF method device-epitaxially grown stack with diodes
Materials described outside the worked examples.
first piezoelectric material (uppermost crystalline layer)
second piezoelectric material (second layer of stack)
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Integrated circuit with transistors in GaN stack
crystalline substrate
GaN
GaN alloy (larger bandgap than GaN)
N-type semiconductor material
P-type semiconductor material
metal anode
2DEG or 2DHG layer
Si
Integrated circuit with transistors in GaN stack
crystalline substrate
GaN
GaN alloy (larger bandgap than GaN)
N-type semiconductor material
P-type semiconductor material
metal anode
2DEG or 2DHG layer
Si
Integrated circuit with transistors in GaN stack
crystalline substrate
GaN
GaN alloy (larger bandgap than GaN)
N-type semiconductor material
P-type semiconductor material
metal anode
2DEG or 2DHG layer
Si
Integrated circuit with transistors in GaN stack
crystalline substrate
GaN
GaN alloy (larger bandgap than GaN)
N-type semiconductor material
P-type semiconductor material
metal anode
2DEG or 2DHG layer
Si