Patent
Atlas literature
Patent
US 12,672,355 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1F illustrates a cross-sectional views representing a 40 structure including a metal-insulator-metal (MIM) capacitor in a patterned substrate having an …
FIG. 2 illustrates a cross-sectional view of a transistor 45 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 55 multi-gate technology, in accordance with …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure. B₂
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: 5 a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, the plurality of semiconduc-tor fins comprising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The integrated circuit structure of claim 1, wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The integrated circuit structure of claim 1, wherein the plurality of semiconductor fins has a spacing of approxi-mately 100 nanometers between neighboring semiconductor fins.
The integrated circuit structure of claim 1, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The integrated circuit structure of claim 1, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: 40 a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and 50 a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the plural-ity of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The computing device of claim 6, wherein the plu-rality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.
The computing device of claim 6, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The computing device of claim 6, wherein a compo-nent is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
A method of fabricating an integrated circuit structure, the method comprising: forming a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; forming a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins comprising silicon, each of the plurality of semicon-ductor fins in direct contact with and entirely above the first side of the material layer, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and forming a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The method of claim 15, wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The method of claim 15, wherein the plurality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.
The method of claim 15, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The method of claim 15, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
The method of claim 15, wherein forming the plurality of semiconductor fins comprises forming the material layer on a substrate having trenches therein, and then removing a portion of the substrate to reveal the trenches.
An integrated circuit structure, comprising: a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
An integrated circuit structure, comprising: a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and 29 30 a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-patterned-Si integrated circuit structure
Si-based device layer
Materials described outside the worked examples.
gallium nitride layer
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 45 having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,672,355 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1F illustrates a cross-sectional views representing a 40 structure including a metal-insulator-metal (MIM) capacitor in a patterned substrate having an …
FIG. 2 illustrates a cross-sectional view of a transistor 45 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 55 multi-gate technology, in accordance with …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure. B₂
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: 5 a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, the plurality of semiconduc-tor fins comprising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The integrated circuit structure of claim 1, wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The integrated circuit structure of claim 1, wherein the plurality of semiconductor fins has a spacing of approxi-mately 100 nanometers between neighboring semiconductor fins.
The integrated circuit structure of claim 1, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The integrated circuit structure of claim 1, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: 40 a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and 50 a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the plural-ity of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The computing device of claim 6, wherein the plu-rality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.
The computing device of claim 6, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The computing device of claim 6, wherein a compo-nent is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
A method of fabricating an integrated circuit structure, the method comprising: forming a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; forming a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins comprising silicon, each of the plurality of semicon-ductor fins in direct contact with and entirely above the first side of the material layer, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and forming a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The method of claim 15, wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The method of claim 15, wherein the plurality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.
The method of claim 15, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The method of claim 15, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
The method of claim 15, wherein forming the plurality of semiconductor fins comprises forming the material layer on a substrate having trenches therein, and then removing a portion of the substrate to reveal the trenches.
An integrated circuit structure, comprising: a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
An integrated circuit structure, comprising: a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and 29 30 a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-patterned-Si integrated circuit structure
Si-based device layer
Materials described outside the worked examples.
gallium nitride layer
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 45 having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,672,355 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1F illustrates a cross-sectional views representing a 40 structure including a metal-insulator-metal (MIM) capacitor in a patterned substrate having an …
FIG. 2 illustrates a cross-sectional view of a transistor 45 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 55 multi-gate technology, in accordance with …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure. B₂
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: 5 a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, the plurality of semiconduc-tor fins comprising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The integrated circuit structure of claim 1, wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The integrated circuit structure of claim 1, wherein the plurality of semiconductor fins has a spacing of approxi-mately 100 nanometers between neighboring semiconductor fins.
The integrated circuit structure of claim 1, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The integrated circuit structure of claim 1, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: 40 a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and 50 a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the plural-ity of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The computing device of claim 6, wherein the plu-rality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.
The computing device of claim 6, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The computing device of claim 6, wherein a compo-nent is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
A method of fabricating an integrated circuit structure, the method comprising: forming a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; forming a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins comprising silicon, each of the plurality of semicon-ductor fins in direct contact with and entirely above the first side of the material layer, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and forming a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The method of claim 15, wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The method of claim 15, wherein the plurality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.
The method of claim 15, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The method of claim 15, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
The method of claim 15, wherein forming the plurality of semiconductor fins comprises forming the material layer on a substrate having trenches therein, and then removing a portion of the substrate to reveal the trenches.
An integrated circuit structure, comprising: a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
An integrated circuit structure, comprising: a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and 29 30 a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-patterned-Si integrated circuit structure
Si-based device layer
Materials described outside the worked examples.
gallium nitride layer
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 45 having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,672,355 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1F illustrates a cross-sectional views representing a 40 structure including a metal-insulator-metal (MIM) capacitor in a patterned substrate having an …
FIG. 2 illustrates a cross-sectional view of a transistor 45 having a drain field plate, in accordance with embodiments of the present disclosure.
FIG. 3 illustrates a cross-sectional view of a GaN tran- sistor having a drain field plate and having multiple gates, in accordance with embodiments of the …
FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …
FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 55 multi-gate technology, in accordance with …
FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure. B₂
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
FIG. 11 illustrates a computing device in accordance with one implementation of the disclosure.
FIG. 12 illustrates an interposer that includes one or more embodiments of the disclosure.
FIG. 13 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: 5 a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, the plurality of semiconduc-tor fins comprising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The integrated circuit structure of claim 1, wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The integrated circuit structure of claim 1, wherein the plurality of semiconductor fins has a spacing of approxi-mately 100 nanometers between neighboring semiconductor fins.
The integrated circuit structure of claim 1, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The integrated circuit structure of claim 1, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
A computing device, comprising: a board; and a component coupled to the board, the component includ-ing an integrated circuit structure, comprising: 40 a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, each of the plurality of semiconductor fins in direct contact with and entirely above the first side of the material layer, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and 50 a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The computing device of claim 6, further comprising: a memory coupled to the board.
The computing device of claim 6, further comprising: a communication chip coupled to the board.
The computing device of claim 6, further comprising: a camera coupled to the board.
The computing device of claim 6, wherein the com-ponent is a packaged integrated circuit die.
The computing device of claim 6, wherein the plural-ity of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The computing device of claim 6, wherein the plu-rality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.
The computing device of claim 6, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The computing device of claim 6, wherein a compo-nent is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
A method of fabricating an integrated circuit structure, the method comprising: forming a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; forming a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins comprising silicon, each of the plurality of semicon-ductor fins in direct contact with and entirely above the first side of the material layer, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and forming a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices.
The method of claim 15, wherein the plurality of semiconductor fins is coupled to the material layer at a Si(111) crystal plane.
The method of claim 15, wherein the plurality of semiconductor fins has a spacing of approximately 100 nanometers between neighboring semiconductor fins.
The method of claim 15, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
The method of claim 15, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator.
The method of claim 15, wherein forming the plurality of semiconductor fins comprises forming the material layer on a substrate having trenches therein, and then removing a portion of the substrate to reveal the trenches.
An integrated circuit structure, comprising: a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices, wherein the device layer is bonded to a second device layer comprising silicon, the second device layer comprising one or more Si-based devices.
An integrated circuit structure, comprising: a material layer comprising gallium and nitrogen, the material layer having a first side and a second side opposite the first side; a plurality of semiconductor fins on the first side of the material layer, the plurality of semiconductor fins com-prising silicon, wherein individual ones of the plurality of semiconductor fins are discontinuous with one another; and 29 30 a device layer on the second side of the material layer, the device layer comprising one or more GaN-based devices, wherein a component is included in a spacing between a pair of the plurality of semiconductor fins, the component selected from the group consisting of a through silicon via, a metal-insulator-metal capacitor, and a resonator. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-on-patterned-Si integrated circuit structure
Si-based device layer
Materials described outside the worked examples.
gallium nitride layer
GaN
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a cross-sectional view of a transistor 45 having a drain field plate, in accordance with embodiments of the present disclosure.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–100 µm | — |
— | 4.9–5.2 eV |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 6
Related documents with shared materials, methods, properties, or citations.
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure. B₂
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
Cited non-patent literature · 2
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure. B₂
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
Cited non-patent literature · 2
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure. B₂
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
Cited non-patent literature · 2
FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure. B₂
FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure.
FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …
| — |
— | 3.9–4.2 eV | — |
Voltage | 48–72 V | — |
Voltage | 0.5–3.3 V | — |
Voltage | ≥ 2 V | — |
Cited non-patent literature · 2
