FIGS. 1-3. In this embodiment, the hard 11 Attorney Docket No.: SE-2771-TD Reference No.: 0008.0033 mask 16 can include a top layer of silicon oxide. …

FIG. 2. A first etch can be used to remove the exposed hard mask 16, and a second etch can be used to remove the exposed silicon 14 and to stop on the sapphire …

FIG. 3 structure. The thermal oxidation process uxiizCes the expose d silicon layer I₄ to Irm dielectric spacers 30, for examp l e, including oxide, while the …

FIG. 4, this grow th is Inhibited by the silicon oxide of the mask layer 16, such that the growth occurs only within the opening between oxide spacers 30 over …

FIG. 5. The various steps to form these layers are not repeated for brevity. [0047]After forming the

FIG. 6. Each MOSFET transistor includes a transistor source metal 330 contacting a first N-well 332 and a transistor drain metal 334 contacting a second N-well …

FIG. 7. For purposes of illustration, the structure of

FIG. 8. For purposes of this disclosure, the selectively grown layers are referred to collectively herein as GaN device layer 80, while silicon device layer 14 …

FIG. 9, such as various semiconductor devices and circuitry. The silicon device layer 14 provides a bulk silicon (i.e., silicon semiconductor functionality), …

FIG. 10, and can include a silicon handle wafer 102, for example, having a <111> crystal orientation, a buried oxide layer 104, and a silicon layer 106, for …

FIG. 11 structure can be performed t resu l t in I te

FIG. 12 st r uct ure. TI ie t hermai oxidatIion process oxidizes the exposed silicon layer 106 to form oxide spacers 120. The thermal oxidation process used to …

FIG. 13, including a < 111 > silicon handle wafer 102 which is exposed at opening 122. Additionally, hard mask 108 will include an upper layer of silicon …

FIG. 14 structure, a planarization process is performed to result in the

FIG. 15 structure. The planarization process can remove layers 108 and 140-146 to form a planar surface which includes silicon layer 106, oxide spacers 120, …

FIG. 16, such as various semiconductor devices and circuitry. The silicon layer 106 provides a bulk silicon (i.e., silicon semiconductor functionality), while …

FIG. 17. These layers can include a stress relief layer 170, a buffer layer 172, a carrier donor layer 174, and an optional capping layer 176. These layers can …

FIG. 18. An upper surface of the

FIG. 19. These devices 190-194 can be similar to devices 60-64 discussed relative to

FIG. 20, which can include a <111> silicon handle wafer 202, a <100> silicon layer 204, a hard mask layer 206 having an upper exposed surface of silicon …

FIG. 21. [0054] Next, exposed silicon surfaces are oxidized, for example, using a thermal oxidation process to result in oxide layer 220 as depicted in

FIG. 22. This process oxidizes the exposed silicon surfaces of both the silicon handle wafer 202 and the silicon layer 204. [0055] Next, an anisotropic spacer …

FIG. 23, which includes oxide spacers 230, and an opening 232. This spacer etch removes a majority of oxide layer 220 from the silicon handle wafer 202. [0056] …

FIG. 24. These layers can be formed using the techniques in accordance wilh tie embodiment of

FIG. 25.

FIG. 27. The various layers can include a stress relief layer 270, a buffer layer 272, an optional barrier layer 274, and a capping layer 276. These layers can …

FIG. 28 structure. Layers 270-276 are collectively referred 21 Attorney Docket No.: SE-2771-TD Reference No.: 0008.0033 to herein as GaN device layer 280 while …

FIG. 30. The electronic system 300 can include a power source (power supply) 302 which is electrically coupled to one or more voltage regulators (voltage …

FIG. 31 below, or other types of devices. For example, a device such as device 60 or 62 formed on and/or within the silicon device layer can include N and P …

FIGS. 1-3. In this embodiment, the hard 11 Attorney Docket No.: SE-2771-TD Reference No.: 0008.0033 mask 16 can include a top layer of silicon oxide. …

FIG. 2. A first etch can be used to remove the exposed hard mask 16, and a second etch can be used to remove the exposed silicon 14 and to stop on the sapphire …

FIG. 3 structure. The thermal oxidation process uxiizCes the expose d silicon layer I₄ to Irm dielectric spacers 30, for examp l e, including oxide, while the …

FIG. 4, this grow th is Inhibited by the silicon oxide of the mask layer 16, such that the growth occurs only within the opening between oxide spacers 30 over …

FIG. 5. The various steps to form these layers are not repeated for brevity. [0047]After forming the

FIG. 6. Each MOSFET transistor includes a transistor source metal 330 contacting a first N-well 332 and a transistor drain metal 334 contacting a second N-well …

FIG. 7. For purposes of illustration, the structure of

FIG. 8. For purposes of this disclosure, the selectively grown layers are referred to collectively herein as GaN device layer 80, while silicon device layer 14 …

FIG. 9, such as various semiconductor devices and circuitry. The silicon device layer 14 provides a bulk silicon (i.e., silicon semiconductor functionality), …

FIG. 10, and can include a silicon handle wafer 102, for example, having a <111> crystal orientation, a buried oxide layer 104, and a silicon layer 106, for …

FIG. 11 structure can be performed t resu l t in I te

FIG. 12 st r uct ure. TI ie t hermai oxidatIion process oxidizes the exposed silicon layer 106 to form oxide spacers 120. The thermal oxidation process used to …

FIG. 13, including a < 111 > silicon handle wafer 102 which is exposed at opening 122. Additionally, hard mask 108 will include an upper layer of silicon …

FIG. 14 structure, a planarization process is performed to result in the

FIG. 15 structure. The planarization process can remove layers 108 and 140-146 to form a planar surface which includes silicon layer 106, oxide spacers 120, …

FIG. 16, such as various semiconductor devices and circuitry. The silicon layer 106 provides a bulk silicon (i.e., silicon semiconductor functionality), while …

FIG. 17. These layers can include a stress relief layer 170, a buffer layer 172, a carrier donor layer 174, and an optional capping layer 176. These layers can …

FIG. 18. An upper surface of the

FIG. 19. These devices 190-194 can be similar to devices 60-64 discussed relative to

FIG. 20, which can include a <111> silicon handle wafer 202, a <100> silicon layer 204, a hard mask layer 206 having an upper exposed surface of silicon …

FIG. 21. [0054] Next, exposed silicon surfaces are oxidized, for example, using a thermal oxidation process to result in oxide layer 220 as depicted in

FIG. 22. This process oxidizes the exposed silicon surfaces of both the silicon handle wafer 202 and the silicon layer 204. [0055] Next, an anisotropic spacer …

FIG. 23, which includes oxide spacers 230, and an opening 232. This spacer etch removes a majority of oxide layer 220 from the silicon handle wafer 202. [0056] …

FIG. 24. These layers can be formed using the techniques in accordance wilh tie embodiment of

FIG. 25.

FIG. 27. The various layers can include a stress relief layer 270, a buffer layer 272, an optional barrier layer 274, and a capping layer 276. These layers can …

FIG. 28 structure. Layers 270-276 are collectively referred 21 Attorney Docket No.: SE-2771-TD Reference No.: 0008.0033 to herein as GaN device layer 280 while …

FIG. 30. The electronic system 300 can include a power source (power supply) 302 which is electrically coupled to one or more voltage regulators (voltage …

FIG. 31 below, or other types of devices. For example, a device such as device 60 or 62 formed on and/or within the silicon device layer can include N and P …

FIGS. 1-3. In this embodiment, the hard 11 Attorney Docket No.: SE-2771-TD Reference No.: 0008.0033 mask 16 can include a top layer of silicon oxide. …

FIG. 2. A first etch can be used to remove the exposed hard mask 16, and a second etch can be used to remove the exposed silicon 14 and to stop on the sapphire …

FIG. 3 structure. The thermal oxidation process uxiizCes the expose d silicon layer I₄ to Irm dielectric spacers 30, for examp l e, including oxide, while the …

FIG. 4, this grow th is Inhibited by the silicon oxide of the mask layer 16, such that the growth occurs only within the opening between oxide spacers 30 over …

FIG. 5. The various steps to form these layers are not repeated for brevity. [0047]After forming the

FIG. 6. Each MOSFET transistor includes a transistor source metal 330 contacting a first N-well 332 and a transistor drain metal 334 contacting a second N-well …

FIG. 7. For purposes of illustration, the structure of

FIG. 8. For purposes of this disclosure, the selectively grown layers are referred to collectively herein as GaN device layer 80, while silicon device layer 14 …

FIG. 9, such as various semiconductor devices and circuitry. The silicon device layer 14 provides a bulk silicon (i.e., silicon semiconductor functionality), …

FIG. 10, and can include a silicon handle wafer 102, for example, having a <111> crystal orientation, a buried oxide layer 104, and a silicon layer 106, for …

FIG. 11 structure can be performed t resu l t in I te

FIG. 12 st r uct ure. TI ie t hermai oxidatIion process oxidizes the exposed silicon layer 106 to form oxide spacers 120. The thermal oxidation process used to …

FIG. 13, including a < 111 > silicon handle wafer 102 which is exposed at opening 122. Additionally, hard mask 108 will include an upper layer of silicon …

FIG. 14 structure, a planarization process is performed to result in the

FIG. 15 structure. The planarization process can remove layers 108 and 140-146 to form a planar surface which includes silicon layer 106, oxide spacers 120, …

FIG. 16, such as various semiconductor devices and circuitry. The silicon layer 106 provides a bulk silicon (i.e., silicon semiconductor functionality), while …

FIG. 17. These layers can include a stress relief layer 170, a buffer layer 172, a carrier donor layer 174, and an optional capping layer 176. These layers can …

FIG. 18. An upper surface of the

FIG. 19. These devices 190-194 can be similar to devices 60-64 discussed relative to

FIG. 20, which can include a <111> silicon handle wafer 202, a <100> silicon layer 204, a hard mask layer 206 having an upper exposed surface of silicon …

FIG. 21. [0054] Next, exposed silicon surfaces are oxidized, for example, using a thermal oxidation process to result in oxide layer 220 as depicted in

FIG. 22. This process oxidizes the exposed silicon surfaces of both the silicon handle wafer 202 and the silicon layer 204. [0055] Next, an anisotropic spacer …

FIG. 23, which includes oxide spacers 230, and an opening 232. This spacer etch removes a majority of oxide layer 220 from the silicon handle wafer 202. [0056] …

FIG. 24. These layers can be formed using the techniques in accordance wilh tie embodiment of

FIG. 25.

FIG. 27. The various layers can include a stress relief layer 270, a buffer layer 272, an optional barrier layer 274, and a capping layer 276. These layers can …

FIG. 28 structure. Layers 270-276 are collectively referred 21 Attorney Docket No.: SE-2771-TD Reference No.: 0008.0033 to herein as GaN device layer 280 while …

FIG. 30. The electronic system 300 can include a power source (power supply) 302 which is electrically coupled to one or more voltage regulators (voltage …

FIG. 31 below, or other types of devices. For example, a device such as device 60 or 62 formed on and/or within the silicon device layer can include N and P …

FIGS. 1-3. In this embodiment, the hard 11 Attorney Docket No.: SE-2771-TD Reference No.: 0008.0033 mask 16 can include a top layer of silicon oxide. …

FIG. 2. A first etch can be used to remove the exposed hard mask 16, and a second etch can be used to remove the exposed silicon 14 and to stop on the sapphire …

FIG. 3 structure. The thermal oxidation process uxiizCes the expose d silicon layer I₄ to Irm dielectric spacers 30, for examp l e, including oxide, while the …

FIG. 4, this grow th is Inhibited by the silicon oxide of the mask layer 16, such that the growth occurs only within the opening between oxide spacers 30 over …

FIG. 5. The various steps to form these layers are not repeated for brevity. [0047]After forming the

FIG. 6. Each MOSFET transistor includes a transistor source metal 330 contacting a first N-well 332 and a transistor drain metal 334 contacting a second N-well …

FIG. 7. For purposes of illustration, the structure of

FIG. 8. For purposes of this disclosure, the selectively grown layers are referred to collectively herein as GaN device layer 80, while silicon device layer 14 …

FIG. 9, such as various semiconductor devices and circuitry. The silicon device layer 14 provides a bulk silicon (i.e., silicon semiconductor functionality), …

FIG. 10, and can include a silicon handle wafer 102, for example, having a <111> crystal orientation, a buried oxide layer 104, and a silicon layer 106, for …

FIG. 11 structure can be performed t resu l t in I te

FIG. 12 st r uct ure. TI ie t hermai oxidatIion process oxidizes the exposed silicon layer 106 to form oxide spacers 120. The thermal oxidation process used to …

FIG. 13, including a < 111 > silicon handle wafer 102 which is exposed at opening 122. Additionally, hard mask 108 will include an upper layer of silicon …

FIG. 14 structure, a planarization process is performed to result in the

FIG. 15 structure. The planarization process can remove layers 108 and 140-146 to form a planar surface which includes silicon layer 106, oxide spacers 120, …

FIG. 16, such as various semiconductor devices and circuitry. The silicon layer 106 provides a bulk silicon (i.e., silicon semiconductor functionality), while …

FIG. 17. These layers can include a stress relief layer 170, a buffer layer 172, a carrier donor layer 174, and an optional capping layer 176. These layers can …

FIG. 18. An upper surface of the

FIG. 19. These devices 190-194 can be similar to devices 60-64 discussed relative to

FIG. 20, which can include a <111> silicon handle wafer 202, a <100> silicon layer 204, a hard mask layer 206 having an upper exposed surface of silicon …

FIG. 21. [0054] Next, exposed silicon surfaces are oxidized, for example, using a thermal oxidation process to result in oxide layer 220 as depicted in

FIG. 22. This process oxidizes the exposed silicon surfaces of both the silicon handle wafer 202 and the silicon layer 204. [0055] Next, an anisotropic spacer …

FIG. 23, which includes oxide spacers 230, and an opening 232. This spacer etch removes a majority of oxide layer 220 from the silicon handle wafer 202. [0056] …

FIG. 24. These layers can be formed using the techniques in accordance wilh tie embodiment of

FIG. 25.

FIG. 27. The various layers can include a stress relief layer 270, a buffer layer 272, an optional barrier layer 274, and a capping layer 276. These layers can …

FIG. 28 structure. Layers 270-276 are collectively referred 21 Attorney Docket No.: SE-2771-TD Reference No.: 0008.0033 to herein as GaN device layer 280 while …

FIG. 30. The electronic system 300 can include a power source (power supply) 302 which is electrically coupled to one or more voltage regulators (voltage …

FIG. 31 below, or other types of devices. For example, a device such as device 60 or 62 formed on and/or within the silicon device layer can include N and P …