Patent
US 8,841,708METHOD AND SYSTEM FOR A GAN VERTICAL JFET WITH SELF-ALIGNED SOURCE METALLIZATION
Donald R. Disney, Richard J. Brown, Hui Nie
AVOGY, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,841,708Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-5 and 6A-6C are simplified cross-sectional diagrams illustrating the fabrication of a vertical junction field-effect transistor (JFET) according to an …
FIG. 2, a photoresist mask 210 is coupled to the second masking layer 150, and exposed portions of the second masking layer 150, the first masking layer 140, …
FIGS. 3 and 4 illustrate how a spacer layer 310 can be deposited and/or otherwise formed to cover the surfaces 121 of the first GaN epitaxial layer 120, as well …
FIG. 5. The sidewall spacer can be an electrically insulating material formed using the methods described herein. As illustrated in
FIG. 6C. Thus, embodiments of the present invention 30 reduce the use of photolithography processes during gate metal definition steps, reducing 15 processing …
FIG. 7A. ILD layer 780 is formed such that it substantially fills up the space above gate structures 610 and gate metal structures 710, between adjacent channel …
FIG. 8 illustrates how an inter-layer dielectric (ILD) 810 may be formed over the existing structures and etched (and/or subject to other material removal …
FIG. 9 illustrates the formation of one or more metal structures 910 to make electrical contact with the second GaN epitaxial layer 130, and the formation of …
FIG. 10 A is a simplified flowchart illustrating a method of fabricating a vertical JFET 20 with self-aligned gate structure according to an embodiment of the …
FIG. 11 is a plan view of a vertical JFET 1100 according to an embodiment of the present invention. Vertical JFET 1100, which is suitable for use as a power …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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Layer stacks claimed or described, ordered top of device to substrate.
GaN vertical JFET with self-aligned source metallization
Materials described outside the worked examples.
III-nitride substrate
first III-nitride epitaxial material
second III-nitride epitaxial material
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-5 and 6A-6C are simplified cross-sectional diagrams illustrating the fabrication of a vertical junction field-effect transistor (JFET) according to an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,841,708Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-5 and 6A-6C are simplified cross-sectional diagrams illustrating the fabrication of a vertical junction field-effect transistor (JFET) according to an …
FIG. 2, a photoresist mask 210 is coupled to the second masking layer 150, and exposed portions of the second masking layer 150, the first masking layer 140, …
FIGS. 3 and 4 illustrate how a spacer layer 310 can be deposited and/or otherwise formed to cover the surfaces 121 of the first GaN epitaxial layer 120, as well …
FIG. 5. The sidewall spacer can be an electrically insulating material formed using the methods described herein. As illustrated in
FIG. 6C. Thus, embodiments of the present invention 30 reduce the use of photolithography processes during gate metal definition steps, reducing 15 processing …
FIG. 7A. ILD layer 780 is formed such that it substantially fills up the space above gate structures 610 and gate metal structures 710, between adjacent channel …
FIG. 8 illustrates how an inter-layer dielectric (ILD) 810 may be formed over the existing structures and etched (and/or subject to other material removal …
FIG. 9 illustrates the formation of one or more metal structures 910 to make electrical contact with the second GaN epitaxial layer 130, and the formation of …
FIG. 10 A is a simplified flowchart illustrating a method of fabricating a vertical JFET 20 with self-aligned gate structure according to an embodiment of the …
FIG. 11 is a plan view of a vertical JFET 1100 according to an embodiment of the present invention. Vertical JFET 1100, which is suitable for use as a power …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN vertical JFET with self-aligned source metallization
Materials described outside the worked examples.
III-nitride substrate
first III-nitride epitaxial material
second III-nitride epitaxial material
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-5 and 6A-6C are simplified cross-sectional diagrams illustrating the fabrication of a vertical junction field-effect transistor (JFET) according to an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,841,708Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-5 and 6A-6C are simplified cross-sectional diagrams illustrating the fabrication of a vertical junction field-effect transistor (JFET) according to an …
FIG. 2, a photoresist mask 210 is coupled to the second masking layer 150, and exposed portions of the second masking layer 150, the first masking layer 140, …
FIGS. 3 and 4 illustrate how a spacer layer 310 can be deposited and/or otherwise formed to cover the surfaces 121 of the first GaN epitaxial layer 120, as well …
FIG. 5. The sidewall spacer can be an electrically insulating material formed using the methods described herein. As illustrated in
FIG. 6C. Thus, embodiments of the present invention 30 reduce the use of photolithography processes during gate metal definition steps, reducing 15 processing …
FIG. 7A. ILD layer 780 is formed such that it substantially fills up the space above gate structures 610 and gate metal structures 710, between adjacent channel …
FIG. 8 illustrates how an inter-layer dielectric (ILD) 810 may be formed over the existing structures and etched (and/or subject to other material removal …
FIG. 9 illustrates the formation of one or more metal structures 910 to make electrical contact with the second GaN epitaxial layer 130, and the formation of …
FIG. 10 A is a simplified flowchart illustrating a method of fabricating a vertical JFET 20 with self-aligned gate structure according to an embodiment of the …
FIG. 11 is a plan view of a vertical JFET 1100 according to an embodiment of the present invention. Vertical JFET 1100, which is suitable for use as a power …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN vertical JFET with self-aligned source metallization
Materials described outside the worked examples.
III-nitride substrate
first III-nitride epitaxial material
second III-nitride epitaxial material
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-5 and 6A-6C are simplified cross-sectional diagrams illustrating the fabrication of a vertical junction field-effect transistor (JFET) according to an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,841,708Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-5 and 6A-6C are simplified cross-sectional diagrams illustrating the fabrication of a vertical junction field-effect transistor (JFET) according to an …
FIG. 2, a photoresist mask 210 is coupled to the second masking layer 150, and exposed portions of the second masking layer 150, the first masking layer 140, …
FIGS. 3 and 4 illustrate how a spacer layer 310 can be deposited and/or otherwise formed to cover the surfaces 121 of the first GaN epitaxial layer 120, as well …
FIG. 5. The sidewall spacer can be an electrically insulating material formed using the methods described herein. As illustrated in
FIG. 6C. Thus, embodiments of the present invention 30 reduce the use of photolithography processes during gate metal definition steps, reducing 15 processing …
FIG. 7A. ILD layer 780 is formed such that it substantially fills up the space above gate structures 610 and gate metal structures 710, between adjacent channel …
FIG. 8 illustrates how an inter-layer dielectric (ILD) 810 may be formed over the existing structures and etched (and/or subject to other material removal …
FIG. 9 illustrates the formation of one or more metal structures 910 to make electrical contact with the second GaN epitaxial layer 130, and the formation of …
FIG. 10 A is a simplified flowchart illustrating a method of fabricating a vertical JFET 20 with self-aligned gate structure according to an embodiment of the …
FIG. 11 is a plan view of a vertical JFET 1100 according to an embodiment of the present invention. Vertical JFET 1100, which is suitable for use as a power …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN vertical JFET with self-aligned source metallization
Materials described outside the worked examples.
III-nitride substrate
first III-nitride epitaxial material
second III-nitride epitaxial material
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-5 and 6A-6C are simplified cross-sectional diagrams illustrating the fabrication of a vertical junction field-effect transistor (JFET) according to an …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
GaN
FIG. 5. The sidewall spacer can be an electrically insulating material formed using the methods described herein. As illustrated in
FIG. 7A. ILD layer 780 is formed such that it substantially fills up the space above gate structures 610 and gate metal structures 710, between adjacent channel …
FIG. 9 illustrates the formation of one or more metal structures 910 to make electrical contact with the second GaN epitaxial layer 130, and the formation of …
GaN
FIG. 5. The sidewall spacer can be an electrically insulating material formed using the methods described herein. As illustrated in
FIG. 7A. ILD layer 780 is formed such that it substantially fills up the space above gate structures 610 and gate metal structures 710, between adjacent channel …
FIG. 9 illustrates the formation of one or more metal structures 910 to make electrical contact with the second GaN epitaxial layer 130, and the formation of …
GaN
FIG. 5. The sidewall spacer can be an electrically insulating material formed using the methods described herein. As illustrated in
FIG. 7A. ILD layer 780 is formed such that it substantially fills up the space above gate structures 610 and gate metal structures 710, between adjacent channel …
FIG. 9 illustrates the formation of one or more metal structures 910 to make electrical contact with the second GaN epitaxial layer 130, and the formation of …
GaN
FIG. 5. The sidewall spacer can be an electrically insulating material formed using the methods described herein. As illustrated in
FIG. 7A. ILD layer 780 is formed such that it substantially fills up the space above gate structures 610 and gate metal structures 710, between adjacent channel …
FIG. 9 illustrates the formation of one or more metal structures 910 to make electrical contact with the second GaN epitaxial layer 130, and the formation of …