Patent
US 9,324,645METHOD AND SYSTEM FOR CO-PACKAGING GALLIUM NITRIDE ELECTRONICS
Donald R. Disney, Hemal N. Shah
Avogy, Inc.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,324,645Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface of …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. 5 [0039] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5. Pin 530A of
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic package comprising: a leadframe; a plurality of pins; a first gallium nitride (GaN) transistor comprising a source, gate, and drain, wherein the source of the first GaN transistor [[is]] has a surface in contact with the leadframe and is electrically connected to the leadframe; a second GaN transistor comprising a source, gate, and drain, wherein the drain of the second GaN transistor is electrically connected to the leadframe; a first GaN diode comprising an anode and cathode, wherein the anode of the first GaN diode is electrically connected to the leadframe; and a second GaN diode comprising an anode and cathode, wherein the cathode of the second GaN diode is electrically connected to the leadframe.
The electronic package of claim 1 wherein: the drain of the first GaN transistor and the cathode of the first diode is electrically connected to a first pin of the plurality of pins; the gate of the first GaN transistor is electrically connected to a second pin of the plurality of pins; the source of the second GaN transistor and the anode of the second diode is electrically connected to a third pin of the plurality of pins; and the gate of the second GaN transistor is electrically connected to a fourth pin of the plurality of pins.
The electronic package of claim 1 wherein: the electrical connection between the anode of the first diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the cathode of the second diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein: the electrical connection between the drain of the second GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the source of the first GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein the gallium nitride- based electronics package is electrically coupled and attached to a circuit board, wherein the leadframe is configured to conduct current from the source of the first GaN transistor, the drain of the second GaN transistor, the anode of the first GaN diode, and the cathode of the second GaN diode directly to the circuit board.
The electronic package of claim 1 further comprising one or more heat sinks attached to the leadframe.
The electronic package of claim 1 wherein the drain of the second GaN transistor and the source and the gate of the first GaN transistor comprises a solderable metal stack.
The electronic package of claim 1 wherein the drain of the first GaN transistor and the gate and source of the second GaN transistor comprises a bondable metal stack.
The electronic package of claim 1 wherein the source of the second GaN transistor is electrically connected to a fifth pin of the plurality of pins.
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Layer stacks claimed or described, ordered top of device to substrate.
co-packaged GaN half-bridge electronic package
Materials described outside the worked examples.
gallium nitride (first GaN transistor)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface of …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,324,645Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface of …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. 5 [0039] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5. Pin 530A of
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic package comprising: a leadframe; a plurality of pins; a first gallium nitride (GaN) transistor comprising a source, gate, and drain, wherein the source of the first GaN transistor [[is]] has a surface in contact with the leadframe and is electrically connected to the leadframe; a second GaN transistor comprising a source, gate, and drain, wherein the drain of the second GaN transistor is electrically connected to the leadframe; a first GaN diode comprising an anode and cathode, wherein the anode of the first GaN diode is electrically connected to the leadframe; and a second GaN diode comprising an anode and cathode, wherein the cathode of the second GaN diode is electrically connected to the leadframe.
The electronic package of claim 1 wherein: the drain of the first GaN transistor and the cathode of the first diode is electrically connected to a first pin of the plurality of pins; the gate of the first GaN transistor is electrically connected to a second pin of the plurality of pins; the source of the second GaN transistor and the anode of the second diode is electrically connected to a third pin of the plurality of pins; and the gate of the second GaN transistor is electrically connected to a fourth pin of the plurality of pins.
The electronic package of claim 1 wherein: the electrical connection between the anode of the first diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the cathode of the second diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein: the electrical connection between the drain of the second GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the source of the first GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein the gallium nitride- based electronics package is electrically coupled and attached to a circuit board, wherein the leadframe is configured to conduct current from the source of the first GaN transistor, the drain of the second GaN transistor, the anode of the first GaN diode, and the cathode of the second GaN diode directly to the circuit board.
The electronic package of claim 1 further comprising one or more heat sinks attached to the leadframe.
The electronic package of claim 1 wherein the drain of the second GaN transistor and the source and the gate of the first GaN transistor comprises a solderable metal stack.
The electronic package of claim 1 wherein the drain of the first GaN transistor and the gate and source of the second GaN transistor comprises a bondable metal stack.
The electronic package of claim 1 wherein the source of the second GaN transistor is electrically connected to a fifth pin of the plurality of pins.
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Layer stacks claimed or described, ordered top of device to substrate.
co-packaged GaN half-bridge electronic package
Materials described outside the worked examples.
gallium nitride (first GaN transistor)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface of …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,324,645Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface of …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. 5 [0039] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5. Pin 530A of
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic package comprising: a leadframe; a plurality of pins; a first gallium nitride (GaN) transistor comprising a source, gate, and drain, wherein the source of the first GaN transistor [[is]] has a surface in contact with the leadframe and is electrically connected to the leadframe; a second GaN transistor comprising a source, gate, and drain, wherein the drain of the second GaN transistor is electrically connected to the leadframe; a first GaN diode comprising an anode and cathode, wherein the anode of the first GaN diode is electrically connected to the leadframe; and a second GaN diode comprising an anode and cathode, wherein the cathode of the second GaN diode is electrically connected to the leadframe.
The electronic package of claim 1 wherein: the drain of the first GaN transistor and the cathode of the first diode is electrically connected to a first pin of the plurality of pins; the gate of the first GaN transistor is electrically connected to a second pin of the plurality of pins; the source of the second GaN transistor and the anode of the second diode is electrically connected to a third pin of the plurality of pins; and the gate of the second GaN transistor is electrically connected to a fourth pin of the plurality of pins.
The electronic package of claim 1 wherein: the electrical connection between the anode of the first diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the cathode of the second diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein: the electrical connection between the drain of the second GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the source of the first GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein the gallium nitride- based electronics package is electrically coupled and attached to a circuit board, wherein the leadframe is configured to conduct current from the source of the first GaN transistor, the drain of the second GaN transistor, the anode of the first GaN diode, and the cathode of the second GaN diode directly to the circuit board.
The electronic package of claim 1 further comprising one or more heat sinks attached to the leadframe.
The electronic package of claim 1 wherein the drain of the second GaN transistor and the source and the gate of the first GaN transistor comprises a solderable metal stack.
The electronic package of claim 1 wherein the drain of the first GaN transistor and the gate and source of the second GaN transistor comprises a bondable metal stack.
The electronic package of claim 1 wherein the source of the second GaN transistor is electrically connected to a fifth pin of the plurality of pins.
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Layer stacks claimed or described, ordered top of device to substrate.
co-packaged GaN half-bridge electronic package
Materials described outside the worked examples.
gallium nitride (first GaN transistor)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface of …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,324,645Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface of …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. 5 [0039] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5. Pin 530A of
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic package comprising: a leadframe; a plurality of pins; a first gallium nitride (GaN) transistor comprising a source, gate, and drain, wherein the source of the first GaN transistor [[is]] has a surface in contact with the leadframe and is electrically connected to the leadframe; a second GaN transistor comprising a source, gate, and drain, wherein the drain of the second GaN transistor is electrically connected to the leadframe; a first GaN diode comprising an anode and cathode, wherein the anode of the first GaN diode is electrically connected to the leadframe; and a second GaN diode comprising an anode and cathode, wherein the cathode of the second GaN diode is electrically connected to the leadframe.
The electronic package of claim 1 wherein: the drain of the first GaN transistor and the cathode of the first diode is electrically connected to a first pin of the plurality of pins; the gate of the first GaN transistor is electrically connected to a second pin of the plurality of pins; the source of the second GaN transistor and the anode of the second diode is electrically connected to a third pin of the plurality of pins; and the gate of the second GaN transistor is electrically connected to a fourth pin of the plurality of pins.
The electronic package of claim 1 wherein: the electrical connection between the anode of the first diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the cathode of the second diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein: the electrical connection between the drain of the second GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the source of the first GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein the gallium nitride- based electronics package is electrically coupled and attached to a circuit board, wherein the leadframe is configured to conduct current from the source of the first GaN transistor, the drain of the second GaN transistor, the anode of the first GaN diode, and the cathode of the second GaN diode directly to the circuit board.
The electronic package of claim 1 further comprising one or more heat sinks attached to the leadframe.
The electronic package of claim 1 wherein the drain of the second GaN transistor and the source and the gate of the first GaN transistor comprises a solderable metal stack.
The electronic package of claim 1 wherein the drain of the first GaN transistor and the gate and source of the second GaN transistor comprises a bondable metal stack.
The electronic package of claim 1 wherein the source of the second GaN transistor is electrically connected to a fifth pin of the plurality of pins.
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Layer stacks claimed or described, ordered top of device to substrate.
co-packaged GaN half-bridge electronic package
Materials described outside the worked examples.
gallium nitride (first GaN transistor)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface of …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. 5 [0039] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. 5 [0039] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. 5 [0039] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
FIG. 2, vertical power transistor 100 includes a GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. 5 [0039] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …