Patent
US 12,119,809 B1DRIVER CIRCUITS FOR GALLIUM NITRIDE HALF BRIDGE POWER CONVERTERS
Santosh Sharma
Navitas Semiconductor Limited, Dublin (IE)·Oct. 15, 2024·US
Copyright © 2026 Matter42. All rights reserved.
Patent
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US 12,119,809 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the dis- closure;
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit 5 illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhance- ment-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in 20
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capaci- tor charging circuit as compared to the circuit illustrated in 25
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit 35 illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the disclosure;
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit 50 illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit 60 illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the disclosure;
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the disclosure;
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the disclosure;
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of a driver circuit;
FIG. 39 is a timing diagram illustrating timing relation- ships between various signals of the driver circuit of
FIG. 40 is a schematic illustration of an embodiment of a driver circuit with feedback switches; and
FIG. 41 is a timing diagram illustrating timing relation- ships between various signals of the driver circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit comprising: an input for receiving an input signal; an output for transmitting a drive signal; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a circuit node, the first drain is coupled to a first voltage source and the first source is coupled to the circuit node via a capaci-tor; a resistor coupled between the first gate and the circuit node; a second switch coupled between the first gate and the circuit node; a feedback signal generator circuit coupled to the second switch; and a third switch having a third source, a third drain and a third gate, wherein the third source is coupled to the circuit node, the third gate is directly coupled to the feedback signal generator circuit and the third drain is coupled to the output.
The driver circuit of claim 1, further comprising a fourth switch coupled between the first source and a ground.
A method of operating a driver circuit, the method comprising: providing a driver circuit, the driver circuit comprising: an input node and an output node; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a first node, the first drain is coupled to a first voltage source and the first source is coupled to a second node, the second node coupled to a third node via a capacitor; a resistor coupled between the third node and the first node; a second switch coupled between the third node and the first node; a feedback signal generator circuit coupled to the second switch; a third switch having a third source, a third drain and a third gate, wherein the third source is coupled to the third node, the third gate is coupled to the feedback signal generator circuit and the third drain is coupled to the output node; receiving an input signal at the input node; and generating an output signal at the output node in response to receiving the input signal at the input node, the driver circuit operating in at least three states comprising: wherein in a first state the capacitor is coupled between a second voltage source having a second voltage and a ground causing the capacitor to charge to the second voltage; wherein in a second state a charge on the capacitor causes the first switch to transition to an on state; and wherein in a third state the feedback signal generator circuit turns on the third switch, thereby connecting the third node to the output node.
The method of claim 8, wherein the driver circuit further comprises a fourth switch coupled between the second node and the ground.
A driver circuit comprising: an input for receiving an input signal; an output for transmitting a drive signal; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a circuit node, the first drain is coupled to a first voltage source and the first source is coupled to the circuit node via a capaci-tor; a resistor coupled between the first gate and the circuit node; a pass gate switch control circuit; and a second switch having a second source, a second drain and a second gate, wherein the second source is coupled to the circuit node, the second gate is directly coupled to the pass gate switch control circuit and the second drain is coupled to the output.
The driver circuit of claim 16, further comprising a third switch coupled between the first source and a ground.
Layer stacks claimed or described, ordered top of device to substrate.
driver circuit with feedback signal generator (claims 1–7)
No layer stack recorded.
driver circuit with pass gate switch control circuit (claims 16–20)
No layer stack recorded.
half bridge power conversion circuit with GaN devices
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Patents and literature cited by this patent (applicant and examiner references).
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Related documents with shared materials, methods, properties, or citations.
Patent
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US 12,119,809 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the dis- closure;
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit 5 illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhance- ment-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in 20
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capaci- tor charging circuit as compared to the circuit illustrated in 25
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit 35 illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the disclosure;
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit 50 illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit 60 illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the disclosure;
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the disclosure;
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the disclosure;
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of a driver circuit;
FIG. 39 is a timing diagram illustrating timing relation- ships between various signals of the driver circuit of
FIG. 40 is a schematic illustration of an embodiment of a driver circuit with feedback switches; and
FIG. 41 is a timing diagram illustrating timing relation- ships between various signals of the driver circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit comprising: an input for receiving an input signal; an output for transmitting a drive signal; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a circuit node, the first drain is coupled to a first voltage source and the first source is coupled to the circuit node via a capaci-tor; a resistor coupled between the first gate and the circuit node; a second switch coupled between the first gate and the circuit node; a feedback signal generator circuit coupled to the second switch; and a third switch having a third source, a third drain and a third gate, wherein the third source is coupled to the circuit node, the third gate is directly coupled to the feedback signal generator circuit and the third drain is coupled to the output.
The driver circuit of claim 1, further comprising a fourth switch coupled between the first source and a ground.
A method of operating a driver circuit, the method comprising: providing a driver circuit, the driver circuit comprising: an input node and an output node; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a first node, the first drain is coupled to a first voltage source and the first source is coupled to a second node, the second node coupled to a third node via a capacitor; a resistor coupled between the third node and the first node; a second switch coupled between the third node and the first node; a feedback signal generator circuit coupled to the second switch; a third switch having a third source, a third drain and a third gate, wherein the third source is coupled to the third node, the third gate is coupled to the feedback signal generator circuit and the third drain is coupled to the output node; receiving an input signal at the input node; and generating an output signal at the output node in response to receiving the input signal at the input node, the driver circuit operating in at least three states comprising: wherein in a first state the capacitor is coupled between a second voltage source having a second voltage and a ground causing the capacitor to charge to the second voltage; wherein in a second state a charge on the capacitor causes the first switch to transition to an on state; and wherein in a third state the feedback signal generator circuit turns on the third switch, thereby connecting the third node to the output node.
The method of claim 8, wherein the driver circuit further comprises a fourth switch coupled between the second node and the ground.
A driver circuit comprising: an input for receiving an input signal; an output for transmitting a drive signal; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a circuit node, the first drain is coupled to a first voltage source and the first source is coupled to the circuit node via a capaci-tor; a resistor coupled between the first gate and the circuit node; a pass gate switch control circuit; and a second switch having a second source, a second drain and a second gate, wherein the second source is coupled to the circuit node, the second gate is directly coupled to the pass gate switch control circuit and the second drain is coupled to the output.
The driver circuit of claim 16, further comprising a third switch coupled between the first source and a ground.
Layer stacks claimed or described, ordered top of device to substrate.
driver circuit with feedback signal generator (claims 1–7)
No layer stack recorded.
driver circuit with pass gate switch control circuit (claims 16–20)
No layer stack recorded.
half bridge power conversion circuit with GaN devices
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,119,809 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the dis- closure;
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit 5 illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhance- ment-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in 20
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capaci- tor charging circuit as compared to the circuit illustrated in 25
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit 35 illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the disclosure;
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit 50 illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit 60 illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the disclosure;
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the disclosure;
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the disclosure;
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of a driver circuit;
FIG. 39 is a timing diagram illustrating timing relation- ships between various signals of the driver circuit of
FIG. 40 is a schematic illustration of an embodiment of a driver circuit with feedback switches; and
FIG. 41 is a timing diagram illustrating timing relation- ships between various signals of the driver circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit comprising: an input for receiving an input signal; an output for transmitting a drive signal; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a circuit node, the first drain is coupled to a first voltage source and the first source is coupled to the circuit node via a capaci-tor; a resistor coupled between the first gate and the circuit node; a second switch coupled between the first gate and the circuit node; a feedback signal generator circuit coupled to the second switch; and a third switch having a third source, a third drain and a third gate, wherein the third source is coupled to the circuit node, the third gate is directly coupled to the feedback signal generator circuit and the third drain is coupled to the output.
The driver circuit of claim 1, further comprising a fourth switch coupled between the first source and a ground.
A method of operating a driver circuit, the method comprising: providing a driver circuit, the driver circuit comprising: an input node and an output node; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a first node, the first drain is coupled to a first voltage source and the first source is coupled to a second node, the second node coupled to a third node via a capacitor; a resistor coupled between the third node and the first node; a second switch coupled between the third node and the first node; a feedback signal generator circuit coupled to the second switch; a third switch having a third source, a third drain and a third gate, wherein the third source is coupled to the third node, the third gate is coupled to the feedback signal generator circuit and the third drain is coupled to the output node; receiving an input signal at the input node; and generating an output signal at the output node in response to receiving the input signal at the input node, the driver circuit operating in at least three states comprising: wherein in a first state the capacitor is coupled between a second voltage source having a second voltage and a ground causing the capacitor to charge to the second voltage; wherein in a second state a charge on the capacitor causes the first switch to transition to an on state; and wherein in a third state the feedback signal generator circuit turns on the third switch, thereby connecting the third node to the output node.
The method of claim 8, wherein the driver circuit further comprises a fourth switch coupled between the second node and the ground.
A driver circuit comprising: an input for receiving an input signal; an output for transmitting a drive signal; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a circuit node, the first drain is coupled to a first voltage source and the first source is coupled to the circuit node via a capaci-tor; a resistor coupled between the first gate and the circuit node; a pass gate switch control circuit; and a second switch having a second source, a second drain and a second gate, wherein the second source is coupled to the circuit node, the second gate is directly coupled to the pass gate switch control circuit and the second drain is coupled to the output.
The driver circuit of claim 16, further comprising a third switch coupled between the first source and a ground.
Layer stacks claimed or described, ordered top of device to substrate.
driver circuit with feedback signal generator (claims 1–7)
No layer stack recorded.
driver circuit with pass gate switch control circuit (claims 16–20)
No layer stack recorded.
half bridge power conversion circuit with GaN devices
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,119,809 B1Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the dis- closure;
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit 5 illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhance- ment-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in 20
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capaci- tor charging circuit as compared to the circuit illustrated in 25
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit 35 illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the disclosure;
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit 50 illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit 60 illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the disclosure;
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the disclosure;
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the disclosure;
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of a driver circuit;
FIG. 39 is a timing diagram illustrating timing relation- ships between various signals of the driver circuit of
FIG. 40 is a schematic illustration of an embodiment of a driver circuit with feedback switches; and
FIG. 41 is a timing diagram illustrating timing relation- ships between various signals of the driver circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit comprising: an input for receiving an input signal; an output for transmitting a drive signal; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a circuit node, the first drain is coupled to a first voltage source and the first source is coupled to the circuit node via a capaci-tor; a resistor coupled between the first gate and the circuit node; a second switch coupled between the first gate and the circuit node; a feedback signal generator circuit coupled to the second switch; and a third switch having a third source, a third drain and a third gate, wherein the third source is coupled to the circuit node, the third gate is directly coupled to the feedback signal generator circuit and the third drain is coupled to the output.
The driver circuit of claim 1, further comprising a fourth switch coupled between the first source and a ground.
A method of operating a driver circuit, the method comprising: providing a driver circuit, the driver circuit comprising: an input node and an output node; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a first node, the first drain is coupled to a first voltage source and the first source is coupled to a second node, the second node coupled to a third node via a capacitor; a resistor coupled between the third node and the first node; a second switch coupled between the third node and the first node; a feedback signal generator circuit coupled to the second switch; a third switch having a third source, a third drain and a third gate, wherein the third source is coupled to the third node, the third gate is coupled to the feedback signal generator circuit and the third drain is coupled to the output node; receiving an input signal at the input node; and generating an output signal at the output node in response to receiving the input signal at the input node, the driver circuit operating in at least three states comprising: wherein in a first state the capacitor is coupled between a second voltage source having a second voltage and a ground causing the capacitor to charge to the second voltage; wherein in a second state a charge on the capacitor causes the first switch to transition to an on state; and wherein in a third state the feedback signal generator circuit turns on the third switch, thereby connecting the third node to the output node.
The method of claim 8, wherein the driver circuit further comprises a fourth switch coupled between the second node and the ground.
A driver circuit comprising: an input for receiving an input signal; an output for transmitting a drive signal; a first switch having a first source, a first drain and a first gate, wherein the first gate is coupled to a circuit node, the first drain is coupled to a first voltage source and the first source is coupled to the circuit node via a capaci-tor; a resistor coupled between the first gate and the circuit node; a pass gate switch control circuit; and a second switch having a second source, a second drain and a second gate, wherein the second source is coupled to the circuit node, the second gate is directly coupled to the pass gate switch control circuit and the second drain is coupled to the output.
The driver circuit of claim 16, further comprising a third switch coupled between the first source and a ground.
Layer stacks claimed or described, ordered top of device to substrate.
driver circuit with feedback signal generator (claims 1–7)
No layer stack recorded.
driver circuit with pass gate switch control circuit (claims 16–20)
No layer stack recorded.
half bridge power conversion circuit with GaN devices
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 1
Related documents with shared materials, methods, properties, or citations.
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhance- ment-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhance- ment-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhance- ment-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhance- ment-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in