Patent
US 9,324,809METHOD AND SYSTEM FOR INTERLEAVED BOOST CONVERTER WITH CO-PACKAGED GALLIUM NITRIDE POWER DEVICES
Hemal N. Shah, Donald R. Disney
Avogy, Inc.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,324,809Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN 11 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
FIG. 2, vertical power transistor 100 includes a 5 GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0041] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5B. Thus, in this design, in addition to integration of transistors and diodes in a single package, inductors are also integrated, reducing 10 footprint …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic package comprising: a leadframe; a plurality of pins; a first gallium nitride (GaN) transistor comprising a source, gate, and drain, wherein the drain of the first GaN transistor is electrically connected to the leadframe; a second GaN transistor comprising a source, gate, and drain, wherein the drain of the second GaN transistor is electrically connected to the leadframe; a first GaN diode comprising an anode and cathode, wherein the anode of the first GaN diode is electrically connected to the leadframe and the cathode of the first GaN diode is wire bonded to an output pin of the plurality of pins; and a second GaN diode comprising an anode and cathode, wherein the anode of the second GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is wire bonded to the output pin of the plurality of pins.
The electronic package of claim 1 wherein: the source of the first GaN transistor is electrically connected to a first pin of the plurality of pins; the gate of the first GaN transistor is electrically connected to a second pin of the plurality of pins; the source of the second GaN transistor is electrically connected to a third pin of the plurality of pins; and the gate of the second GaN transistor is electrically connected to a fourth pin of the plurality of pins.
The electronic package of claim 1 wherein: the electrical connection between the anode of the first diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the anode of the second diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein: the electrical connection between the drain of the second GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the drain of the first GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein the gallium nitride- based electronics package is electrically coupled and attached to a circuit board, wherein the leadframe is configured to conduct current from the drain of the first GaN transistor, the drain of the second GaN transistor, the anode of the first GaN diode, and the anode of the second GaN diode directly to the circuit board.
The electronic package of claim 1 further comprising one or more heat sinks attached to the leadframe.
The electronic package of claim 1 wherein the drain of the first GaN transistor and the drain of the second GaN transistor comprise a solderable metal stack.
The electronic package of claim 1 wherein the source of the first GaN transistor and the source of the second GaN transistor comprise a bondable metal stack.
A method of fabricating an electronic package, the method comprising: providing a package comprising a leadframe and a plurality of pins; Page 3 of 9 App l. No. 14/083,217 PATENT Am dt. dated Response to Office Action of providing a set of gallium nitride (GaN) transistors, each comprising a drain contact, a source contact, and a gate contact; joining the drain contact of a first GaN transistor of the set of GaN transistors and the drain contact of a second GaN transistor of the set of GaN transistors to the leadframe; providing a set of GaN diodes, each comprising an anode contact and a cathode contact; and joining the anode contact of the first GaN diode and the anode contact of the second GaN diode to the leadframe. withdrawn
The method of claim 11 further comprising: electrically connecting the cathode contact of the first GaN diode to a first pin of the plurality of pins; electrically connecting the cathode contact of the second GaN diode to the first pin of the plurality of pins; electrically connecting the source contact of the first GaN transistor to a second pin of the plurality of pins; electrically connecting the gate contact of the first GaN transistor to a third pin of the plurality of pins; electrically connecting the source contact of the second GaN transistor to a fourth pin of the plurality of pins; and electrically connecting the gate contact of the second GaN transistor to a fifth pin of the plurality of pins. withdrawn
The method of claim 11 further comprising attaching the electronic package to a circuit board, wherein the leadframe is configured to conduct current from the drain contact of the first GaN transistor, the drain contact of the second GaN transistor, the anode contact of the first GaN diode, and the anode contact of the second GaN diode directly to the circuit board. withdrawn
The method of claim 11 wherein: the first GaN transistor comprises a solderable metal stack on the drain contact and a bondable metal stack on each of the source contact and gate contact; and the second GaN transistor comprises a solderable metal stack on the drain contact and a bondable metal stack on each of the source contact and gate contact. withdrawn
The method of claim 11 wherein: the first GaN diode comprises a solderable metal stack on the anode contact and a bondable metal stack on the cathode contact; and the second GaN diode comprises a solderable metal stack on the anode contact and a bondable metal stack on the cathode contact. withdrawn
The method of claim 11 further comprising electrically connecting the source contact of the second GaN transistor to a fifth pin of the plurality of pins. Page 5 of 9 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
co-packaged GaN electronic package (interleaved boost converter)
Materials described outside the worked examples.
gallium nitride (GaN) — transistor
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN 11 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 25–400 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,324,809Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN 11 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
FIG. 2, vertical power transistor 100 includes a 5 GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0041] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5B. Thus, in this design, in addition to integration of transistors and diodes in a single package, inductors are also integrated, reducing 10 footprint …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic package comprising: a leadframe; a plurality of pins; a first gallium nitride (GaN) transistor comprising a source, gate, and drain, wherein the drain of the first GaN transistor is electrically connected to the leadframe; a second GaN transistor comprising a source, gate, and drain, wherein the drain of the second GaN transistor is electrically connected to the leadframe; a first GaN diode comprising an anode and cathode, wherein the anode of the first GaN diode is electrically connected to the leadframe and the cathode of the first GaN diode is wire bonded to an output pin of the plurality of pins; and a second GaN diode comprising an anode and cathode, wherein the anode of the second GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is wire bonded to the output pin of the plurality of pins.
The electronic package of claim 1 wherein: the source of the first GaN transistor is electrically connected to a first pin of the plurality of pins; the gate of the first GaN transistor is electrically connected to a second pin of the plurality of pins; the source of the second GaN transistor is electrically connected to a third pin of the plurality of pins; and the gate of the second GaN transistor is electrically connected to a fourth pin of the plurality of pins.
The electronic package of claim 1 wherein: the electrical connection between the anode of the first diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the anode of the second diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein: the electrical connection between the drain of the second GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the drain of the first GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein the gallium nitride- based electronics package is electrically coupled and attached to a circuit board, wherein the leadframe is configured to conduct current from the drain of the first GaN transistor, the drain of the second GaN transistor, the anode of the first GaN diode, and the anode of the second GaN diode directly to the circuit board.
The electronic package of claim 1 further comprising one or more heat sinks attached to the leadframe.
The electronic package of claim 1 wherein the drain of the first GaN transistor and the drain of the second GaN transistor comprise a solderable metal stack.
The electronic package of claim 1 wherein the source of the first GaN transistor and the source of the second GaN transistor comprise a bondable metal stack.
A method of fabricating an electronic package, the method comprising: providing a package comprising a leadframe and a plurality of pins; Page 3 of 9 App l. No. 14/083,217 PATENT Am dt. dated Response to Office Action of providing a set of gallium nitride (GaN) transistors, each comprising a drain contact, a source contact, and a gate contact; joining the drain contact of a first GaN transistor of the set of GaN transistors and the drain contact of a second GaN transistor of the set of GaN transistors to the leadframe; providing a set of GaN diodes, each comprising an anode contact and a cathode contact; and joining the anode contact of the first GaN diode and the anode contact of the second GaN diode to the leadframe. withdrawn
The method of claim 11 further comprising: electrically connecting the cathode contact of the first GaN diode to a first pin of the plurality of pins; electrically connecting the cathode contact of the second GaN diode to the first pin of the plurality of pins; electrically connecting the source contact of the first GaN transistor to a second pin of the plurality of pins; electrically connecting the gate contact of the first GaN transistor to a third pin of the plurality of pins; electrically connecting the source contact of the second GaN transistor to a fourth pin of the plurality of pins; and electrically connecting the gate contact of the second GaN transistor to a fifth pin of the plurality of pins. withdrawn
The method of claim 11 further comprising attaching the electronic package to a circuit board, wherein the leadframe is configured to conduct current from the drain contact of the first GaN transistor, the drain contact of the second GaN transistor, the anode contact of the first GaN diode, and the anode contact of the second GaN diode directly to the circuit board. withdrawn
The method of claim 11 wherein: the first GaN transistor comprises a solderable metal stack on the drain contact and a bondable metal stack on each of the source contact and gate contact; and the second GaN transistor comprises a solderable metal stack on the drain contact and a bondable metal stack on each of the source contact and gate contact. withdrawn
The method of claim 11 wherein: the first GaN diode comprises a solderable metal stack on the anode contact and a bondable metal stack on the cathode contact; and the second GaN diode comprises a solderable metal stack on the anode contact and a bondable metal stack on the cathode contact. withdrawn
The method of claim 11 further comprising electrically connecting the source contact of the second GaN transistor to a fifth pin of the plurality of pins. Page 5 of 9 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
co-packaged GaN electronic package (interleaved boost converter)
Materials described outside the worked examples.
gallium nitride (GaN) — transistor
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN 11 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 25–400 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,324,809Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN 11 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
FIG. 2, vertical power transistor 100 includes a 5 GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0041] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5B. Thus, in this design, in addition to integration of transistors and diodes in a single package, inductors are also integrated, reducing 10 footprint …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic package comprising: a leadframe; a plurality of pins; a first gallium nitride (GaN) transistor comprising a source, gate, and drain, wherein the drain of the first GaN transistor is electrically connected to the leadframe; a second GaN transistor comprising a source, gate, and drain, wherein the drain of the second GaN transistor is electrically connected to the leadframe; a first GaN diode comprising an anode and cathode, wherein the anode of the first GaN diode is electrically connected to the leadframe and the cathode of the first GaN diode is wire bonded to an output pin of the plurality of pins; and a second GaN diode comprising an anode and cathode, wherein the anode of the second GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is wire bonded to the output pin of the plurality of pins.
The electronic package of claim 1 wherein: the source of the first GaN transistor is electrically connected to a first pin of the plurality of pins; the gate of the first GaN transistor is electrically connected to a second pin of the plurality of pins; the source of the second GaN transistor is electrically connected to a third pin of the plurality of pins; and the gate of the second GaN transistor is electrically connected to a fourth pin of the plurality of pins.
The electronic package of claim 1 wherein: the electrical connection between the anode of the first diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the anode of the second diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein: the electrical connection between the drain of the second GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the drain of the first GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein the gallium nitride- based electronics package is electrically coupled and attached to a circuit board, wherein the leadframe is configured to conduct current from the drain of the first GaN transistor, the drain of the second GaN transistor, the anode of the first GaN diode, and the anode of the second GaN diode directly to the circuit board.
The electronic package of claim 1 further comprising one or more heat sinks attached to the leadframe.
The electronic package of claim 1 wherein the drain of the first GaN transistor and the drain of the second GaN transistor comprise a solderable metal stack.
The electronic package of claim 1 wherein the source of the first GaN transistor and the source of the second GaN transistor comprise a bondable metal stack.
A method of fabricating an electronic package, the method comprising: providing a package comprising a leadframe and a plurality of pins; Page 3 of 9 App l. No. 14/083,217 PATENT Am dt. dated Response to Office Action of providing a set of gallium nitride (GaN) transistors, each comprising a drain contact, a source contact, and a gate contact; joining the drain contact of a first GaN transistor of the set of GaN transistors and the drain contact of a second GaN transistor of the set of GaN transistors to the leadframe; providing a set of GaN diodes, each comprising an anode contact and a cathode contact; and joining the anode contact of the first GaN diode and the anode contact of the second GaN diode to the leadframe. withdrawn
The method of claim 11 further comprising: electrically connecting the cathode contact of the first GaN diode to a first pin of the plurality of pins; electrically connecting the cathode contact of the second GaN diode to the first pin of the plurality of pins; electrically connecting the source contact of the first GaN transistor to a second pin of the plurality of pins; electrically connecting the gate contact of the first GaN transistor to a third pin of the plurality of pins; electrically connecting the source contact of the second GaN transistor to a fourth pin of the plurality of pins; and electrically connecting the gate contact of the second GaN transistor to a fifth pin of the plurality of pins. withdrawn
The method of claim 11 further comprising attaching the electronic package to a circuit board, wherein the leadframe is configured to conduct current from the drain contact of the first GaN transistor, the drain contact of the second GaN transistor, the anode contact of the first GaN diode, and the anode contact of the second GaN diode directly to the circuit board. withdrawn
The method of claim 11 wherein: the first GaN transistor comprises a solderable metal stack on the drain contact and a bondable metal stack on each of the source contact and gate contact; and the second GaN transistor comprises a solderable metal stack on the drain contact and a bondable metal stack on each of the source contact and gate contact. withdrawn
The method of claim 11 wherein: the first GaN diode comprises a solderable metal stack on the anode contact and a bondable metal stack on the cathode contact; and the second GaN diode comprises a solderable metal stack on the anode contact and a bondable metal stack on the cathode contact. withdrawn
The method of claim 11 further comprising electrically connecting the source contact of the second GaN transistor to a fifth pin of the plurality of pins. Page 5 of 9 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
co-packaged GaN electronic package (interleaved boost converter)
Materials described outside the worked examples.
gallium nitride (GaN) — transistor
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN 11 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 25–400 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,324,809Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. As described, current flow through the GaN 11 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
FIG. 2, vertical power transistor 100 includes a 5 GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0041] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5B. Thus, in this design, in addition to integration of transistors and diodes in a single package, inductors are also integrated, reducing 10 footprint …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic package comprising: a leadframe; a plurality of pins; a first gallium nitride (GaN) transistor comprising a source, gate, and drain, wherein the drain of the first GaN transistor is electrically connected to the leadframe; a second GaN transistor comprising a source, gate, and drain, wherein the drain of the second GaN transistor is electrically connected to the leadframe; a first GaN diode comprising an anode and cathode, wherein the anode of the first GaN diode is electrically connected to the leadframe and the cathode of the first GaN diode is wire bonded to an output pin of the plurality of pins; and a second GaN diode comprising an anode and cathode, wherein the anode of the second GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is wire bonded to the output pin of the plurality of pins.
The electronic package of claim 1 wherein: the source of the first GaN transistor is electrically connected to a first pin of the plurality of pins; the gate of the first GaN transistor is electrically connected to a second pin of the plurality of pins; the source of the second GaN transistor is electrically connected to a third pin of the plurality of pins; and the gate of the second GaN transistor is electrically connected to a fourth pin of the plurality of pins.
The electronic package of claim 1 wherein: the electrical connection between the anode of the first diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the anode of the second diode and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein: the electrical connection between the drain of the second GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder; and the electrical connection between the drain of the first GaN transistor and the leadframe comprises at least one of epoxy, eutectic, sintering, or solder.
The electronic package of claim 1 wherein the gallium nitride- based electronics package is electrically coupled and attached to a circuit board, wherein the leadframe is configured to conduct current from the drain of the first GaN transistor, the drain of the second GaN transistor, the anode of the first GaN diode, and the anode of the second GaN diode directly to the circuit board.
The electronic package of claim 1 further comprising one or more heat sinks attached to the leadframe.
The electronic package of claim 1 wherein the drain of the first GaN transistor and the drain of the second GaN transistor comprise a solderable metal stack.
The electronic package of claim 1 wherein the source of the first GaN transistor and the source of the second GaN transistor comprise a bondable metal stack.
A method of fabricating an electronic package, the method comprising: providing a package comprising a leadframe and a plurality of pins; Page 3 of 9 App l. No. 14/083,217 PATENT Am dt. dated Response to Office Action of providing a set of gallium nitride (GaN) transistors, each comprising a drain contact, a source contact, and a gate contact; joining the drain contact of a first GaN transistor of the set of GaN transistors and the drain contact of a second GaN transistor of the set of GaN transistors to the leadframe; providing a set of GaN diodes, each comprising an anode contact and a cathode contact; and joining the anode contact of the first GaN diode and the anode contact of the second GaN diode to the leadframe. withdrawn
The method of claim 11 further comprising: electrically connecting the cathode contact of the first GaN diode to a first pin of the plurality of pins; electrically connecting the cathode contact of the second GaN diode to the first pin of the plurality of pins; electrically connecting the source contact of the first GaN transistor to a second pin of the plurality of pins; electrically connecting the gate contact of the first GaN transistor to a third pin of the plurality of pins; electrically connecting the source contact of the second GaN transistor to a fourth pin of the plurality of pins; and electrically connecting the gate contact of the second GaN transistor to a fifth pin of the plurality of pins. withdrawn
The method of claim 11 further comprising attaching the electronic package to a circuit board, wherein the leadframe is configured to conduct current from the drain contact of the first GaN transistor, the drain contact of the second GaN transistor, the anode contact of the first GaN diode, and the anode contact of the second GaN diode directly to the circuit board. withdrawn
The method of claim 11 wherein: the first GaN transistor comprises a solderable metal stack on the drain contact and a bondable metal stack on each of the source contact and gate contact; and the second GaN transistor comprises a solderable metal stack on the drain contact and a bondable metal stack on each of the source contact and gate contact. withdrawn
The method of claim 11 wherein: the first GaN diode comprises a solderable metal stack on the anode contact and a bondable metal stack on the cathode contact; and the second GaN diode comprises a solderable metal stack on the anode contact and a bondable metal stack on the cathode contact. withdrawn
The method of claim 11 further comprising electrically connecting the source contact of the second GaN transistor to a fifth pin of the plurality of pins. Page 5 of 9 withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
co-packaged GaN electronic package (interleaved boost converter)
Materials described outside the worked examples.
gallium nitride (GaN) — transistor
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. As described, current flow through the GaN 11 power transistor occurs in a substantially vertical direction (referenced to the horizontal bottom surface …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 25–400 nm | — |
Related documents with shared materials, methods, properties, or citations.
FIG. 2, vertical power transistor 100 includes a 5 GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0041] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5B. Thus, in this design, in addition to integration of transistors and diodes in a single package, inductors are also integrated, reducing 10 footprint …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
FIG. 2, vertical power transistor 100 includes a 5 GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0041] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5B. Thus, in this design, in addition to integration of transistors and diodes in a single package, inductors are also integrated, reducing 10 footprint …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
FIG. 2, vertical power transistor 100 includes a 5 GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0041] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5B. Thus, in this design, in addition to integration of transistors and diodes in a single package, inductors are also integrated, reducing 10 footprint …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …
FIG. 2, vertical power transistor 100 includes a 5 GaN substrate 202. A first GaN epitaxial layer 102 is coupled to and disposed over a surface of GaN substrate …
FIG. 3, the tops of finger-like projections 118 may be recessed below the tops of source regions 304 to provide electrical isolation. [0041] In some …
FIG. 4 illustrates a cross-sectional view of vertical GaN power diode 400 including GaN substrate 406 and first GaN epitaxial layer 404. Similar to the vertical …
FIG. 5B. Thus, in this design, in addition to integration of transistors and diodes in a single package, inductors are also integrated, reducing 10 footprint …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a GaN- based electronics package where a set of vertical GaN transistors are co-packaged …