Patent
US 10,727,834LEVEL SHIFTER FOR HALF BRIDGE GaN DRIVER APPLICATIONS
Edward Lee
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 10,727,834Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a schematic of a conventional half bridge integrated circuit with a level shifter. [0017]
FIG. 2 illustrates a schematic of a conventional direct-coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
FIG. 3 illustrates a schematic of a conventional capacitively coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
FIG. 4 illustrates a direct-coupled level shifter according to an exemplary embodiment of the present invention. [0020]
FIG. 5 illustrates a positive level shift driver according to an exemplary embodiment of the present invention for inclusion in the direct-coupled level …
FIG. 6 illustrates a negative level shift driver according to an exemplary embodiment of the present invention for inclusion in the direct-coupled level …
FIG. 7 illustrates a pulse generator for inclusion in the direct-coupled level shifter shown in
FIG. 8 illustrates a latch for inclusion in the direct-coupled level shifter shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A direct-coupled level shifter for generating a level shifted control signal from a ground referenced control signal, comprising: a first set of level shift drivers for generating a first output and comprising a positive level shift driver configured to receive the control signal and a negative level shift driver configured to receive an inverse of the control signal; and a second set of level shift drivers for generating a second output and comprising a positive level shift driver configured to receive the inverse of the control signal and a negative level shift driver configured to receive the control signal, wherein: the positive level shift drivers in the first and second sets of level shift drivers are referenced to ground and are configured to generate the first and second outputs, respectively, if a reference voltage is positive, and turn off if the reference voltage is negative, and the negative level shift drivers in the first and second sets of level shift drivers are referenced to ground and the reference voltage and are configured to generate the first and second outputs, respectively, if the reference voltage is negative, and turn off if the reference voltage is positive.
The direct-coupled level shifter of claim 1, further comprising a latch circuit for receiving the first output and providing the level shifted control signal based on the first output.
The direct-coupled level shifter of claim 1, further comprising: a pulse filter for receiving the first output and providing an output; and an SR flip-flop for receiving the output of the pulse filter and providing the level shifted control signal.
The direct-coupled level shifter of claim 1, wherein each of the first and second sets of level shift drivers further comprises a pulse generator for generating a short pulse in response to a logic signal transition in the control signal or the inverse of the control signal, respectively.
The direct-coupled level shifter of claim 1, further comprising an inverter for generating the inverse of the control signal.
The direct-coupled level shifter of claim 1, wherein the positive level shift driver comprises: a first set of at least one gallium nitride (G aN) field effect transistor (FET) configured as a diode and connected in series for receiving the reference voltage; a first resistor having a first terminal connected to the first set of GaN FETs and a second terminal connected to a node; a second resistor having a first terminal connected to the node and a second terminal configured to receive a supply voltage; a first GaN FET having a gate terminal connected to the node, a source terminal, and a drain terminal, wherein the first resistor and the first set of GaN FETs are configured to produce a voltage difference between the reference voltage and a voltage on the node sufficient to turn on the first GaN FET if the reference voltage is positive; and a second G aN FET for allowing or blocking the first output based on the control signal or the second output based on the inverse of the control signal, respectively, and having a drain terminal connected to the source terminal of the first GaN FET, a source terminal, and a gate terminal for receiving the control signal or the inverse of the control signal, respectively.
The direct-coupled level shifter of claim 1, wherein the negative level shift driver comprises: a first gallium nitride (GaN) field effect transistor (FET) for allowing or blocking the first output based on the inverse of the control signal or the second output based on the control signal, respectively, and having a drain terminal, a source terminal, and a gate terminal for receiving the inverse of the control signal or the control signal, respectively; a logic level translator connected to the drain terminal of the first GaN F ET and configured to receive the reference voltage, a first supply voltage, and a second supply voltage, wherein the second supply voltage is greater than or equal to the first supply voltage, wherein the logic level translator is further connected to a node; and a second F ET having a source terminal for receiving the reference voltage, a drain terminal, and a gate terminal connected to the node, wherein the logic level translator is configured to produce a voltage difference between the reference voltage and a voltage on the node sufficient to turn on the second F ET in response to the reference voltage being less than a predetermined voltage and based on the inverse of the control signal or the control signal, respectively.
Layer stacks claimed or described, ordered top of device to substrate.
direct-coupled level shifter
No layer stack recorded.
positive level shift driver with GaN FETs
negative level shift driver with GaN FETs
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a schematic of a conventional direct-coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,727,834Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a schematic of a conventional half bridge integrated circuit with a level shifter. [0017]
FIG. 2 illustrates a schematic of a conventional direct-coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
FIG. 3 illustrates a schematic of a conventional capacitively coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
FIG. 4 illustrates a direct-coupled level shifter according to an exemplary embodiment of the present invention. [0020]
FIG. 5 illustrates a positive level shift driver according to an exemplary embodiment of the present invention for inclusion in the direct-coupled level …
FIG. 6 illustrates a negative level shift driver according to an exemplary embodiment of the present invention for inclusion in the direct-coupled level …
FIG. 7 illustrates a pulse generator for inclusion in the direct-coupled level shifter shown in
FIG. 8 illustrates a latch for inclusion in the direct-coupled level shifter shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A direct-coupled level shifter for generating a level shifted control signal from a ground referenced control signal, comprising: a first set of level shift drivers for generating a first output and comprising a positive level shift driver configured to receive the control signal and a negative level shift driver configured to receive an inverse of the control signal; and a second set of level shift drivers for generating a second output and comprising a positive level shift driver configured to receive the inverse of the control signal and a negative level shift driver configured to receive the control signal, wherein: the positive level shift drivers in the first and second sets of level shift drivers are referenced to ground and are configured to generate the first and second outputs, respectively, if a reference voltage is positive, and turn off if the reference voltage is negative, and the negative level shift drivers in the first and second sets of level shift drivers are referenced to ground and the reference voltage and are configured to generate the first and second outputs, respectively, if the reference voltage is negative, and turn off if the reference voltage is positive.
The direct-coupled level shifter of claim 1, further comprising a latch circuit for receiving the first output and providing the level shifted control signal based on the first output.
The direct-coupled level shifter of claim 1, further comprising: a pulse filter for receiving the first output and providing an output; and an SR flip-flop for receiving the output of the pulse filter and providing the level shifted control signal.
The direct-coupled level shifter of claim 1, wherein each of the first and second sets of level shift drivers further comprises a pulse generator for generating a short pulse in response to a logic signal transition in the control signal or the inverse of the control signal, respectively.
The direct-coupled level shifter of claim 1, further comprising an inverter for generating the inverse of the control signal.
The direct-coupled level shifter of claim 1, wherein the positive level shift driver comprises: a first set of at least one gallium nitride (G aN) field effect transistor (FET) configured as a diode and connected in series for receiving the reference voltage; a first resistor having a first terminal connected to the first set of GaN FETs and a second terminal connected to a node; a second resistor having a first terminal connected to the node and a second terminal configured to receive a supply voltage; a first GaN FET having a gate terminal connected to the node, a source terminal, and a drain terminal, wherein the first resistor and the first set of GaN FETs are configured to produce a voltage difference between the reference voltage and a voltage on the node sufficient to turn on the first GaN FET if the reference voltage is positive; and a second G aN FET for allowing or blocking the first output based on the control signal or the second output based on the inverse of the control signal, respectively, and having a drain terminal connected to the source terminal of the first GaN FET, a source terminal, and a gate terminal for receiving the control signal or the inverse of the control signal, respectively.
The direct-coupled level shifter of claim 1, wherein the negative level shift driver comprises: a first gallium nitride (GaN) field effect transistor (FET) for allowing or blocking the first output based on the inverse of the control signal or the second output based on the control signal, respectively, and having a drain terminal, a source terminal, and a gate terminal for receiving the inverse of the control signal or the control signal, respectively; a logic level translator connected to the drain terminal of the first GaN F ET and configured to receive the reference voltage, a first supply voltage, and a second supply voltage, wherein the second supply voltage is greater than or equal to the first supply voltage, wherein the logic level translator is further connected to a node; and a second F ET having a source terminal for receiving the reference voltage, a drain terminal, and a gate terminal connected to the node, wherein the logic level translator is configured to produce a voltage difference between the reference voltage and a voltage on the node sufficient to turn on the second F ET in response to the reference voltage being less than a predetermined voltage and based on the inverse of the control signal or the control signal, respectively.
Layer stacks claimed or described, ordered top of device to substrate.
direct-coupled level shifter
No layer stack recorded.
positive level shift driver with GaN FETs
negative level shift driver with GaN FETs
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a schematic of a conventional direct-coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,727,834Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a schematic of a conventional half bridge integrated circuit with a level shifter. [0017]
FIG. 2 illustrates a schematic of a conventional direct-coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
FIG. 3 illustrates a schematic of a conventional capacitively coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
FIG. 4 illustrates a direct-coupled level shifter according to an exemplary embodiment of the present invention. [0020]
FIG. 5 illustrates a positive level shift driver according to an exemplary embodiment of the present invention for inclusion in the direct-coupled level …
FIG. 6 illustrates a negative level shift driver according to an exemplary embodiment of the present invention for inclusion in the direct-coupled level …
FIG. 7 illustrates a pulse generator for inclusion in the direct-coupled level shifter shown in
FIG. 8 illustrates a latch for inclusion in the direct-coupled level shifter shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A direct-coupled level shifter for generating a level shifted control signal from a ground referenced control signal, comprising: a first set of level shift drivers for generating a first output and comprising a positive level shift driver configured to receive the control signal and a negative level shift driver configured to receive an inverse of the control signal; and a second set of level shift drivers for generating a second output and comprising a positive level shift driver configured to receive the inverse of the control signal and a negative level shift driver configured to receive the control signal, wherein: the positive level shift drivers in the first and second sets of level shift drivers are referenced to ground and are configured to generate the first and second outputs, respectively, if a reference voltage is positive, and turn off if the reference voltage is negative, and the negative level shift drivers in the first and second sets of level shift drivers are referenced to ground and the reference voltage and are configured to generate the first and second outputs, respectively, if the reference voltage is negative, and turn off if the reference voltage is positive.
The direct-coupled level shifter of claim 1, further comprising a latch circuit for receiving the first output and providing the level shifted control signal based on the first output.
The direct-coupled level shifter of claim 1, further comprising: a pulse filter for receiving the first output and providing an output; and an SR flip-flop for receiving the output of the pulse filter and providing the level shifted control signal.
The direct-coupled level shifter of claim 1, wherein each of the first and second sets of level shift drivers further comprises a pulse generator for generating a short pulse in response to a logic signal transition in the control signal or the inverse of the control signal, respectively.
The direct-coupled level shifter of claim 1, further comprising an inverter for generating the inverse of the control signal.
The direct-coupled level shifter of claim 1, wherein the positive level shift driver comprises: a first set of at least one gallium nitride (G aN) field effect transistor (FET) configured as a diode and connected in series for receiving the reference voltage; a first resistor having a first terminal connected to the first set of GaN FETs and a second terminal connected to a node; a second resistor having a first terminal connected to the node and a second terminal configured to receive a supply voltage; a first GaN FET having a gate terminal connected to the node, a source terminal, and a drain terminal, wherein the first resistor and the first set of GaN FETs are configured to produce a voltage difference between the reference voltage and a voltage on the node sufficient to turn on the first GaN FET if the reference voltage is positive; and a second G aN FET for allowing or blocking the first output based on the control signal or the second output based on the inverse of the control signal, respectively, and having a drain terminal connected to the source terminal of the first GaN FET, a source terminal, and a gate terminal for receiving the control signal or the inverse of the control signal, respectively.
The direct-coupled level shifter of claim 1, wherein the negative level shift driver comprises: a first gallium nitride (GaN) field effect transistor (FET) for allowing or blocking the first output based on the inverse of the control signal or the second output based on the control signal, respectively, and having a drain terminal, a source terminal, and a gate terminal for receiving the inverse of the control signal or the control signal, respectively; a logic level translator connected to the drain terminal of the first GaN F ET and configured to receive the reference voltage, a first supply voltage, and a second supply voltage, wherein the second supply voltage is greater than or equal to the first supply voltage, wherein the logic level translator is further connected to a node; and a second F ET having a source terminal for receiving the reference voltage, a drain terminal, and a gate terminal connected to the node, wherein the logic level translator is configured to produce a voltage difference between the reference voltage and a voltage on the node sufficient to turn on the second F ET in response to the reference voltage being less than a predetermined voltage and based on the inverse of the control signal or the control signal, respectively.
Layer stacks claimed or described, ordered top of device to substrate.
direct-coupled level shifter
No layer stack recorded.
positive level shift driver with GaN FETs
negative level shift driver with GaN FETs
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a schematic of a conventional direct-coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,727,834Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a schematic of a conventional half bridge integrated circuit with a level shifter. [0017]
FIG. 2 illustrates a schematic of a conventional direct-coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
FIG. 3 illustrates a schematic of a conventional capacitively coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
FIG. 4 illustrates a direct-coupled level shifter according to an exemplary embodiment of the present invention. [0020]
FIG. 5 illustrates a positive level shift driver according to an exemplary embodiment of the present invention for inclusion in the direct-coupled level …
FIG. 6 illustrates a negative level shift driver according to an exemplary embodiment of the present invention for inclusion in the direct-coupled level …
FIG. 7 illustrates a pulse generator for inclusion in the direct-coupled level shifter shown in
FIG. 8 illustrates a latch for inclusion in the direct-coupled level shifter shown in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A direct-coupled level shifter for generating a level shifted control signal from a ground referenced control signal, comprising: a first set of level shift drivers for generating a first output and comprising a positive level shift driver configured to receive the control signal and a negative level shift driver configured to receive an inverse of the control signal; and a second set of level shift drivers for generating a second output and comprising a positive level shift driver configured to receive the inverse of the control signal and a negative level shift driver configured to receive the control signal, wherein: the positive level shift drivers in the first and second sets of level shift drivers are referenced to ground and are configured to generate the first and second outputs, respectively, if a reference voltage is positive, and turn off if the reference voltage is negative, and the negative level shift drivers in the first and second sets of level shift drivers are referenced to ground and the reference voltage and are configured to generate the first and second outputs, respectively, if the reference voltage is negative, and turn off if the reference voltage is positive.
The direct-coupled level shifter of claim 1, further comprising a latch circuit for receiving the first output and providing the level shifted control signal based on the first output.
The direct-coupled level shifter of claim 1, further comprising: a pulse filter for receiving the first output and providing an output; and an SR flip-flop for receiving the output of the pulse filter and providing the level shifted control signal.
The direct-coupled level shifter of claim 1, wherein each of the first and second sets of level shift drivers further comprises a pulse generator for generating a short pulse in response to a logic signal transition in the control signal or the inverse of the control signal, respectively.
The direct-coupled level shifter of claim 1, further comprising an inverter for generating the inverse of the control signal.
The direct-coupled level shifter of claim 1, wherein the positive level shift driver comprises: a first set of at least one gallium nitride (G aN) field effect transistor (FET) configured as a diode and connected in series for receiving the reference voltage; a first resistor having a first terminal connected to the first set of GaN FETs and a second terminal connected to a node; a second resistor having a first terminal connected to the node and a second terminal configured to receive a supply voltage; a first GaN FET having a gate terminal connected to the node, a source terminal, and a drain terminal, wherein the first resistor and the first set of GaN FETs are configured to produce a voltage difference between the reference voltage and a voltage on the node sufficient to turn on the first GaN FET if the reference voltage is positive; and a second G aN FET for allowing or blocking the first output based on the control signal or the second output based on the inverse of the control signal, respectively, and having a drain terminal connected to the source terminal of the first GaN FET, a source terminal, and a gate terminal for receiving the control signal or the inverse of the control signal, respectively.
The direct-coupled level shifter of claim 1, wherein the negative level shift driver comprises: a first gallium nitride (GaN) field effect transistor (FET) for allowing or blocking the first output based on the inverse of the control signal or the second output based on the control signal, respectively, and having a drain terminal, a source terminal, and a gate terminal for receiving the inverse of the control signal or the control signal, respectively; a logic level translator connected to the drain terminal of the first GaN F ET and configured to receive the reference voltage, a first supply voltage, and a second supply voltage, wherein the second supply voltage is greater than or equal to the first supply voltage, wherein the logic level translator is further connected to a node; and a second F ET having a source terminal for receiving the reference voltage, a drain terminal, and a gate terminal connected to the node, wherein the logic level translator is configured to produce a voltage difference between the reference voltage and a voltage on the node sufficient to turn on the second F ET in response to the reference voltage being less than a predetermined voltage and based on the inverse of the control signal or the control signal, respectively.
Layer stacks claimed or described, ordered top of device to substrate.
direct-coupled level shifter
No layer stack recorded.
positive level shift driver with GaN FETs
negative level shift driver with GaN FETs
Materials described outside the worked examples.
gallium nitride
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a schematic of a conventional direct-coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
Related documents with shared materials, methods, properties, or citations.
FIG. 3 illustrates a schematic of a conventional capacitively coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
GAN DRIVER USING ACTIVE PRE-DRIVER WITH FEEDBACK
FIG. 3 illustrates a schematic of a conventional capacitively coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
GAN DRIVER USING ACTIVE PRE-DRIVER WITH FEEDBACK
FIG. 3 illustrates a schematic of a conventional capacitively coupled level shifter for a gate driver associated with a high side transistor in a half bridge …
GAN DRIVER USING ACTIVE PRE-DRIVER WITH FEEDBACK
FIG. 3 illustrates a schematic of a conventional capacitively coupled level shifter for a gate driver associated with a high side transistor in a half bridge …