Patent
US 9,502,544METHOD AND SYSTEM FOR PLANAR REGROWTH IN GAN ELECTRONIC DEVICES
Isik C. Kizilyalli
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,502,544Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the substrate is an n- type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
FIG. 2B. An angle a of greater than 90 degrees can facilitate deposition and/or 20 regrowth of subsequent layers and can help improve performance by enabling …
FIG. 3. Formation of an etch/regrowth mask, etching of the via for the 20 plug, as well as the regrowth process is not illustrated for purposes of clarity and …
FIG. 4 is a simplified schematic diagram illustrating a planar regrown resistor structure according to an embodiment of the present invention. As illustrated in
FIG. 5 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. In some …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a vertical JFET with regrown gate regions according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical JFET comprising: a III -nitride substrate; and a I II -nitride epitaxial structure coupled to the I II -nitride substrate, wherein the III- nitride epitaxial structure comprises: a plurality of channels of a first conductivity type, wherein each of the channels comprises an interface surface, a plurality of sources of the first conductivity type, wherein each of the sources comprises a contact surface contacting an interface surface of the channels, and a plurality of epitaxially grown gates interleaved with the channels, wherein an upper surface of the gates is substantially coplanar with the contact surfaces of the sources.
The vertical JFET of claim 1, further comprising: a plurality of source contacts, wherein each source contact is electrically coupled to one of the sources; and a plurality of gate contacts, wherein each gate contact is electrically coupled to one of the regrown gates.
The vertical JFET of claim 1, further comprising a drain contact electrically coupled to the I II-nitride substrate.
The vertical JFET of claim 1, wherein the first conductivity type is n type and the gates are p type.
The vertical JFET of claim 1, wherein the channels are disposed between the gates such that current flow during operation of the vertical JFET is along a direction orthogonal to the upper surface of the set of regrown gates. 20 KILPATRICK TOWNSEND 67566975 1
The vertical JF E T of claim 1, wherein the I II -nitride substrate comprises an n-type substrate.
The vertical JF E T of claim 1, wherein a width of the channels measured along a direction orthogonal to a thickness of the I II -nitride epitaxial layer is less than 5 pm.
The vertical JF E T of claim 1, wherein the gates comprise a p-type III- nitride material.
The vertical JF E T of claim 1, wherein the gates are f u rther electrically coupled to a drift region.
The vertical JF E T of claim 1, wherein the channels have a first dopant concentration and the gates have a second dopant concentration.
A method of manufacturing a vertical JF E T, the method comprising: providing a III -nitride substrate; and forming a III -nitride epitaxial structure on the I II -nitride substrate, wherein the III -nitride epitaxial structure comprises: a plurality of channels of a first conductivity type, wherein each of the channels comprises an interface surface, a plurality of sources of the first conductivity type, wherein each of the sources comprises a contact surface contacting an interface surface of the channels, and a plurality of epitaxially grown gates interleaved with the channels, wherein an upper surface of the gates is substantially coplanar with the contact surfaces of the sources. 21 KILPATRICK TOWNSEND 67566975 1
The method of claim 12, further comprising: forming a plurality of source contacts, wherein each source contact is electrically coupled to one of the sources; and forming a plurality of gate contacts, wherein each gate contact is electrically coupled to one of the regrown gates.
The method of claim 12, further comprising forming a drain contact electrically coupled to the I II -nitride substrate.
The method of claim 12, wherein the first conductivity type is n type and the gates are p type.
The method of claim 12, wherein the channels are disposed between the gates such that current flow during operation of the vertical JF E T is along a direction orthogonal to the upper surface of the set of regrown gates.
The method of claim 12, wherein the I II -nitride substrate comprises an n- type substrate.
The method of claim 12, wherein a width of the channels measured along a direction orthogonal to a thickness of the I II -nitride epitaxial layer is less than 5 pm.
The method of claim 12, wherein the gates comprise a p-type I II -nitride material.
The method of claim 12, wherein the gates are f u rther electrically coupled to a drift region.
The method of claim 12, wherein the channels have a first dopant concentration and the gates have a second dopant concentration. 22 KILPATRICK TOWNSEND 67566975 1
Layer stacks claimed or described, ordered top of device to substrate.
vertical JFET
Materials described outside the worked examples.
III-nitride substrate
III-nitride epitaxial structure
p-type III-nitride gate material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the substrate is an n- type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,502,544Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the substrate is an n- type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
FIG. 2B. An angle a of greater than 90 degrees can facilitate deposition and/or 20 regrowth of subsequent layers and can help improve performance by enabling …
FIG. 3. Formation of an etch/regrowth mask, etching of the via for the 20 plug, as well as the regrowth process is not illustrated for purposes of clarity and …
FIG. 4 is a simplified schematic diagram illustrating a planar regrown resistor structure according to an embodiment of the present invention. As illustrated in
FIG. 5 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. In some …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a vertical JFET with regrown gate regions according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical JFET comprising: a III -nitride substrate; and a I II -nitride epitaxial structure coupled to the I II -nitride substrate, wherein the III- nitride epitaxial structure comprises: a plurality of channels of a first conductivity type, wherein each of the channels comprises an interface surface, a plurality of sources of the first conductivity type, wherein each of the sources comprises a contact surface contacting an interface surface of the channels, and a plurality of epitaxially grown gates interleaved with the channels, wherein an upper surface of the gates is substantially coplanar with the contact surfaces of the sources.
The vertical JFET of claim 1, further comprising: a plurality of source contacts, wherein each source contact is electrically coupled to one of the sources; and a plurality of gate contacts, wherein each gate contact is electrically coupled to one of the regrown gates.
The vertical JFET of claim 1, further comprising a drain contact electrically coupled to the I II-nitride substrate.
The vertical JFET of claim 1, wherein the first conductivity type is n type and the gates are p type.
The vertical JFET of claim 1, wherein the channels are disposed between the gates such that current flow during operation of the vertical JFET is along a direction orthogonal to the upper surface of the set of regrown gates. 20 KILPATRICK TOWNSEND 67566975 1
The vertical JF E T of claim 1, wherein the I II -nitride substrate comprises an n-type substrate.
The vertical JF E T of claim 1, wherein a width of the channels measured along a direction orthogonal to a thickness of the I II -nitride epitaxial layer is less than 5 pm.
The vertical JF E T of claim 1, wherein the gates comprise a p-type III- nitride material.
The vertical JF E T of claim 1, wherein the gates are f u rther electrically coupled to a drift region.
The vertical JF E T of claim 1, wherein the channels have a first dopant concentration and the gates have a second dopant concentration.
A method of manufacturing a vertical JF E T, the method comprising: providing a III -nitride substrate; and forming a III -nitride epitaxial structure on the I II -nitride substrate, wherein the III -nitride epitaxial structure comprises: a plurality of channels of a first conductivity type, wherein each of the channels comprises an interface surface, a plurality of sources of the first conductivity type, wherein each of the sources comprises a contact surface contacting an interface surface of the channels, and a plurality of epitaxially grown gates interleaved with the channels, wherein an upper surface of the gates is substantially coplanar with the contact surfaces of the sources. 21 KILPATRICK TOWNSEND 67566975 1
The method of claim 12, further comprising: forming a plurality of source contacts, wherein each source contact is electrically coupled to one of the sources; and forming a plurality of gate contacts, wherein each gate contact is electrically coupled to one of the regrown gates.
The method of claim 12, further comprising forming a drain contact electrically coupled to the I II -nitride substrate.
The method of claim 12, wherein the first conductivity type is n type and the gates are p type.
The method of claim 12, wherein the channels are disposed between the gates such that current flow during operation of the vertical JF E T is along a direction orthogonal to the upper surface of the set of regrown gates.
The method of claim 12, wherein the I II -nitride substrate comprises an n- type substrate.
The method of claim 12, wherein a width of the channels measured along a direction orthogonal to a thickness of the I II -nitride epitaxial layer is less than 5 pm.
The method of claim 12, wherein the gates comprise a p-type I II -nitride material.
The method of claim 12, wherein the gates are f u rther electrically coupled to a drift region.
The method of claim 12, wherein the channels have a first dopant concentration and the gates have a second dopant concentration. 22 KILPATRICK TOWNSEND 67566975 1
Layer stacks claimed or described, ordered top of device to substrate.
vertical JFET
Materials described outside the worked examples.
III-nitride substrate
III-nitride epitaxial structure
p-type III-nitride gate material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the substrate is an n- type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,502,544Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the substrate is an n- type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
FIG. 2B. An angle a of greater than 90 degrees can facilitate deposition and/or 20 regrowth of subsequent layers and can help improve performance by enabling …
FIG. 3. Formation of an etch/regrowth mask, etching of the via for the 20 plug, as well as the regrowth process is not illustrated for purposes of clarity and …
FIG. 4 is a simplified schematic diagram illustrating a planar regrown resistor structure according to an embodiment of the present invention. As illustrated in
FIG. 5 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. In some …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a vertical JFET with regrown gate regions according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical JFET comprising: a III -nitride substrate; and a I II -nitride epitaxial structure coupled to the I II -nitride substrate, wherein the III- nitride epitaxial structure comprises: a plurality of channels of a first conductivity type, wherein each of the channels comprises an interface surface, a plurality of sources of the first conductivity type, wherein each of the sources comprises a contact surface contacting an interface surface of the channels, and a plurality of epitaxially grown gates interleaved with the channels, wherein an upper surface of the gates is substantially coplanar with the contact surfaces of the sources.
The vertical JFET of claim 1, further comprising: a plurality of source contacts, wherein each source contact is electrically coupled to one of the sources; and a plurality of gate contacts, wherein each gate contact is electrically coupled to one of the regrown gates.
The vertical JFET of claim 1, further comprising a drain contact electrically coupled to the I II-nitride substrate.
The vertical JFET of claim 1, wherein the first conductivity type is n type and the gates are p type.
The vertical JFET of claim 1, wherein the channels are disposed between the gates such that current flow during operation of the vertical JFET is along a direction orthogonal to the upper surface of the set of regrown gates. 20 KILPATRICK TOWNSEND 67566975 1
The vertical JF E T of claim 1, wherein the I II -nitride substrate comprises an n-type substrate.
The vertical JF E T of claim 1, wherein a width of the channels measured along a direction orthogonal to a thickness of the I II -nitride epitaxial layer is less than 5 pm.
The vertical JF E T of claim 1, wherein the gates comprise a p-type III- nitride material.
The vertical JF E T of claim 1, wherein the gates are f u rther electrically coupled to a drift region.
The vertical JF E T of claim 1, wherein the channels have a first dopant concentration and the gates have a second dopant concentration.
A method of manufacturing a vertical JF E T, the method comprising: providing a III -nitride substrate; and forming a III -nitride epitaxial structure on the I II -nitride substrate, wherein the III -nitride epitaxial structure comprises: a plurality of channels of a first conductivity type, wherein each of the channels comprises an interface surface, a plurality of sources of the first conductivity type, wherein each of the sources comprises a contact surface contacting an interface surface of the channels, and a plurality of epitaxially grown gates interleaved with the channels, wherein an upper surface of the gates is substantially coplanar with the contact surfaces of the sources. 21 KILPATRICK TOWNSEND 67566975 1
The method of claim 12, further comprising: forming a plurality of source contacts, wherein each source contact is electrically coupled to one of the sources; and forming a plurality of gate contacts, wherein each gate contact is electrically coupled to one of the regrown gates.
The method of claim 12, further comprising forming a drain contact electrically coupled to the I II -nitride substrate.
The method of claim 12, wherein the first conductivity type is n type and the gates are p type.
The method of claim 12, wherein the channels are disposed between the gates such that current flow during operation of the vertical JF E T is along a direction orthogonal to the upper surface of the set of regrown gates.
The method of claim 12, wherein the I II -nitride substrate comprises an n- type substrate.
The method of claim 12, wherein a width of the channels measured along a direction orthogonal to a thickness of the I II -nitride epitaxial layer is less than 5 pm.
The method of claim 12, wherein the gates comprise a p-type I II -nitride material.
The method of claim 12, wherein the gates are f u rther electrically coupled to a drift region.
The method of claim 12, wherein the channels have a first dopant concentration and the gates have a second dopant concentration. 22 KILPATRICK TOWNSEND 67566975 1
Layer stacks claimed or described, ordered top of device to substrate.
vertical JFET
Materials described outside the worked examples.
III-nitride substrate
III-nitride epitaxial structure
p-type III-nitride gate material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the substrate is an n- type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,502,544Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the substrate is an n- type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
FIG. 2B. An angle a of greater than 90 degrees can facilitate deposition and/or 20 regrowth of subsequent layers and can help improve performance by enabling …
FIG. 3. Formation of an etch/regrowth mask, etching of the via for the 20 plug, as well as the regrowth process is not illustrated for purposes of clarity and …
FIG. 4 is a simplified schematic diagram illustrating a planar regrown resistor structure according to an embodiment of the present invention. As illustrated in
FIG. 5 is a simplified flowchart illustrating a method of fabricating an electronic device according to an embodiment of the present invention. In some …
FIG. 6 is a simplified flowchart illustrating a method of fabricating a vertical JFET with regrown gate regions according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A vertical JFET comprising: a III -nitride substrate; and a I II -nitride epitaxial structure coupled to the I II -nitride substrate, wherein the III- nitride epitaxial structure comprises: a plurality of channels of a first conductivity type, wherein each of the channels comprises an interface surface, a plurality of sources of the first conductivity type, wherein each of the sources comprises a contact surface contacting an interface surface of the channels, and a plurality of epitaxially grown gates interleaved with the channels, wherein an upper surface of the gates is substantially coplanar with the contact surfaces of the sources.
The vertical JFET of claim 1, further comprising: a plurality of source contacts, wherein each source contact is electrically coupled to one of the sources; and a plurality of gate contacts, wherein each gate contact is electrically coupled to one of the regrown gates.
The vertical JFET of claim 1, further comprising a drain contact electrically coupled to the I II-nitride substrate.
The vertical JFET of claim 1, wherein the first conductivity type is n type and the gates are p type.
The vertical JFET of claim 1, wherein the channels are disposed between the gates such that current flow during operation of the vertical JFET is along a direction orthogonal to the upper surface of the set of regrown gates. 20 KILPATRICK TOWNSEND 67566975 1
The vertical JF E T of claim 1, wherein the I II -nitride substrate comprises an n-type substrate.
The vertical JF E T of claim 1, wherein a width of the channels measured along a direction orthogonal to a thickness of the I II -nitride epitaxial layer is less than 5 pm.
The vertical JF E T of claim 1, wherein the gates comprise a p-type III- nitride material.
The vertical JF E T of claim 1, wherein the gates are f u rther electrically coupled to a drift region.
The vertical JF E T of claim 1, wherein the channels have a first dopant concentration and the gates have a second dopant concentration.
A method of manufacturing a vertical JF E T, the method comprising: providing a III -nitride substrate; and forming a III -nitride epitaxial structure on the I II -nitride substrate, wherein the III -nitride epitaxial structure comprises: a plurality of channels of a first conductivity type, wherein each of the channels comprises an interface surface, a plurality of sources of the first conductivity type, wherein each of the sources comprises a contact surface contacting an interface surface of the channels, and a plurality of epitaxially grown gates interleaved with the channels, wherein an upper surface of the gates is substantially coplanar with the contact surfaces of the sources. 21 KILPATRICK TOWNSEND 67566975 1
The method of claim 12, further comprising: forming a plurality of source contacts, wherein each source contact is electrically coupled to one of the sources; and forming a plurality of gate contacts, wherein each gate contact is electrically coupled to one of the regrown gates.
The method of claim 12, further comprising forming a drain contact electrically coupled to the I II -nitride substrate.
The method of claim 12, wherein the first conductivity type is n type and the gates are p type.
The method of claim 12, wherein the channels are disposed between the gates such that current flow during operation of the vertical JF E T is along a direction orthogonal to the upper surface of the set of regrown gates.
The method of claim 12, wherein the I II -nitride substrate comprises an n- type substrate.
The method of claim 12, wherein a width of the channels measured along a direction orthogonal to a thickness of the I II -nitride epitaxial layer is less than 5 pm.
The method of claim 12, wherein the gates comprise a p-type I II -nitride material.
The method of claim 12, wherein the gates are f u rther electrically coupled to a drift region.
The method of claim 12, wherein the channels have a first dopant concentration and the gates have a second dopant concentration. 22 KILPATRICK TOWNSEND 67566975 1
Layer stacks claimed or described, ordered top of device to substrate.
vertical JFET
Materials described outside the worked examples.
III-nitride substrate
III-nitride epitaxial structure
p-type III-nitride gate material
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the substrate is an n- type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | ≥ 1 V | — |
Related documents with shared materials, methods, properties, or citations.
gallium nitride (GaN)
GaN
FIG. 2B. An angle a of greater than 90 degrees can facilitate deposition and/or 20 regrowth of subsequent layers and can help improve performance by enabling …
FIG. 4 is a simplified schematic diagram illustrating a planar regrown resistor structure according to an embodiment of the present invention. As illustrated in
gallium nitride (GaN)
GaN
FIG. 2B. An angle a of greater than 90 degrees can facilitate deposition and/or 20 regrowth of subsequent layers and can help improve performance by enabling …
FIG. 4 is a simplified schematic diagram illustrating a planar regrown resistor structure according to an embodiment of the present invention. As illustrated in
gallium nitride (GaN)
GaN
FIG. 2B. An angle a of greater than 90 degrees can facilitate deposition and/or 20 regrowth of subsequent layers and can help improve performance by enabling …
FIG. 4 is a simplified schematic diagram illustrating a planar regrown resistor structure according to an embodiment of the present invention. As illustrated in
gallium nitride (GaN)
GaN
FIG. 2B. An angle a of greater than 90 degrees can facilitate deposition and/or 20 regrowth of subsequent layers and can help improve performance by enabling …
FIG. 4 is a simplified schematic diagram illustrating a planar regrown resistor structure according to an embodiment of the present invention. As illustrated in